Alex Forencich
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f920e56348
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eth: Add frame length enforcement and additional statistics outputs to taxi_axis_baser_rx_64
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-04-07 23:37:29 -07:00 |
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Alex Forencich
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df87998a1b
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eth: Clean up error detection logic in combined MAC/PCS
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-27 09:33:56 -07:00 |
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Alex Forencich
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bec324dc03
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eth: Fix bugs in 10G MAC RX related to short IFGs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-26 23:03:57 -07:00 |
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Alex Forencich
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7f2ecf9b49
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eth: Implement RX sequence error reporting in MAC+PHY module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-22 10:16:32 -08:00 |
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Alex Forencich
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422c54229e
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eth: Split block type checks in MAC+PHY to reduce fanin
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-22 10:02:08 -08:00 |
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Alex Forencich
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8f6a99112b
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eth: Add missing block types to MAC+PHY logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-22 09:55:28 -08:00 |
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Alex Forencich
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e3f047d735
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eth: Add AXI stream 64-bit BASE-R Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-07 16:27:27 -08:00 |
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