Update readme

Signed-off-by: Alex Forencich <alex@alexforencich.com>

README.md

@@ -232,6 +232,10 @@ Example designs are provided for several different FPGA boards, showcasing many
 *  HiTech Global HTG-ZRF8-R2 (Xilinx Zynq UltraScale+ RFSoC XCZU28DR/XCZU48DR)
 *  HiTech Global HTG-ZRF8-EM (Xilinx Zynq UltraScale+ RFSoC XCZU28DR/XCZU48DR)
 *  Opal Kelley XEM8320 (Xilinx Artix UltraScale+ XCAU25P)
+*  Napatech NT20E3 (Xilinx Virtex 7 XC7V330T)
+*  Napatech NT40E3 (Xilinx Virtex 7 XC7V330T)
+*  Napatech NT200A01 (Xilinx Virtex UltraScale XCVU095)
+*  Napatech NT200A02 (Xilinx Virtex UltraScale+ XCVU5P)
 *  Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P)
 *  Xilinx Alveo U45N/SN1000 (Xilinx Virtex UltraScale+ XCU26)
 *  Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50)

src/cndm/board/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv

@@ -321,7 +321,7 @@ assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n;
 assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p;
 assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n;
 
-for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
 
     localparam CNT = 4;
 

src/cndm/board/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -282,8 +283,7 @@ class TB:
         self.qsfp_sources = []
         self.qsfp_sinks = []
 
-        for inst in dut.uut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.uut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64:

src/cndm/board/Alveo/fpga/rtl/fpga_core.sv

@@ -412,7 +412,7 @@ wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
 
 wire eth_gty_rst[GTY_CLK_CNT];
 
-for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
+for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gt_clk
 
     wire eth_gty_mgt_refclk_int;
 
@@ -469,7 +469,7 @@ assign led[0] = ptp_pps_str;
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3",  "QSFP1.4"};
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3",  "QSFP2.4"};
 
-for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
 
     localparam CLK = n;
     localparam CNT = 4;

src/cndm/board/Alveo/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -293,8 +294,7 @@ class TB:
         self.qsfp_sources = []
         self.qsfp_sinks = []
 
-        for inst in dut.uut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.uut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64:

src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -259,8 +260,7 @@ class TB:
         self.qsfp_sources = []
         self.qsfp_sinks = []
 
-        for inst in dut.uut.gt_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.uut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64:

src/cndm/board/NT200A02/fpga/README.md

@@ -0,0 +1,52 @@
+# Corundum for NT200A01/NT200A02
+
+## Introduction
+
+This design targets the Napatech NT200A01/NT200A02 FPGA board.
+
+*  QSFP28
+    *  10GBASE-R or 25GBASE-R MACs via GTY transceivers
+
+## Board details
+
+* FPGA
+  * NT200A01: xcvu095-ffva2104-2-e
+  * NT200A02: xcvu5p-flva2104-2-e
+*  PCIe: gen 3 x16 (~128 Gbps)
+*  Reference oscillator: 322.265625 MHz from Si5340
+*  25GBASE-R PHY: Soft PCS with GTY transceivers
+
+## Licensing
+
+*  Toolchain
+    *  Vivado Enterprise (requires license)
+*  IP
+    *  No licensed vendor IP or 3rd party IP
+
+## How to build
+
+Run `make` in the appropriate `fpga*` subdirectory to build the bitstream.  Ensure that the Xilinx Vivado toolchain components are in PATH.
+
+On the host system, run `make` in `modules/cndm` to build the driver.  Ensure that the headers for the running kernel are installed, otherwise the driver cannot be compiled.
+
+## How to test
+
+Run `make program` to program the board with Vivado.  Then, reboot the machine to re-enumerate the PCIe bus.  Finally, load the driver on the host system with `insmod cndm.ko`.  Check `dmesg` for output from driver initialization.  Run `cndm_ddcmd.sh =p` to enable all debug messages.
+
+## JTAG pinout
+
+Napatech boards use a non-standard connector for JTAG.  There are three debug connectors, and one of them carries the JTAG signals for the FPGA.
+
+        J16             J22
+        FPGA            AVR
+    TDI 7 8 GND     TDI 7 8 GND
+    TMS 5 6 HALT    TMS 5 6
+    TDO 3 4 Vref    TDO 3 4 Vref
+    TCK 1 2 GND     TCK 1 2 GND
+
+            J17
+        GND 2 1
+            4 3
+            6 5
+
+Note: J18.6 HALT must be driven low to access the JTAG chain.  So, either tie to to ground, or connect it to the HALT signal on DLC9/DLC10 cables.

src/cndm/board/NT200A02/fpga/common/vivado.mk

@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: MIT
+###################################################################
+#
+# Xilinx Vivado FPGA Makefile
+#
+# Copyright (c) 2016-2025 Alex Forencich
+#
+###################################################################
+#
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - list of source files
+# INC_FILES - list of include files
+# XDC_FILES - list of timing constraint files
+# XCI_FILES - list of IP XCI files
+# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
+# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
+#
+# Note: both SYN_FILES and INC_FILES support file list files.  File list
+# files are files with a .f extension that contain a list of additional
+# files to include, one path relative to the .f file location per line.
+# The .f files are processed recursively, and then the complete file list
+# is de-duplicated, with later files in the list taking precedence.
+#
+# Example:
+#
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+#
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include $(CONFIG)
+
+FPGA_TOP ?= fpga
+PROJECT ?= $(FPGA_TOP)
+XDC_FILES ?= $(PROJECT).xdc
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
+INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
+
+###################################################################
+# Main Targets
+#
+# all: build everything (fpga)
+# fpga: build FPGA config
+# vivado: open project in Vivado
+# tmpclean: remove intermediate files
+# clean: remove output files and project files
+# distclean: remove archived output files
+###################################################################
+
+all: fpga
+
+fpga: $(PROJECT).bit
+
+vivado: $(PROJECT).xpr
+	vivado $(PROJECT).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+	-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+
+# create fresh project if Makefile or IP files have changed
+create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
+	echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
+	for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+# source config TCL scripts if any source file has changed
+update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
+	echo "open_project -quiet $(PROJECT).xpr" > $@
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+$(PROJECT).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
+	echo "open_project $(PROJECT).xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
+	echo "open_project $(PROJECT).xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "open_run impl_1" >> run_impl.tcl
+	echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
+	echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# output files (including potentially bit, bin, ltx, and xsa)
+$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
+	echo "open_project $(PROJECT).xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
+	echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
+	echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
+	if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi

src/cndm/board/NT200A02/fpga/fpga_NT200A01/Makefile

@@ -0,0 +1,163 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xcvu095-ffva2104-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = virtexu
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga_nt200a01.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(RTL_DIR)/../pll/si5340_i2c_init.sv
+SYN_FILES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/lss/rtl/taxi_i2c_master.sv
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vsec_qspi.f
+
+# XDC files
+XDC_FILES = ../fpga_nt200a01.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_leaf.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_phc_regs.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES = ../ip/pcie3_ultrascale_0.tcl
+IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl
+
+# Configuration
+CONFIG_TCL_FILES = config.tcl
+
+include ../common/vivado.mk
+
+%_fallback.bit: %.bit
+	echo "open_project $*.xpr" > generate_fallback_bit.tcl
+	echo "open_run impl_1" >> generate_fallback_bit.tcl
+	echo "startgroup" >> generate_fallback_bit.tcl
+	echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl
+	echo "endgroup" >> generate_fallback_bit.tcl
+	echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
+	echo "undo" >> generate_fallback_bit.tcl
+	echo "exit" >> generate_fallback_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
+
+program: $(FPGA_TOP).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+%_fallback.mcs %_fallback.prm: %_fallback.bit
+	echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x03000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
+	echo "exit" >> generate_fallback_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
+	echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
+
+%_full.mcs %_full.prm: %_fallback.bit %.bit
+	echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x03000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
+	echo "exit" >> generate_full_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
+	echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw_manager" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+
+flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
+	echo "open_hw_manager" > flash$*.tcl
+	echo "connect_hw_server" >> flash$*.tcl
+	echo "open_hw_target" >> flash$*.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash$*.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
+	echo "exit" >> flash$*.tcl
+	vivado -nojournal -nolog -mode batch -source flash$*.tcl

src/cndm/board/NT200A02/fpga/fpga_NT200A01/config.tcl

@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# collect build information
+set build_date [clock seconds]
+set git_hash 00000000
+set git_tag ""
+
+if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
+    puts "Error running git or project not under version control"
+}
+
+if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
+    puts "Error running git, project not under version control, or no tag found"
+}
+
+puts "Build date: ${build_date}"
+puts "Git hash: ${git_hash}"
+puts "Git tag: ${git_tag}"
+
+if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
+    puts "Failed to extract version from git tag"
+    set tag_ver 0.0.1
+}
+
+puts "Tag version: ${tag_ver}"
+
+# FW and board IDs
+set fpga_id [expr 0x3842093]
+set fw_id [expr 0x0000C001]
+set fw_ver $tag_ver
+set board_vendor_id [expr 0x18f4]
+set board_device_id [expr 0x01a5]
+set board_ver 1.0
+set release_info [expr 0x00000000]
+
+# PCIe IDs
+set pcie_vendor_id [expr 0x1234]
+set pcie_device_id [expr 0xC001]
+set pcie_class_code [expr 0x020000]
+set pcie_revision_id [expr 0x00]
+set pcie_subsystem_device_id $board_device_id
+set pcie_subsystem_vendor_id $board_vendor_id
+
+# FW ID
+dict set params FPGA_ID [format "32'h%08x" $fpga_id]
+dict set params FW_ID [format "32'h%08x" $fw_id]
+dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0]
+dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
+dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0]
+dict set params BUILD_DATE "32'd${build_date}"
+dict set params GIT_HASH "32'h${git_hash}"
+dict set params RELEASE_INFO [format "32'h%08x" $release_info]
+
+# PTP configuration
+dict set params PTP_TS_EN "1"
+
+# AXI lite interface configuration (control)
+dict set params AXIL_CTRL_DATA_W "32"
+dict set params AXIL_CTRL_ADDR_W "24"
+
+# MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "1"
+dict set params MAC_DATA_W "64"
+
+# PCIe IP core settings
+set pcie [get_ips pcie3_ultrascale_0]
+
+# configure BAR settings
+proc configure_bar {pcie pf bar aperture} {
+    set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes}
+    for { set i 0 } { $i < [llength $size_list] } { incr i } {
+        set scale [lindex $size_list $i]
+
+        if {$aperture > 0 && $aperture < ($i+1)*10} {
+            set size [expr 1 << $aperture - ($i*10)]
+
+            puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)"
+
+            set pcie_config [dict create]
+
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size
+
+            set_property -dict $pcie_config $pcie
+
+            return
+        }
+    }
+    puts "${pcie} PF${pf} BAR${bar}: disabled"
+    set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie
+}
+
+# Control BAR (BAR 0)
+configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W]
+
+# PCIe IP core configuration
+set pcie_config [dict create]
+
+# PCIe IDs
+dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id]
+dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id]
+dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code]
+dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id]
+dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id]
+dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id]
+
+# MSI
+dict set pcie_config "CONFIG.pf0_msi_enabled" {true}
+
+set_property -dict $pcie_config $pcie
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/cndm/board/NT200A02/fpga/fpga_NT200A01_10g/Makefile

@@ -0,0 +1,163 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xcvu095-ffva2104-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = virtexu
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga_nt200a01.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(RTL_DIR)/../pll/si5340_i2c_init.sv
+SYN_FILES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/lss/rtl/taxi_i2c_master.sv
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vsec_qspi.f
+
+# XDC files
+XDC_FILES = ../fpga_nt200a01.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_leaf.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_phc_regs.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES = ../ip/pcie3_ultrascale_0.tcl
+IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_322.tcl
+
+# Configuration
+CONFIG_TCL_FILES = config.tcl
+
+include ../common/vivado.mk
+
+%_fallback.bit: %.bit
+	echo "open_project $*.xpr" > generate_fallback_bit.tcl
+	echo "open_run impl_1" >> generate_fallback_bit.tcl
+	echo "startgroup" >> generate_fallback_bit.tcl
+	echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl
+	echo "endgroup" >> generate_fallback_bit.tcl
+	echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
+	echo "undo" >> generate_fallback_bit.tcl
+	echo "exit" >> generate_fallback_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
+
+program: $(FPGA_TOP).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+%_fallback.mcs %_fallback.prm: %_fallback.bit
+	echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x03000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
+	echo "exit" >> generate_fallback_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
+	echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
+
+%_full.mcs %_full.prm: %_fallback.bit %.bit
+	echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x03000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
+	echo "exit" >> generate_full_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
+	echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw_manager" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+
+flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
+	echo "open_hw_manager" > flash$*.tcl
+	echo "connect_hw_server" >> flash$*.tcl
+	echo "open_hw_target" >> flash$*.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash$*.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
+	echo "exit" >> flash$*.tcl
+	vivado -nojournal -nolog -mode batch -source flash$*.tcl

src/cndm/board/NT200A02/fpga/fpga_NT200A01_10g/config.tcl

@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# collect build information
+set build_date [clock seconds]
+set git_hash 00000000
+set git_tag ""
+
+if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
+    puts "Error running git or project not under version control"
+}
+
+if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
+    puts "Error running git, project not under version control, or no tag found"
+}
+
+puts "Build date: ${build_date}"
+puts "Git hash: ${git_hash}"
+puts "Git tag: ${git_tag}"
+
+if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
+    puts "Failed to extract version from git tag"
+    set tag_ver 0.0.1
+}
+
+puts "Tag version: ${tag_ver}"
+
+# FW and board IDs
+set fpga_id [expr 0x3842093]
+set fw_id [expr 0x0000C001]
+set fw_ver $tag_ver
+set board_vendor_id [expr 0x18f4]
+set board_device_id [expr 0x01a5]
+set board_ver 1.0
+set release_info [expr 0x00000000]
+
+# PCIe IDs
+set pcie_vendor_id [expr 0x1234]
+set pcie_device_id [expr 0xC001]
+set pcie_class_code [expr 0x020000]
+set pcie_revision_id [expr 0x00]
+set pcie_subsystem_device_id $board_device_id
+set pcie_subsystem_vendor_id $board_vendor_id
+
+# FW ID
+dict set params FPGA_ID [format "32'h%08x" $fpga_id]
+dict set params FW_ID [format "32'h%08x" $fw_id]
+dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0]
+dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
+dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0]
+dict set params BUILD_DATE "32'd${build_date}"
+dict set params GIT_HASH "32'h${git_hash}"
+dict set params RELEASE_INFO [format "32'h%08x" $release_info]
+
+# PTP configuration
+dict set params PTP_TS_EN "1"
+
+# AXI lite interface configuration (control)
+dict set params AXIL_CTRL_DATA_W "32"
+dict set params AXIL_CTRL_ADDR_W "24"
+
+# MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "1"
+dict set params MAC_DATA_W "32"
+
+# PCIe IP core settings
+set pcie [get_ips pcie3_ultrascale_0]
+
+# configure BAR settings
+proc configure_bar {pcie pf bar aperture} {
+    set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes}
+    for { set i 0 } { $i < [llength $size_list] } { incr i } {
+        set scale [lindex $size_list $i]
+
+        if {$aperture > 0 && $aperture < ($i+1)*10} {
+            set size [expr 1 << $aperture - ($i*10)]
+
+            puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)"
+
+            set pcie_config [dict create]
+
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size
+
+            set_property -dict $pcie_config $pcie
+
+            return
+        }
+    }
+    puts "${pcie} PF${pf} BAR${bar}: disabled"
+    set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie
+}
+
+# Control BAR (BAR 0)
+configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W]
+
+# PCIe IP core configuration
+set pcie_config [dict create]
+
+# PCIe IDs
+dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id]
+dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id]
+dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code]
+dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id]
+dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id]
+dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id]
+
+# MSI
+dict set pcie_config "CONFIG.pf0_msi_enabled" {true}
+
+set_property -dict $pcie_config $pcie
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/cndm/board/NT200A02/fpga/fpga_NT200A02/Makefile

@@ -0,0 +1,163 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xcvu5p-flva2104-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = virtexuplus
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga_nt200a02.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(RTL_DIR)/../pll/si5340_i2c_init.sv
+SYN_FILES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/lss/rtl/taxi_i2c_master.sv
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vsec_qspi.f
+
+# XDC files
+XDC_FILES = ../fpga_nt200a02.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_leaf.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_phc_regs.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES = ../ip/pcie4_uscale_plus_0.tcl
+IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl
+
+# Configuration
+CONFIG_TCL_FILES = config.tcl
+
+include ../common/vivado.mk
+
+%_fallback.bit: %.bit
+	echo "open_project $*.xpr" > generate_fallback_bit.tcl
+	echo "open_run impl_1" >> generate_fallback_bit.tcl
+	echo "startgroup" >> generate_fallback_bit.tcl
+	echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl
+	echo "endgroup" >> generate_fallback_bit.tcl
+	echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
+	echo "undo" >> generate_fallback_bit.tcl
+	echo "exit" >> generate_fallback_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
+
+program: $(FPGA_TOP).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+%_fallback.mcs %_fallback.prm: %_fallback.bit
+	echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x0C000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
+	echo "exit" >> generate_fallback_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
+	echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
+
+%_full.mcs %_full.prm: %_fallback.bit %.bit
+	echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x0C000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
+	echo "exit" >> generate_full_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
+	echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw_manager" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+
+flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
+	echo "open_hw_manager" > flash$*.tcl
+	echo "connect_hw_server" >> flash$*.tcl
+	echo "open_hw_target" >> flash$*.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash$*.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
+	echo "exit" >> flash$*.tcl
+	vivado -nojournal -nolog -mode batch -source flash$*.tcl

src/cndm/board/NT200A02/fpga/fpga_NT200A02/config.tcl

@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# collect build information
+set build_date [clock seconds]
+set git_hash 00000000
+set git_tag ""
+
+if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
+    puts "Error running git or project not under version control"
+}
+
+if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
+    puts "Error running git, project not under version control, or no tag found"
+}
+
+puts "Build date: ${build_date}"
+puts "Git hash: ${git_hash}"
+puts "Git tag: ${git_tag}"
+
+if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
+    puts "Failed to extract version from git tag"
+    set tag_ver 0.0.1
+}
+
+puts "Tag version: ${tag_ver}"
+
+# FW and board IDs
+set fpga_id [expr 0x4B2B093]
+set fw_id [expr 0x0000C001]
+set fw_ver $tag_ver
+set board_vendor_id [expr 0x18f4]
+set board_device_id [expr 0x01c5]
+set board_ver 1.0
+set release_info [expr 0x00000000]
+
+# PCIe IDs
+set pcie_vendor_id [expr 0x1234]
+set pcie_device_id [expr 0xC001]
+set pcie_class_code [expr 0x020000]
+set pcie_revision_id [expr 0x00]
+set pcie_subsystem_device_id $board_device_id
+set pcie_subsystem_vendor_id $board_vendor_id
+
+# FW ID
+dict set params FPGA_ID [format "32'h%08x" $fpga_id]
+dict set params FW_ID [format "32'h%08x" $fw_id]
+dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0]
+dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
+dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0]
+dict set params BUILD_DATE "32'd${build_date}"
+dict set params GIT_HASH "32'h${git_hash}"
+dict set params RELEASE_INFO [format "32'h%08x" $release_info]
+
+# PTP configuration
+dict set params PTP_TS_EN "1"
+
+# AXI lite interface configuration (control)
+dict set params AXIL_CTRL_DATA_W "32"
+dict set params AXIL_CTRL_ADDR_W "24"
+
+# MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "1"
+dict set params MAC_DATA_W "64"
+
+# PCIe IP core settings
+set pcie [get_ips pcie4_uscale_plus_0]
+
+# configure BAR settings
+proc configure_bar {pcie pf bar aperture} {
+    set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes}
+    for { set i 0 } { $i < [llength $size_list] } { incr i } {
+        set scale [lindex $size_list $i]
+
+        if {$aperture > 0 && $aperture < ($i+1)*10} {
+            set size [expr 1 << $aperture - ($i*10)]
+
+            puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)"
+
+            set pcie_config [dict create]
+
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size
+
+            set_property -dict $pcie_config $pcie
+
+            return
+        }
+    }
+    puts "${pcie} PF${pf} BAR${bar}: disabled"
+    set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie
+}
+
+# Control BAR (BAR 0)
+configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W]
+
+# PCIe IP core configuration
+set pcie_config [dict create]
+
+# PCIe IDs
+dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id]
+dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id]
+dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code]
+dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id]
+dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id]
+dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id]
+
+# MSI
+dict set pcie_config "CONFIG.pf0_msi_enabled" {true}
+
+set_property -dict $pcie_config $pcie
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/cndm/board/NT200A02/fpga/fpga_NT200A02_10g/Makefile

@@ -0,0 +1,163 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xcvu5p-flva2104-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = virtexuplus
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga_nt200a02.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(RTL_DIR)/../pll/si5340_i2c_init.sv
+SYN_FILES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/lss/rtl/taxi_i2c_master.sv
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vsec_qspi.f
+
+# XDC files
+XDC_FILES = ../fpga_nt200a02.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_leaf.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_phc_regs.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES = ../ip/pcie4_uscale_plus_0.tcl
+IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_322.tcl
+
+# Configuration
+CONFIG_TCL_FILES = config.tcl
+
+include ../common/vivado.mk
+
+%_fallback.bit: %.bit
+	echo "open_project $*.xpr" > generate_fallback_bit.tcl
+	echo "open_run impl_1" >> generate_fallback_bit.tcl
+	echo "startgroup" >> generate_fallback_bit.tcl
+	echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl
+	echo "endgroup" >> generate_fallback_bit.tcl
+	echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
+	echo "undo" >> generate_fallback_bit.tcl
+	echo "exit" >> generate_fallback_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
+
+program: $(FPGA_TOP).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+%_fallback.mcs %_fallback.prm: %_fallback.bit
+	echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x0C000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
+	echo "exit" >> generate_fallback_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
+	echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
+
+%_full.mcs %_full.prm: %_fallback.bit %.bit
+	echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x0C000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
+	echo "exit" >> generate_full_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
+	echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw_manager" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+
+flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
+	echo "open_hw_manager" > flash$*.tcl
+	echo "connect_hw_server" >> flash$*.tcl
+	echo "open_hw_target" >> flash$*.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash$*.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
+	echo "exit" >> flash$*.tcl
+	vivado -nojournal -nolog -mode batch -source flash$*.tcl

src/cndm/board/NT200A02/fpga/fpga_NT200A02_10g/config.tcl

@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# collect build information
+set build_date [clock seconds]
+set git_hash 00000000
+set git_tag ""
+
+if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
+    puts "Error running git or project not under version control"
+}
+
+if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
+    puts "Error running git, project not under version control, or no tag found"
+}
+
+puts "Build date: ${build_date}"
+puts "Git hash: ${git_hash}"
+puts "Git tag: ${git_tag}"
+
+if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
+    puts "Failed to extract version from git tag"
+    set tag_ver 0.0.1
+}
+
+puts "Tag version: ${tag_ver}"
+
+# FW and board IDs
+set fpga_id [expr 0x4B2B093]
+set fw_id [expr 0x0000C001]
+set fw_ver $tag_ver
+set board_vendor_id [expr 0x18f4]
+set board_device_id [expr 0x01c5]
+set board_ver 1.0
+set release_info [expr 0x00000000]
+
+# PCIe IDs
+set pcie_vendor_id [expr 0x1234]
+set pcie_device_id [expr 0xC001]
+set pcie_class_code [expr 0x020000]
+set pcie_revision_id [expr 0x00]
+set pcie_subsystem_device_id $board_device_id
+set pcie_subsystem_vendor_id $board_vendor_id
+
+# FW ID
+dict set params FPGA_ID [format "32'h%08x" $fpga_id]
+dict set params FW_ID [format "32'h%08x" $fw_id]
+dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0]
+dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
+dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0]
+dict set params BUILD_DATE "32'd${build_date}"
+dict set params GIT_HASH "32'h${git_hash}"
+dict set params RELEASE_INFO [format "32'h%08x" $release_info]
+
+# PTP configuration
+dict set params PTP_TS_EN "1"
+
+# AXI lite interface configuration (control)
+dict set params AXIL_CTRL_DATA_W "32"
+dict set params AXIL_CTRL_ADDR_W "24"
+
+# MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "1"
+dict set params MAC_DATA_W "32"
+
+# PCIe IP core settings
+set pcie [get_ips pcie4_uscale_plus_0]
+
+# configure BAR settings
+proc configure_bar {pcie pf bar aperture} {
+    set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes}
+    for { set i 0 } { $i < [llength $size_list] } { incr i } {
+        set scale [lindex $size_list $i]
+
+        if {$aperture > 0 && $aperture < ($i+1)*10} {
+            set size [expr 1 << $aperture - ($i*10)]
+
+            puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)"
+
+            set pcie_config [dict create]
+
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size
+
+            set_property -dict $pcie_config $pcie
+
+            return
+        }
+    }
+    puts "${pcie} PF${pf} BAR${bar}: disabled"
+    set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie
+}
+
+# Control BAR (BAR 0)
+configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W]
+
+# PCIe IP core configuration
+set pcie_config [dict create]
+
+# PCIe IDs
+dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id]
+dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id]
+dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code]
+dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id]
+dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id]
+dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id]
+
+# MSI
+dict set pcie_config "CONFIG.pf0_msi_enabled" {true}
+
+set_property -dict $pcie_config $pcie
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/cndm/board/NT200A02/fpga/fpga_nt200a01.xdc

@@ -0,0 +1,262 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Napatech NT200A01 board
+# part: xcvu095-ffva2104-2-e
+
+# General configuration
+set_property CFGBVS GND                                [current_design]
+set_property CONFIG_VOLTAGE 1.8                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
+set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
+
+# System clocks
+# 50 MHz system clock
+set_property -dict {LOC AK34 IOSTANDARD LVCMOS18} [get_ports clk_50mhz] ;# U10
+create_clock -period 20.000 -name clk_50mhz [get_ports clk_50mhz]
+
+# 80 MHz EMCCLK
+#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_80mhz] ;# U9
+#create_clock -period 12.500 -name clk_80mhz [get_ports clk_80mhz]
+
+# 20 MHz reference clock
+#set_property -dict {LOC AM33 IOSTANDARD LVCMOS18} [get_ports clk_20mhz] ;# U201/U22
+#create_clock -period 12.500 -name clk_20mhz [get_ports clk_20mhz]
+
+# 100 MHz DDR4 C0 clock from Si5340 OUT0 via U167
+#set_property -dict {LOC BA19 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c0_p]
+#set_property -dict {LOC AY19 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c0_n]
+#create_clock -period 10.000 -name clk_ddr_c0 [get_ports clk_ddr_c0_p]
+
+# 100 MHz DDR4 C1 clock from Si5340 OUT0 via U167
+#set_property -dict {LOC BB39 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c1_p]
+#set_property -dict {LOC BB38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c1_n]
+#create_clock -period 10.000 -name clk_ddr_c1 [get_ports clk_ddr_c1_p]
+
+# 100 MHz DDR4 C2 clock from Si5340 OUT0 via U167
+#set_property -dict {LOC B10  IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c2_p]
+#set_property -dict {LOC C10  IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c2_n]
+#create_clock -period 10.000 -name clk_ddr_c2 [get_ports clk_ddr_c2_p]
+
+# LEDs
+set_property -dict {LOC R26  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[0]}] ;# D5
+set_property -dict {LOC M28  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[1]}] ;# D6
+set_property -dict {LOC R27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[2]}] ;# D7
+set_property -dict {LOC T24  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[3]}] ;# D8
+set_property -dict {LOC J27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][0]}] ;# D16
+set_property -dict {LOC K27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][1]}] ;# D17
+set_property -dict {LOC L25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][2]}] ;# D18
+set_property -dict {LOC L24  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][3]}] ;# D29
+set_property -dict {LOC B28  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][0]}] ;# D27
+set_property -dict {LOC C27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][1]}] ;# D28
+set_property -dict {LOC J25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][2]}] ;# D29
+set_property -dict {LOC K26  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][3]}] ;# D30
+set_property -dict {LOC D27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_red}] ;# D52
+set_property -dict {LOC D26  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_green}] ;# D52
+set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_sync[0]}] ;# D54
+set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_sync[1]}] ;# D56
+set_property -dict {LOC M15  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {eth_led_yellow}] ;# J28
+set_property -dict {LOC M13  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {eth_led_green}] ;# J28
+
+set_false_path -to [get_ports {led[*] qsfp_led[*][*] led_red led_green led_sync[*] eth_led_yellow eth_led_green}]
+set_output_delay 0 [get_ports {led[*] qsfp_led[*][*] led_red led_green led_sync[*] eth_led_yellow eth_led_green}]
+
+# Si5340 U18
+set_property -dict {LOC AT36 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5340_i2c_scl] ;# U23.14 SCLK
+set_property -dict {LOC AT35 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5340_i2c_sda] ;# U23.13 SDA
+set_property -dict {LOC AT37 IOSTANDARD LVCMOS18} [get_ports si5340_intr] ;# U18.33 INTR
+
+set_false_path -to [get_ports {si5340_i2c_scl si5340_i2c_sda}]
+set_output_delay 0 [get_ports {si5340_i2c_scl si5340_i2c_sda}]
+set_false_path -from [get_ports {si5340_i2c_scl si5340_i2c_sda si5340_intr}]
+set_input_delay 0 [get_ports {si5340_i2c_scl si5340_i2c_sda si5340_intr}]
+
+# Gigabit PHY (DP83867)
+#set_property -dict {LOC P12  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_gtx_clk] ;# U198.29 GTX_CLK via ?
+#set_property -dict {LOC P15  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_tx_ctl] ;# U198.37 TX_CTRL via ?
+#set_property -dict {LOC R11  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] ;# U198.28 TX_D0/SGMII_SIN via ?
+#set_property -dict {LOC R12  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] ;# U198.27 TX_D1/SGMII_SIP via ?
+#set_property -dict {LOC P11  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] ;# U198.26 TX_D2 via ?
+#set_property -dict {LOC N12  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] ;# U198.25 TX_D3 via ?
+#set_property -dict {LOC U13  IOSTANDARD LVCMOS18} [get_ports phy_rx_clk] ;# U198.32 RX_CLK via ?
+#set_property -dict {LOC U16  IOSTANDARD LVCMOS18} [get_ports phy_rx_ctl] ;# U198.38 RX_CTRL via ?
+#set_property -dict {LOC T11  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[0]}] ;# U198.33 RX_D0/SGMII_COP via ?
+#set_property -dict {LOC U11  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[1]}] ;# U198.34 RX_D1/SGMII_CON via ?
+#set_property -dict {LOC R13  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[2]}] ;# U198.35 RX_D2/SGMII_SOP via ?
+#set_property -dict {LOC V15  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[3]}] ;# U198.36 RX_D3/SGMII_SON via ?
+#set_property -dict {LOC J11  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_refclk] ;# U198.15 XI 25 MHz
+#set_property -dict {LOC T14  IOSTANDARD LVCMOS18} [get_ports phy_clk_out] ;# U198.18 CLK_OUT
+#set_property -dict {LOC M11  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_reset_n] ;# U198.43 RESET_N
+#set_property -dict {LOC V16  IOSTANDARD LVCMOS18} [get_ports phy_int_n] ;# U198.44 PWRDOWN/INTN
+#set_property -dict {LOC U12  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_mdc] ;# U198.16 MDC
+#set_property -dict {LOC J12  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_mdio] ;# U198.17 MDIO
+#set_property -dict {LOC L14  IOSTANDARD LVCMOS18} [get_ports phy_gpio0] ;# U198.39 GPIO_0
+#set_property -dict {LOC M12  IOSTANDARD LVCMOS18} [get_ports phy_gpio1] ;# U198.40 GPIO_1
+#set_property -dict {LOC L15  IOSTANDARD LVCMOS18} [get_ports phy_led0] ;# U198.47 LED_0
+#set_property -dict {LOC W14  IOSTANDARD LVCMOS18} [get_ports phy_led1] ;# U198.46 LED_1
+#set_property -dict {LOC K14  IOSTANDARD LVCMOS18} [get_ports phy_led2] ;# U198.45 LED_2
+
+# QSFP28 Interfaces
+set_property -dict {LOC R45 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC R46 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC M42 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC M43 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC U45 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC U46 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC P42 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC P43 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC N45 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC N46 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC K42 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC K43 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC W45 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC W46 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC T42 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC T43 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC V38 } [get_ports qsfp0_mgt_refclk_p] ;# MGTREFCLK0P_129 from Si5340 U23 OUT1
+set_property -dict {LOC V39 } [get_ports qsfp0_mgt_refclk_n] ;# MGTREFCLK0N_129 from Si5340 U23 OUT1
+set_property -dict {LOC A26  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl]
+set_property -dict {LOC C25  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp0_modprsl]
+set_property -dict {LOC B26  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp0_intl]
+set_property -dict {LOC G25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode]
+set_property -dict {LOC B25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_scl]
+set_property -dict {LOC F25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_sda]
+
+# 322.265625 MHz MGT reference clock
+create_clock -period 3.103 -name qsfp0_mgt_refclk [get_ports qsfp0_mgt_refclk_p]
+
+set_false_path -to [get_ports {qsfp0_resetl qsfp0_lpmode}]
+set_output_delay 0 [get_ports {qsfp0_resetl qsfp0_lpmode}]
+set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
+set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
+
+set_false_path -to [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
+set_output_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
+set_false_path -from [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
+set_input_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
+
+set_property -dict {LOC G45 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP2_130 GTYE3_CHANNEL_X0Y26 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC G46 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN2_130 GTYE3_CHANNEL_X0Y26 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC D42 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP2_130 GTYE3_CHANNEL_X0Y26 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC D43 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN2_130 GTYE3_CHANNEL_X0Y26 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC J45 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC J46 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC F42 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC F43 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC E45 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP3_130 GTYE3_CHANNEL_X0Y27 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC E46 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN3_130 GTYE3_CHANNEL_X0Y27 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC B42 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP3_130 GTYE3_CHANNEL_X0Y27 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC B43 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN3_130 GTYE3_CHANNEL_X0Y27 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC L45 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC L46 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC H42 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC H43 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC R40 } [get_ports qsfp1_mgt_refclk_p] ;# MGTREFCLK0P_130 from Si5340 U23 OUT2
+set_property -dict {LOC R41 } [get_ports qsfp1_mgt_refclk_n] ;# MGTREFCLK0N_130 from Si5340 U23 OUT2
+set_property -dict {LOC B27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl]
+set_property -dict {LOC H28  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_modprsl]
+set_property -dict {LOC N24  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_intl]
+set_property -dict {LOC H25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode]
+set_property -dict {LOC P27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_scl]
+set_property -dict {LOC R24  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_sda]
+
+# 322.265625 MHz MGT reference clock
+create_clock -period 3.103 -name qsfp1_mgt_refclk [get_ports qsfp1_mgt_refclk_p]
+
+set_false_path -to [get_ports {qsfp1_resetl qsfp1_lpmode}]
+set_output_delay 0 [get_ports {qsfp1_resetl qsfp1_lpmode}]
+set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}]
+set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}]
+
+set_false_path -to [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
+set_output_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
+set_false_path -from [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
+set_input_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
+
+# PCIe Interface
+set_property -dict {LOC U4  } [get_ports {pcie_rx_p[0]}]  ;# MGTHRXP3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4
+set_property -dict {LOC U3  } [get_ports {pcie_rx_n[0]}]  ;# MGTHRXN3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4
+set_property -dict {LOC M7  } [get_ports {pcie_tx_p[0]}]  ;# MGTHTXP3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4
+set_property -dict {LOC M6  } [get_ports {pcie_tx_n[0]}]  ;# MGTHTXN3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4
+set_property -dict {LOC V2  } [get_ports {pcie_rx_p[1]}]  ;# MGTHRXP2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4
+set_property -dict {LOC V1  } [get_ports {pcie_rx_n[1]}]  ;# MGTHRXN2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4
+set_property -dict {LOC P7  } [get_ports {pcie_tx_p[1]}]  ;# MGTHTXP2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4
+set_property -dict {LOC P6  } [get_ports {pcie_tx_n[1]}]  ;# MGTHTXN2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4
+set_property -dict {LOC W4  } [get_ports {pcie_rx_p[2]}]  ;# MGTHRXP1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4
+set_property -dict {LOC W3  } [get_ports {pcie_rx_n[2]}]  ;# MGTHRXN1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4
+set_property -dict {LOC T7  } [get_ports {pcie_tx_p[2]}]  ;# MGTHTXP1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4
+set_property -dict {LOC T6  } [get_ports {pcie_tx_n[2]}]  ;# MGTHTXN1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4
+set_property -dict {LOC Y2  } [get_ports {pcie_rx_p[3]}]  ;# MGTHRXP0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4
+set_property -dict {LOC Y1  } [get_ports {pcie_rx_n[3]}]  ;# MGTHRXN0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4
+set_property -dict {LOC V7  } [get_ports {pcie_tx_p[3]}]  ;# MGTHTXP0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4
+set_property -dict {LOC V6  } [get_ports {pcie_tx_n[3]}]  ;# MGTHTXN0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4
+set_property -dict {LOC AA4 } [get_ports {pcie_rx_p[4]}]  ;# MGTHRXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC AA3 } [get_ports {pcie_rx_n[4]}]  ;# MGTHRXN3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC Y7  } [get_ports {pcie_tx_p[4]}]  ;# MGTHTXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC Y6  } [get_ports {pcie_tx_n[4]}]  ;# MGTHTXN3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[5]}]  ;# MGTHRXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[5]}]  ;# MGTHRXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC AB7 } [get_ports {pcie_tx_p[5]}]  ;# MGTHTXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC AB6 } [get_ports {pcie_tx_n[5]}]  ;# MGTHTXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC AC4 } [get_ports {pcie_rx_p[6]}]  ;# MGTHRXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC AC3 } [get_ports {pcie_rx_n[6]}]  ;# MGTHRXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[6]}]  ;# MGTHTXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[6]}]  ;# MGTHTXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[7]}]  ;# MGTHRXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[7]}]  ;# MGTHRXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[7]}]  ;# MGTHTXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
+set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[7]}]  ;# MGTHTXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
+#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[8]}]  ;# MGTHRXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[8]}]  ;# MGTHRXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}]  ;# MGTHTXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}]  ;# MGTHTXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[9]}]  ;# MGTHRXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[9]}]  ;# MGTHRXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AR5 } [get_ports {pcie_tx_p[9]}]  ;# MGTHTXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AR4 } [get_ports {pcie_tx_n[9]}]  ;# MGTHTXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[10]}] ;# MGTHRXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[10]}] ;# MGTHRXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTHTXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTHTXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[11]}] ;# MGTHRXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[11]}] ;# MGTHRXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AU5 } [get_ports {pcie_tx_p[11]}] ;# MGTHTXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AU4 } [get_ports {pcie_tx_n[11]}] ;# MGTHTXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[12]}] ;# MGTHRXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[12]}] ;# MGTHRXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC AW5 } [get_ports {pcie_tx_p[12]}] ;# MGTHTXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC AW4 } [get_ports {pcie_tx_n[12]}] ;# MGTHTXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[13]}] ;# MGTHRXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[13]}] ;# MGTHRXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC BA5 } [get_ports {pcie_tx_p[13]}] ;# MGTHTXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC BA4 } [get_ports {pcie_tx_n[13]}] ;# MGTHTXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC AY2 } [get_ports {pcie_rx_p[14]}] ;# MGTHRXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC AY1 } [get_ports {pcie_rx_n[14]}] ;# MGTHRXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC BC5 } [get_ports {pcie_tx_p[14]}] ;# MGTHTXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC BC4 } [get_ports {pcie_tx_n[14]}] ;# MGTHTXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC BB2 } [get_ports {pcie_rx_p[15]}] ;# MGTHRXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC BB1 } [get_ports {pcie_rx_n[15]}] ;# MGTHRXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC BE5 } [get_ports {pcie_tx_p[15]}] ;# MGTHTXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC BE4 } [get_ports {pcie_tx_n[15]}] ;# MGTHTXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC AR9 } [get_ports pcie_refclk_0_p] ;# MGTREFCLK0P_224
+#set_property -dict {LOC AR8 } [get_ports pcie_refclk_0_n] ;# MGTREFCLK0N_224
+set_property -dict {LOC AC9 } [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_227
+set_property -dict {LOC AC8 } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_227
+set_property -dict {LOC AM17 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset]
+
+# 100 MHz MGT reference clock
+#create_clock -period 10.000 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p]
+create_clock -period 10.000 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
+
+set_false_path -from [get_ports {pcie_reset}]
+set_input_delay 0 [get_ports {pcie_reset}]

src/cndm/board/NT200A02/fpga/fpga_nt200a02.xdc

@@ -0,0 +1,259 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Napatech NT200A02 board
+# part: xcvu5p-flva2104-2-e
+
+# General configuration
+set_property CFGBVS GND                                [current_design]
+set_property CONFIG_VOLTAGE 1.8                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
+set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
+
+# System clocks
+# 50 MHz system clock
+set_property -dict {LOC AK34 IOSTANDARD LVCMOS18} [get_ports clk_50mhz] ;# U10
+create_clock -period 20.000 -name clk_50mhz [get_ports clk_50mhz]
+
+# 80 MHz EMCCLK
+#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_80mhz] ;# U9
+#create_clock -period 12.500 -name clk_80mhz [get_ports clk_80mhz]
+
+# 20 MHz reference clock
+#set_property -dict {LOC AM33 IOSTANDARD LVCMOS18} [get_ports clk_20mhz] ;# U201/U22
+#create_clock -period 12.500 -name clk_20mhz [get_ports clk_20mhz]
+
+# 100 MHz DDR4 C0 clock from Si5340 OUT0 via U167
+#set_property -dict {LOC BA19 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c0_p]
+#set_property -dict {LOC AY19 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c0_n]
+#create_clock -period 10.000 -name clk_ddr_c0 [get_ports clk_ddr_c0_p]
+
+# 100 MHz DDR4 C1 clock from Si5340 OUT0 via U167
+#set_property -dict {LOC BB39 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c1_p]
+#set_property -dict {LOC BB38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c1_n]
+#create_clock -period 10.000 -name clk_ddr_c1 [get_ports clk_ddr_c1_p]
+
+# 100 MHz DDR4 C2 clock from Si5340 OUT0 via U167
+#set_property -dict {LOC B10  IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c2_p]
+#set_property -dict {LOC C10  IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c2_n]
+#create_clock -period 10.000 -name clk_ddr_c2 [get_ports clk_ddr_c2_p]
+
+# LEDs
+set_property -dict {LOC R26  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[0]}] ;# D5
+set_property -dict {LOC M28  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[1]}] ;# D6
+set_property -dict {LOC R27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[2]}] ;# D7
+set_property -dict {LOC T24  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[3]}] ;# D8
+set_property -dict {LOC J27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][0]}] ;# D16
+set_property -dict {LOC K27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][1]}] ;# D17
+set_property -dict {LOC L25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][2]}] ;# D18
+set_property -dict {LOC L24  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][3]}] ;# D29
+set_property -dict {LOC B28  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][0]}] ;# D27
+set_property -dict {LOC C27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][1]}] ;# D28
+set_property -dict {LOC J25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][2]}] ;# D29
+set_property -dict {LOC K26  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][3]}] ;# D30
+set_property -dict {LOC D27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_red}] ;# D52
+set_property -dict {LOC D26  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_green}] ;# D52
+set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_sync[0]}] ;# D54
+set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_sync[1]}] ;# D56
+set_property -dict {LOC M15  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {eth_led_yellow}] ;# J28
+set_property -dict {LOC M13  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {eth_led_green}] ;# J28
+
+set_false_path -to [get_ports {led[*] qsfp_led[*][*] led_red led_green led_sync[*] eth_led_yellow eth_led_green}]
+set_output_delay 0 [get_ports {led[*] qsfp_led[*][*] led_red led_green led_sync[*] eth_led_yellow eth_led_green}]
+
+# Si5340 U18
+set_property -dict {LOC AT36 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5340_i2c_scl] ;# U23.14 SCLK
+set_property -dict {LOC AT35 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5340_i2c_sda] ;# U23.13 SDA
+set_property -dict {LOC AT37 IOSTANDARD LVCMOS18} [get_ports si5340_intr] ;# U18.33 INTR
+
+set_false_path -to [get_ports {si5340_i2c_scl si5340_i2c_sda}]
+set_output_delay 0 [get_ports {si5340_i2c_scl si5340_i2c_sda}]
+set_false_path -from [get_ports {si5340_i2c_scl si5340_i2c_sda si5340_intr}]
+set_input_delay 0 [get_ports {si5340_i2c_scl si5340_i2c_sda si5340_intr}]
+
+# Gigabit PHY (DP83867)
+#set_property -dict {LOC P12  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_gtx_clk] ;# U198.29 GTX_CLK via ?
+#set_property -dict {LOC P15  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_tx_ctl] ;# U198.37 TX_CTRL via ?
+#set_property -dict {LOC R11  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] ;# U198.28 TX_D0/SGMII_SIN via ?
+#set_property -dict {LOC R12  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] ;# U198.27 TX_D1/SGMII_SIP via ?
+#set_property -dict {LOC P11  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] ;# U198.26 TX_D2 via ?
+#set_property -dict {LOC N12  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] ;# U198.25 TX_D3 via ?
+#set_property -dict {LOC U13  IOSTANDARD LVCMOS18} [get_ports phy_rx_clk] ;# U198.32 RX_CLK via ?
+#set_property -dict {LOC U16  IOSTANDARD LVCMOS18} [get_ports phy_rx_ctl] ;# U198.38 RX_CTRL via ?
+#set_property -dict {LOC T11  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[0]}] ;# U198.33 RX_D0/SGMII_COP via ?
+#set_property -dict {LOC U11  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[1]}] ;# U198.34 RX_D1/SGMII_CON via ?
+#set_property -dict {LOC R13  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[2]}] ;# U198.35 RX_D2/SGMII_SOP via ?
+#set_property -dict {LOC V15  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[3]}] ;# U198.36 RX_D3/SGMII_SON via ?
+#set_property -dict {LOC J11  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_refclk] ;# U198.15 XI 25 MHz
+#set_property -dict {LOC T14  IOSTANDARD LVCMOS18} [get_ports phy_clk_out] ;# U198.18 CLK_OUT
+#set_property -dict {LOC M11  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_reset_n] ;# U198.43 RESET_N
+#set_property -dict {LOC V16  IOSTANDARD LVCMOS18} [get_ports phy_int_n] ;# U198.44 PWRDOWN/INTN
+#set_property -dict {LOC U12  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_mdc] ;# U198.16 MDC
+#set_property -dict {LOC J12  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_mdio] ;# U198.17 MDIO
+#set_property -dict {LOC L14  IOSTANDARD LVCMOS18} [get_ports phy_gpio0] ;# U198.39 GPIO_0
+#set_property -dict {LOC M12  IOSTANDARD LVCMOS18} [get_ports phy_gpio1] ;# U198.40 GPIO_1
+#set_property -dict {LOC L15  IOSTANDARD LVCMOS18} [get_ports phy_led0] ;# U198.47 LED_0
+#set_property -dict {LOC W14  IOSTANDARD LVCMOS18} [get_ports phy_led1] ;# U198.46 LED_1
+#set_property -dict {LOC K14  IOSTANDARD LVCMOS18} [get_ports phy_led2] ;# U198.45 LED_2
+
+# QSFP28 Interfaces
+set_property -dict {LOC R45 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC R46 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC M42 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC M43 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC U45 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC U46 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC P42 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC P43 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC N45 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC N46 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC K42 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC K43 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC W45 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC W46 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC T42 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC T43 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC V38 } [get_ports qsfp0_mgt_refclk_p] ;# MGTREFCLK0P_131 from Si5340 U23 OUT1
+set_property -dict {LOC V39 } [get_ports qsfp0_mgt_refclk_n] ;# MGTREFCLK0N_131 from Si5340 U23 OUT1
+set_property -dict {LOC A26  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl]
+set_property -dict {LOC C25  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp0_modprsl]
+set_property -dict {LOC B26  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp0_intl]
+set_property -dict {LOC G25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode]
+set_property -dict {LOC B25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_scl]
+set_property -dict {LOC F25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_sda]
+
+# 322.265625 MHz MGT reference clock
+create_clock -period 3.103 -name qsfp0_mgt_refclk [get_ports qsfp0_mgt_refclk_p]
+
+set_false_path -to [get_ports {qsfp0_resetl qsfp0_lpmode}]
+set_output_delay 0 [get_ports {qsfp0_resetl qsfp0_lpmode}]
+set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
+set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
+
+set_false_path -to [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
+set_output_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
+set_false_path -from [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
+set_input_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
+
+set_property -dict {LOC G45 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC G46 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC D42 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC D43 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC J45 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC J46 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC F42 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC F43 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC E45 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC E46 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC B42 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC B43 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC L45 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC L46 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC H42 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC H43 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC R40 } [get_ports qsfp1_mgt_refclk_p] ;# MGTREFCLK0P_132 from Si5340 U23 OUT2
+set_property -dict {LOC R41 } [get_ports qsfp1_mgt_refclk_n] ;# MGTREFCLK0N_132 from Si5340 U23 OUT2
+set_property -dict {LOC B27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl]
+set_property -dict {LOC H28  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_modprsl]
+set_property -dict {LOC N24  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_intl]
+set_property -dict {LOC H25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode]
+set_property -dict {LOC P27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_scl]
+set_property -dict {LOC R24  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_sda]
+
+# 322.265625 MHz MGT reference clock
+create_clock -period 3.103 -name qsfp1_mgt_refclk [get_ports qsfp1_mgt_refclk_p]
+
+set_false_path -to [get_ports {qsfp1_resetl qsfp1_lpmode}]
+set_output_delay 0 [get_ports {qsfp1_resetl qsfp1_lpmode}]
+set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}]
+set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}]
+
+set_false_path -to [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
+set_output_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
+set_false_path -from [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
+set_input_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
+
+# PCIe Interface
+set_property -dict {LOC AA4 } [get_ports {pcie_rx_p[0]}]  ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
+set_property -dict {LOC AA3 } [get_ports {pcie_rx_n[0]}]  ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
+set_property -dict {LOC Y7  } [get_ports {pcie_tx_p[0]}]  ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
+set_property -dict {LOC Y6  } [get_ports {pcie_tx_n[0]}]  ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
+set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[1]}]  ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
+set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[1]}]  ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
+set_property -dict {LOC AB7 } [get_ports {pcie_tx_p[1]}]  ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
+set_property -dict {LOC AB6 } [get_ports {pcie_tx_n[1]}]  ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
+set_property -dict {LOC AC4 } [get_ports {pcie_rx_p[2]}]  ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
+set_property -dict {LOC AC3 } [get_ports {pcie_rx_n[2]}]  ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
+set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[2]}]  ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
+set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[2]}]  ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
+set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[3]}]  ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
+set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[3]}]  ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
+set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[3]}]  ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
+set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[3]}]  ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
+set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[4]}]  ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
+set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[4]}]  ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
+set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[4]}]  ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
+set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[4]}]  ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
+set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[5]}]  ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
+set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[5]}]  ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
+set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[5]}]  ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
+set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[5]}]  ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
+set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[6]}]  ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
+set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[6]}]  ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
+set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}]  ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
+set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}]  ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
+set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[7]}]  ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
+set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[7]}]  ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
+set_property -dict {LOC AN5 } [get_ports {pcie_tx_p[7]}]  ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
+set_property -dict {LOC AN4 } [get_ports {pcie_tx_n[7]}]  ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
+set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[8]}]  ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
+set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[8]}]  ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
+set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}]  ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
+set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}]  ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
+set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[9]}]  ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
+set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[9]}]  ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
+set_property -dict {LOC AR5 } [get_ports {pcie_tx_p[9]}]  ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
+set_property -dict {LOC AR4 } [get_ports {pcie_tx_n[9]}]  ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
+set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
+set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
+set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
+set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
+set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
+set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
+set_property -dict {LOC AU5 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
+set_property -dict {LOC AU4 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
+set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
+set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
+set_property -dict {LOC AW5 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
+set_property -dict {LOC AW4 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
+set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
+set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
+set_property -dict {LOC BA5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
+set_property -dict {LOC BA4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
+set_property -dict {LOC AY2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
+set_property -dict {LOC AY1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
+set_property -dict {LOC BC5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
+set_property -dict {LOC BC4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
+set_property -dict {LOC BB2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
+set_property -dict {LOC BB1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
+set_property -dict {LOC BE5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
+set_property -dict {LOC BE4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
+set_property -dict {LOC AG9 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_226
+set_property -dict {LOC AG8 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_226
+set_property -dict {LOC AM17 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset]
+
+# 100 MHz MGT reference clock
+create_clock -period 10.000 -name pcie_mgt_refclk [get_ports pcie_refclk_p]
+
+set_false_path -from [get_ports {pcie_reset}]
+set_input_delay 0 [get_ports {pcie_reset}]

src/cndm/board/NT200A02/fpga/ip/pcie3_ultrascale_0.tcl

@@ -0,0 +1,31 @@
+
+create_ip -name pcie3_ultrascale -vendor xilinx.com -library ip -module_name pcie3_ultrascale_0
+
+set_property -dict [list \
+    CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
+    CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
+    CONFIG.AXISTEN_IF_RC_STRADDLE {false} \
+    CONFIG.axisten_if_enable_client_tag {true} \
+    CONFIG.axisten_if_width {256_bit} \
+    CONFIG.extended_tag_field {true} \
+    CONFIG.pf0_dev_cap_max_payload {1024_bytes} \
+    CONFIG.axisten_freq {250} \
+    CONFIG.PF0_Use_Class_Code_Lookup_Assistant {false} \
+    CONFIG.pf0_class_code_base {02} \
+    CONFIG.pf0_class_code_sub {00} \
+    CONFIG.pf0_class_code_interface {00} \
+    CONFIG.PF0_DEVICE_ID {C001} \
+    CONFIG.PF0_SUBSYSTEM_ID {01a5} \
+    CONFIG.PF0_SUBSYSTEM_VENDOR_ID {18f4} \
+    CONFIG.pf0_bar0_64bit {true} \
+    CONFIG.pf0_bar0_prefetchable {true} \
+    CONFIG.pf0_bar0_scale {Megabytes} \
+    CONFIG.pf0_bar0_size {16} \
+    CONFIG.pf0_msi_enabled {true} \
+    CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
+    CONFIG.en_msi_per_vec_masking {true} \
+    CONFIG.ext_pcie_cfg_space_enabled {true} \
+    CONFIG.vendor_id {1234} \
+    CONFIG.pcie_blk_locn {X0Y1} \
+    CONFIG.mode_selection {Advanced} \
+] [get_ips pcie3_ultrascale_0]

src/cndm/board/NT200A02/fpga/ip/pcie4_uscale_plus_0.tcl

@@ -0,0 +1,31 @@
+
+create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0
+
+set_property -dict [list \
+    CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
+    CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {false} \
+    CONFIG.axisten_if_enable_client_tag {true} \
+    CONFIG.axisten_if_width {512_bit} \
+    CONFIG.extended_tag_field {true} \
+    CONFIG.pf0_dev_cap_max_payload {1024_bytes} \
+    CONFIG.axisten_freq {250} \
+    CONFIG.PF0_Use_Class_Code_Lookup_Assistant {false} \
+    CONFIG.PF0_CLASS_CODE {020000} \
+    CONFIG.PF0_DEVICE_ID {C001} \
+    CONFIG.PF0_SUBSYSTEM_ID {01c5} \
+    CONFIG.PF0_SUBSYSTEM_VENDOR_ID {18f4} \
+    CONFIG.pf0_bar0_64bit {true} \
+    CONFIG.pf0_bar0_prefetchable {true} \
+    CONFIG.pf0_bar0_scale {Megabytes} \
+    CONFIG.pf0_bar0_size {16} \
+    CONFIG.pf0_msi_enabled {true} \
+    CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
+    CONFIG.en_msi_per_vec_masking {true} \
+    CONFIG.ext_pcie_cfg_space_enabled {true} \
+    CONFIG.vendor_id {1234} \
+    CONFIG.pcie_blk_locn {X1Y0} \
+    CONFIG.mode_selection {Advanced} \
+] [get_ips pcie4_uscale_plus_0]

src/cndm/board/NT200A02/fpga/lib/taxi

@@ -0,0 +1 @@
+../../../../../../

src/cndm/board/NT200A02/fpga/pll/Si5340-RevD-NT200-Registers.txt

@@ -0,0 +1,351 @@
+# Si534x/7x/8x/9x Registers Script
+# 
+# Part: Si5340
+# Project File: X:\Projects\taxi-corundum\src\eth\example\NT200A02\fpga\pll\Si5340-RevD-NT200-Project.slabtimeproj
+# Design ID: NT200
+# Includes Pre/Post Download Control Register Writes: Yes
+# Die Revision: B1
+# Creator: ClockBuilder Pro v4.1 [2021-09-22]
+# Created On: 2026-04-04 21:47:23 GMT-07:00
+Address,Data
+# 
+# Start configuration preamble
+0x0B24,0xC0
+0x0B25,0x00
+# Rev D stuck divider fix
+0x0502,0x01
+0x0505,0x03
+0x0957,0x17
+0x0B4E,0x1A
+# End configuration preamble
+# 
+# Delay 300 msec
+#    Delay is worst case time for device to complete any calibration
+#    that is running due to device state change previous to this script
+#    being processed.
+# 
+# Start configuration registers
+0x0006,0x00
+0x0007,0x00
+0x0008,0x00
+0x000B,0x74
+0x0017,0xD0
+0x0018,0xFF
+0x0021,0x0F
+0x0022,0x00
+0x002B,0x02
+0x002C,0x20
+0x002D,0x00
+0x002E,0x00
+0x002F,0x00
+0x0030,0x00
+0x0031,0x00
+0x0032,0x00
+0x0033,0x00
+0x0034,0x00
+0x0035,0x00
+0x0036,0x00
+0x0037,0x00
+0x0038,0x00
+0x0039,0x00
+0x003A,0x00
+0x003B,0x00
+0x003C,0x00
+0x003D,0x00
+0x0041,0x00
+0x0042,0x00
+0x0043,0x00
+0x0044,0x00
+0x009E,0x00
+0x0102,0x01
+0x0112,0x06
+0x0113,0x09
+0x0114,0x3B
+0x0115,0x28
+0x0117,0x06
+0x0118,0x09
+0x0119,0x3B
+0x011A,0x29
+0x0126,0x06
+0x0127,0x09
+0x0128,0x3B
+0x0129,0x29
+0x012B,0x06
+0x012C,0x09
+0x012D,0x3B
+0x012E,0x29
+0x013F,0x00
+0x0140,0x00
+0x0141,0x40
+0x0206,0x00
+0x0208,0x00
+0x0209,0x00
+0x020A,0x00
+0x020B,0x00
+0x020C,0x00
+0x020D,0x00
+0x020E,0x00
+0x020F,0x00
+0x0210,0x00
+0x0211,0x00
+0x0212,0x00
+0x0213,0x00
+0x0214,0x00
+0x0215,0x00
+0x0216,0x00
+0x0217,0x00
+0x0218,0x00
+0x0219,0x00
+0x021A,0x00
+0x021B,0x00
+0x021C,0x00
+0x021D,0x00
+0x021E,0x00
+0x021F,0x00
+0x0220,0x00
+0x0221,0x00
+0x0222,0x00
+0x0223,0x00
+0x0224,0x00
+0x0225,0x00
+0x0226,0x00
+0x0227,0x00
+0x0228,0x00
+0x0229,0x00
+0x022A,0x00
+0x022B,0x00
+0x022C,0x00
+0x022D,0x00
+0x022E,0x00
+0x022F,0x00
+0x0235,0xA0
+0x0236,0x2A
+0x0237,0xCD
+0x0238,0xD8
+0x0239,0xAD
+0x023A,0x00
+0x023B,0x00
+0x023C,0x80
+0x023D,0x96
+0x023E,0x98
+0x0250,0x00
+0x0251,0x00
+0x0252,0x00
+0x0253,0x00
+0x0254,0x00
+0x0255,0x00
+0x025C,0x00
+0x025D,0x00
+0x025E,0x00
+0x025F,0x00
+0x0260,0x00
+0x0261,0x00
+0x026B,0x4E
+0x026C,0x54
+0x026D,0x32
+0x026E,0x30
+0x026F,0x30
+0x0270,0x00
+0x0271,0x00
+0x0272,0x00
+0x0302,0x00
+0x0303,0x00
+0x0304,0x00
+0x0305,0x00
+0x0306,0x0F
+0x0307,0x00
+0x0308,0x00
+0x0309,0x00
+0x030A,0x00
+0x030B,0x80
+0x030C,0x00
+0x030D,0xAA
+0x030E,0xD2
+0x030F,0x8C
+0x0310,0xDD
+0x0311,0x0A
+0x0312,0x00
+0x0313,0xFC
+0x0314,0x8D
+0x0315,0x0E
+0x0316,0x80
+0x0317,0x00
+0x0318,0x00
+0x0319,0x00
+0x031A,0x00
+0x031B,0x00
+0x031C,0x00
+0x031D,0x00
+0x031E,0x00
+0x031F,0x00
+0x0320,0x00
+0x0321,0x00
+0x0322,0x00
+0x0323,0x00
+0x0324,0x00
+0x0325,0x00
+0x0326,0x00
+0x0327,0x00
+0x0328,0x00
+0x0329,0x00
+0x032A,0x00
+0x032B,0x00
+0x032C,0x00
+0x032D,0x00
+0x0338,0x00
+0x0339,0x1F
+0x033B,0x00
+0x033C,0x00
+0x033D,0x00
+0x033E,0x00
+0x033F,0x00
+0x0340,0x00
+0x0341,0x00
+0x0342,0x00
+0x0343,0x00
+0x0344,0x00
+0x0345,0x00
+0x0346,0x00
+0x0347,0x00
+0x0348,0x00
+0x0349,0x00
+0x034A,0x00
+0x034B,0x00
+0x034C,0x00
+0x034D,0x00
+0x034E,0x00
+0x034F,0x00
+0x0350,0x00
+0x0351,0x00
+0x0352,0x00
+0x0359,0x00
+0x035A,0x00
+0x035B,0x00
+0x035C,0x00
+0x035D,0x00
+0x035E,0x00
+0x035F,0x00
+0x0360,0x00
+0x0802,0x00
+0x0803,0x00
+0x0804,0x00
+0x0805,0x00
+0x0806,0x00
+0x0807,0x00
+0x0808,0x00
+0x0809,0x00
+0x080A,0x00
+0x080B,0x00
+0x080C,0x00
+0x080D,0x00
+0x080E,0x00
+0x080F,0x00
+0x0810,0x00
+0x0811,0x00
+0x0812,0x00
+0x0813,0x00
+0x0814,0x00
+0x0815,0x00
+0x0816,0x00
+0x0817,0x00
+0x0818,0x00
+0x0819,0x00
+0x081A,0x00
+0x081B,0x00
+0x081C,0x00
+0x081D,0x00
+0x081E,0x00
+0x081F,0x00
+0x0820,0x00
+0x0821,0x00
+0x0822,0x00
+0x0823,0x00
+0x0824,0x00
+0x0825,0x00
+0x0826,0x00
+0x0827,0x00
+0x0828,0x00
+0x0829,0x00
+0x082A,0x00
+0x082B,0x00
+0x082C,0x00
+0x082D,0x00
+0x082E,0x00
+0x082F,0x00
+0x0830,0x00
+0x0831,0x00
+0x0832,0x00
+0x0833,0x00
+0x0834,0x00
+0x0835,0x00
+0x0836,0x00
+0x0837,0x00
+0x0838,0x00
+0x0839,0x00
+0x083A,0x00
+0x083B,0x00
+0x083C,0x00
+0x083D,0x00
+0x083E,0x00
+0x083F,0x00
+0x0840,0x00
+0x0841,0x00
+0x0842,0x00
+0x0843,0x00
+0x0844,0x00
+0x0845,0x00
+0x0846,0x00
+0x0847,0x00
+0x0848,0x00
+0x0849,0x00
+0x084A,0x00
+0x084B,0x00
+0x084C,0x00
+0x084D,0x00
+0x084E,0x00
+0x084F,0x00
+0x0850,0x00
+0x0851,0x00
+0x0852,0x00
+0x0853,0x00
+0x0854,0x00
+0x0855,0x00
+0x0856,0x00
+0x0857,0x00
+0x0858,0x00
+0x0859,0x00
+0x085A,0x00
+0x085B,0x00
+0x085C,0x00
+0x085D,0x00
+0x085E,0x00
+0x085F,0x00
+0x0860,0x00
+0x0861,0x00
+0x090E,0x02
+0x091C,0x04
+0x0943,0x00
+0x0949,0x00
+0x094A,0x00
+0x094E,0x49
+0x094F,0x02
+0x095E,0x00
+0x0A02,0x00
+0x0A03,0x03
+0x0A04,0x01
+0x0A05,0x03
+0x0A14,0x00
+0x0A1A,0x00
+0x0A20,0x00
+0x0A26,0x00
+0x0B44,0x0F
+0x0B4A,0x0C
+0x0B57,0x0E
+0x0B58,0x01
+# End configuration registers
+# 
+# Start configuration postamble
+0x001C,0x01
+0x0B24,0xC3
+0x0B25,0x02
+# End configuration postamble

src/cndm/board/NT200A02/fpga/pll/si5340_i2c_init.py

@@ -0,0 +1,642 @@
+#!/usr/bin/env python
+"""
+Generates an I2C init module for multiple chips
+"""
+
+from jinja2 import Template
+
+
+def si5340_cmds(regs, dev_addr=0x77):
+    cur_page = None
+    cur_addr = None
+
+    cmds = []
+
+    print(f"Reading register list file '{regs}'...")
+
+    with open(regs, "r") as f:
+        for line in f:
+            line = line.strip()
+            if not line or line == "Address,Data":
+                continue
+            if line[0] == '#':
+                cmds.append(f"// {line[1:].strip()}")
+
+                if line.startswith("# Delay"):
+                    cmds.append("cmd_delay(10); // delay 300 ms")
+                    cur_addr = None
+
+                continue
+
+            d = line.split(",")
+            addr = int(d[0], 0)
+            page = (addr >> 8) & 0xff
+            data = int(d[1], 0)
+
+            if page != cur_page:
+                cmds.append(f"cmd_start(7'h{dev_addr:02x});")
+                cmds.append("cmd_wr(8'h01);")
+                cmds.append(f"cmd_wr(8'h{page:02x}); // set page {page:#04x}")
+                cur_page = page
+                cur_addr = None
+
+            if addr != cur_addr:
+                cmds.append(f"cmd_start(7'h{dev_addr:02x});")
+                cmds.append(f"cmd_wr(8'h{addr & 0xff:02x});")
+                cur_addr = addr
+
+            cmds.append(f"cmd_wr(8'h{data:02x}); // write {data:#04x} to {addr:#06x}")
+            cur_addr += 1
+
+    return cmds
+
+
+def mux_cmds(val, dev_addr):
+    cmds = []
+    cmds.append(f"cmd_start(7'h{dev_addr:02x});")
+    cmds.append(f"cmd_wr(8'h{val:02x});")
+    cmds.append("cmd_stop(); // I2C stop")
+    return cmds
+
+
+def main():
+    cmds = []
+
+    cmds.append("// Initial delay")
+    cmds.append("cmd_delay(6); // delay 30 ms")
+
+    cmds.extend(si5340_cmds("Si5340-RevD-NT200-Registers.txt", 0x74))
+
+    generate(cmds, output="si5340_i2c_init.sv")
+
+
+def generate(cmds=None, name=None, output=None):
+    if cmds is None:
+        raise Exception("Command list is required")
+
+    if name is None:
+        name = "si5340_i2c_init"
+
+    if output is None:
+        output = name + ".sv"
+
+    print(f"Generating Si5340 I2C init module {name}...")
+
+    cmds = cmds.copy()
+    cmds.append("cmd_halt(); // end")
+
+    cmd_str = ""
+    cmd_count = 0
+
+    for cmd in cmds:
+        if cmd.startswith('//'):
+            cmd_str += f"    {cmd}\n"
+        else:
+            cmd_str += f"    init_data[{cmd_count}] = {cmd}\n"
+            cmd_count += 1
+
+    t = Template(u"""// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2015-2026 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * {{name}}
+ */
+module {{name}} #
+(
+    parameter logic SIM_SPEEDUP = 1'b0
+)
+(
+    input  wire logic  clk,
+    input  wire logic  rst,
+
+    /*
+     * I2C master interface
+     */
+    taxi_axis_if.src   m_axis_cmd,
+    taxi_axis_if.src   m_axis_tx,
+
+    /*
+     * Status
+     */
+    output wire logic  busy,
+
+    /*
+     * Configuration
+     */
+    input  wire logic  start
+);
+
+/*
+
+Generic module for I2C bus initialization.  Good for use when multiple devices
+on an I2C bus must be initialized on system start without intervention of a
+general-purpose processor.
+
+Copy this file and change init_data and INIT_DATA_LEN as needed.
+
+This module can be used in two modes: simple device initialization, or multiple
+device initialization.  In multiple device mode, the same initialization sequence
+can be performed on multiple different device addresses.
+
+To use single device mode, only use the start write to address and write data commands.
+The module will generate the I2C commands in sequential order.  Terminate the list
+with a 0 entry.
+
+To use the multiple device mode, use the start data and start address block commands
+to set up lists of initialization data and device addresses.  The module enters
+multiple device mode upon seeing a start data block command.  The module stores the
+offset of the start of the data block and then skips ahead until it reaches a start
+address block command.  The module will store the offset to the address block and
+read the first address in the block.  Then it will jump back to the data block
+and execute it, substituting the stored address for each current address write
+command.  Upon reaching the start address block command, the module will read out the
+next address and start again at the top of the data block.  If the module encounters
+a start data block command while looking for an address, then it will store a new data
+offset and then look for a start address block command.  Terminate the list with a 0
+entry.  Normal address commands will operate normally inside a data block.
+
+Commands:
+
+00 0000000 : stop
+00 0000001 : exit multiple device mode
+00 0000011 : start write to current address
+00 0001000 : start address block
+00 0001001 : start data block
+00 001dddd : delay 2**(16+d) cycles
+00 1000001 : send I2C stop
+01 aaaaaaa : start write to address
+1 dddddddd : write 8-bit data
+
+Examples
+
+write 0x11223344 to register 0x0004 on device at 0x50
+
+01 1010000  start write to 0x50
+1 00000000  write address 0x0004
+1 00000100
+1 00010001  write data 0x11223344
+1 00100010
+1 00110011
+1 01000100
+0 00000000  stop
+
+write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53
+
+00 0001001  start data block
+00 0000011  start write to current address
+1 00000000  write address 0x0004
+1 00000100
+1 00010001  write data 0x11223344
+1 00100010
+1 00110011
+1 01000100
+00 0001000  start address block
+01 1010000  address 0x50
+01 1010001  address 0x51
+01 1010010  address 0x52
+01 1010011  address 0x53
+00 0000001  exit multi-dev mode
+00 0000000  stop
+
+*/
+
+// check configuration
+if (m_axis_cmd.DATA_W < 12)
+    $fatal(0, "Command interface width must be at least 12 bits (instance %m)");
+
+if (m_axis_tx.DATA_W != 8)
+    $fatal(0, "Data interface width must be 8 bits (instance %m)");
+
+function [8:0] cmd_start(input [6:0] addr);
+    cmd_start = {2'b01, addr};
+endfunction
+
+function [8:0] cmd_wr(input [7:0] data);
+    cmd_wr = {1'b1, data};
+endfunction
+
+function [8:0] cmd_stop();
+    cmd_stop = {2'b00, 7'b1000001};
+endfunction
+
+function [8:0] cmd_delay(input [3:0] d);
+    cmd_delay = {2'b00, 3'b001, d};
+endfunction
+
+function [8:0] cmd_halt();
+    cmd_halt = 9'd0;
+endfunction
+
+function [8:0] blk_start_data();
+    blk_start_data = {2'b00, 7'b0001001};
+endfunction
+
+function [8:0] blk_start_addr();
+    blk_start_addr = {2'b00, 7'b0001000};
+endfunction
+
+function [8:0] cmd_start_cur();
+    cmd_start_cur = {2'b00, 7'b0000011};
+endfunction
+
+function [8:0] cmd_exit();
+    cmd_exit = {2'b00, 7'b0000001};
+endfunction
+
+// init_data ROM
+localparam INIT_DATA_LEN = {{cmd_count}};
+
+reg [8:0] init_data [INIT_DATA_LEN-1:0];
+
+initial begin
+{{cmd_str-}}
+end
+
+typedef enum logic [2:0] {
+    STATE_IDLE,
+    STATE_RUN,
+    STATE_TABLE_1,
+    STATE_TABLE_2,
+    STATE_TABLE_3
+} state_t;
+
+state_t state_reg = STATE_IDLE, state_next;
+
+localparam AW = $clog2(INIT_DATA_LEN);
+
+logic [8:0] init_data_reg = '0;
+
+logic [AW-1:0] address_reg = '0, address_next;
+logic [AW-1:0] address_ptr_reg = '0, address_ptr_next;
+logic [AW-1:0] data_ptr_reg = '0, data_ptr_next;
+
+logic [6:0] cur_address_reg = '0, cur_address_next;
+
+logic [31:0] delay_counter_reg = '0, delay_counter_next;
+
+logic [6:0] m_axis_cmd_address_reg = '0, m_axis_cmd_address_next;
+logic m_axis_cmd_start_reg = 1'b0, m_axis_cmd_start_next;
+logic m_axis_cmd_write_reg = 1'b0, m_axis_cmd_write_next;
+logic m_axis_cmd_stop_reg = 1'b0, m_axis_cmd_stop_next;
+logic m_axis_cmd_valid_reg = 1'b0, m_axis_cmd_valid_next;
+
+logic [7:0] m_axis_tx_tdata_reg = '0, m_axis_tx_tdata_next;
+logic m_axis_tx_tvalid_reg = 1'b0, m_axis_tx_tvalid_next;
+
+logic start_flag_reg = 1'b0, start_flag_next;
+
+logic busy_reg = 1'b0;
+
+assign m_axis_cmd.tdata[6:0] = m_axis_cmd_address_reg;
+assign m_axis_cmd.tdata[7]   = m_axis_cmd_start_reg;
+assign m_axis_cmd.tdata[8]   = 1'b0; // read
+assign m_axis_cmd.tdata[9]   = m_axis_cmd_write_reg;
+assign m_axis_cmd.tdata[10]  = 1'b0; // write multi
+assign m_axis_cmd.tdata[11]  = m_axis_cmd_stop_reg;
+assign m_axis_cmd.tvalid = m_axis_cmd_valid_reg;
+assign m_axis_cmd.tlast = 1'b1;
+assign m_axis_cmd.tid = '0;
+assign m_axis_cmd.tdest = '0;
+assign m_axis_cmd.tuser = '0;
+
+assign m_axis_tx.tdata = m_axis_tx_tdata_reg;
+assign m_axis_tx.tvalid = m_axis_tx_tvalid_reg;
+assign m_axis_tx.tlast = 1'b1;
+assign m_axis_tx.tid = '0;
+assign m_axis_tx.tdest = '0;
+assign m_axis_tx.tuser = '0;
+
+assign busy = busy_reg;
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    address_next = address_reg;
+    address_ptr_next = address_ptr_reg;
+    data_ptr_next = data_ptr_reg;
+
+    cur_address_next = cur_address_reg;
+
+    delay_counter_next = delay_counter_reg;
+
+    m_axis_cmd_address_next = m_axis_cmd_address_reg;
+    m_axis_cmd_start_next = m_axis_cmd_start_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
+    m_axis_cmd_write_next = m_axis_cmd_write_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
+    m_axis_cmd_stop_next = m_axis_cmd_stop_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
+    m_axis_cmd_valid_next = m_axis_cmd_valid_reg && !m_axis_cmd.tready;
+
+    m_axis_tx_tdata_next = m_axis_tx_tdata_reg;
+    m_axis_tx_tvalid_next = m_axis_tx_tvalid_reg && !m_axis_tx.tready;
+
+    start_flag_next = start_flag_reg;
+
+    if (m_axis_cmd.tvalid || m_axis_tx.tvalid) begin
+        // wait for output registers to clear
+        state_next = state_reg;
+    end else if (delay_counter_reg != 0) begin
+        // delay
+        delay_counter_next = delay_counter_reg - 1;
+        state_next = state_reg;
+    end else begin
+        case (state_reg)
+            STATE_IDLE: begin
+                // wait for start signal
+                if (!start_flag_reg && start) begin
+                    address_next = '0;
+                    start_flag_next = 1'b1;
+                    state_next = STATE_RUN;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_RUN: begin
+                // process commands
+                if (init_data_reg[8] == 1'b1) begin
+                    // write data
+                    m_axis_cmd_write_next = 1'b1;
+                    m_axis_cmd_stop_next = 1'b0;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    m_axis_tx_tdata_next = init_data_reg[7:0];
+                    m_axis_tx_tvalid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg[8:7] == 2'b01) begin
+                    // write address
+                    m_axis_cmd_address_next = init_data_reg[6:0];
+                    m_axis_cmd_start_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg[8:4] == 5'b00001) begin
+                    // delay
+                    if (SIM_SPEEDUP) begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]);
+                    end else begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]+16);
+                    end
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'b001000001) begin
+                    // send stop
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end
+            end
+            STATE_TABLE_1: begin
+                // find address table start
+                if (init_data_reg == 9'b000001000) begin
+                    // address table start
+                    address_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_2;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 1) begin
+                    // exit mode
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end
+            end
+            STATE_TABLE_2: begin
+                // find next address
+                if (init_data_reg[8:7] == 2'b01) begin
+                    // write address command
+                    // store address and move to data table
+                    cur_address_next = init_data_reg[6:0];
+                    address_ptr_next = address_reg + 1;
+                    address_next = data_ptr_reg;
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 9'd1) begin
+                    // exit mode
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_2;
+                end
+            end
+            STATE_TABLE_3: begin
+                // process data table with selected address
+                if (init_data_reg[8] == 1'b1) begin
+                    // write data
+                    m_axis_cmd_write_next = 1'b1;
+                    m_axis_cmd_stop_next = 1'b0;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    m_axis_tx_tdata_next = init_data_reg[7:0];
+                    m_axis_tx_tvalid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg[8:7] == 2'b01) begin
+                    // write address
+                    m_axis_cmd_address_next = init_data_reg[6:0];
+                    m_axis_cmd_start_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b000000011) begin
+                    // write current address
+                    m_axis_cmd_address_next = cur_address_reg;
+                    m_axis_cmd_start_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg[8:4] == 5'b00001) begin
+                    // delay
+                    if (SIM_SPEEDUP) begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]);
+                    end else begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]+16);
+                    end
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b001000001) begin
+                    // send stop
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 9'b000001000) begin
+                    // address table start
+                    address_next = address_ptr_reg;
+                    state_next = STATE_TABLE_2;
+                end else if (init_data_reg == 9'd1) begin
+                    // exit mode
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_3;
+                end
+            end
+            default: begin
+                // invalid state
+                state_next = STATE_IDLE;
+            end
+        endcase
+    end
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+
+    // read init_data ROM
+    init_data_reg <= init_data[address_next];
+
+    address_reg <= address_next;
+    address_ptr_reg <= address_ptr_next;
+    data_ptr_reg <= data_ptr_next;
+
+    cur_address_reg <= cur_address_next;
+
+    delay_counter_reg <= delay_counter_next;
+
+    m_axis_cmd_address_reg <= m_axis_cmd_address_next;
+    m_axis_cmd_start_reg <= m_axis_cmd_start_next;
+    m_axis_cmd_write_reg <= m_axis_cmd_write_next;
+    m_axis_cmd_stop_reg <= m_axis_cmd_stop_next;
+    m_axis_cmd_valid_reg <= m_axis_cmd_valid_next;
+
+    m_axis_tx_tdata_reg <= m_axis_tx_tdata_next;
+    m_axis_tx_tvalid_reg <= m_axis_tx_tvalid_next;
+
+    start_flag_reg <= start && start_flag_next;
+
+    busy_reg <= (state_reg != STATE_IDLE);
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+
+        init_data_reg <= '0;
+
+        address_reg <= '0;
+        address_ptr_reg <= '0;
+        data_ptr_reg <= '0;
+
+        cur_address_reg <= '0;
+
+        delay_counter_reg <= '0;
+
+        m_axis_cmd_valid_reg <= 1'b0;
+
+        m_axis_tx_tvalid_reg <= 1'b0;
+
+        start_flag_reg <= 1'b0;
+
+        busy_reg <= 1'b0;
+    end
+end
+
+endmodule
+
+`resetall
+""")
+
+    print(f"Writing file '{output}'...")
+
+    with open(output, 'w') as f:
+        f.write(t.render(
+            cmd_str=cmd_str,
+            cmd_count=cmd_count,
+            name=name
+        ))
+        f.flush()
+
+    print("Done")
+
+
+if __name__ == "__main__":
+    main()

src/cndm/board/NT200A02/fpga/rtl/fpga_core.sv

@@ -0,0 +1,731 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2014-2026 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA core logic
+ */
+module fpga_core #
+(
+    // simulation (set to avoid vendor primitives)
+    parameter logic SIM = 1'b0,
+    // vendor ("GENERIC", "XILINX", "ALTERA")
+    parameter string VENDOR = "XILINX",
+    // device family
+    parameter string FAMILY = "virtexuplus",
+
+    // Board configuration
+    parameter PORT_CNT = 2,
+    parameter GTY_QUAD_CNT = PORT_CNT,
+    parameter GTY_CNT = GTY_QUAD_CNT*4,
+    parameter GTY_CLK_CNT = GTY_QUAD_CNT,
+
+    // FW ID
+    parameter FPGA_ID = 32'h4B2B093,
+    parameter FW_ID = 32'h0000C001,
+    parameter FW_VER = 32'h000_01_000,
+    parameter BOARD_ID = 32'h18f4_01c5,
+    parameter BOARD_VER = 32'h001_00_000,
+    parameter BUILD_DATE = 32'd602976000,
+    parameter GIT_HASH = 32'h5f87c2e8,
+    parameter RELEASE_INFO = 32'h00000000,
+
+    // PTP configuration
+    parameter logic PTP_TS_EN = 1'b1,
+    parameter PTP_CLK_PER_NS_NUM = 512,
+    parameter PTP_CLK_PER_NS_DEN = 165,
+
+    // PCIe interface configuration
+    parameter RQ_SEQ_NUM_W = 6,
+
+    // AXI lite interface configuration (control)
+    parameter AXIL_CTRL_DATA_W = 32,
+    parameter AXIL_CTRL_ADDR_W = 24,
+
+    // MAC configuration
+    parameter logic CFG_LOW_LATENCY = 1'b1,
+    parameter logic COMBINED_MAC_PCS = 1'b1,
+    parameter MAC_DATA_W = 64
+)
+(
+    /*
+     * Clock: 125 MHz
+     * Synchronous reset
+     */
+    input  wire logic                     clk_125mhz,
+    input  wire logic                     rst_125mhz,
+
+    /*
+     * GPIO
+     */
+    output wire logic [3:0]               led,
+    output wire logic [3:0]               qsfp_led[PORT_CNT],
+    output wire logic                     led_red,
+    output wire logic                     led_green,
+    output wire logic [1:0]               led_sync,
+    output wire logic                     eth_led_yellow,
+    output wire logic                     eth_led_green,
+
+    /*
+     * Ethernet: QSFP28
+     */
+    output wire logic                     eth_gty_tx_p[GTY_CNT],
+    output wire logic                     eth_gty_tx_n[GTY_CNT],
+    input  wire logic                     eth_gty_rx_p[GTY_CNT],
+    input  wire logic                     eth_gty_rx_n[GTY_CNT],
+    input  wire logic                     eth_gty_mgt_refclk_p[GTY_CLK_CNT],
+    input  wire logic                     eth_gty_mgt_refclk_n[GTY_CLK_CNT],
+    output wire logic                     eth_gty_mgt_refclk_out[GTY_CLK_CNT],
+
+    output wire logic [PORT_CNT-1:0]      eth_port_resetl,
+    input  wire logic [PORT_CNT-1:0]      eth_port_modprsl,
+    input  wire logic [PORT_CNT-1:0]      eth_port_intl,
+    output wire logic [PORT_CNT-1:0]      eth_port_lpmode,
+
+    input  wire logic [PORT_CNT-1:0]      eth_port_i2c_scl_i,
+    output wire logic [PORT_CNT-1:0]      eth_port_i2c_scl_o,
+    input  wire logic [PORT_CNT-1:0]      eth_port_i2c_sda_i,
+    output wire logic [PORT_CNT-1:0]      eth_port_i2c_sda_o,
+
+    /*
+     * PCIe
+     */
+    input  wire logic                     pcie_clk,
+    input  wire logic                     pcie_rst,
+    taxi_axis_if.snk                      s_axis_pcie_cq,
+    taxi_axis_if.src                      m_axis_pcie_cc,
+    taxi_axis_if.src                      m_axis_pcie_rq,
+    taxi_axis_if.snk                      s_axis_pcie_rc,
+
+    input  wire logic [RQ_SEQ_NUM_W-1:0]  pcie_rq_seq_num0,
+    input  wire logic                     pcie_rq_seq_num_vld0,
+    input  wire logic [RQ_SEQ_NUM_W-1:0]  pcie_rq_seq_num1,
+    input  wire logic                     pcie_rq_seq_num_vld1,
+
+    input  wire logic [2:0]               cfg_max_payload,
+    input  wire logic [2:0]               cfg_max_read_req,
+    input  wire logic [3:0]               cfg_rcb_status,
+
+    output wire logic [9:0]               cfg_mgmt_addr,
+    output wire logic [7:0]               cfg_mgmt_function_number,
+    output wire logic                     cfg_mgmt_write,
+    output wire logic [31:0]              cfg_mgmt_write_data,
+    output wire logic [3:0]               cfg_mgmt_byte_enable,
+    output wire logic                     cfg_mgmt_read,
+    output wire logic [31:0]              cfg_mgmt_read_data,
+    input  wire logic                     cfg_mgmt_read_write_done,
+
+    input  wire logic [7:0]               cfg_fc_ph,
+    input  wire logic [11:0]              cfg_fc_pd,
+    input  wire logic [7:0]               cfg_fc_nph,
+    input  wire logic [11:0]              cfg_fc_npd,
+    input  wire logic [7:0]               cfg_fc_cplh,
+    input  wire logic [11:0]              cfg_fc_cpld,
+    output wire logic [2:0]               cfg_fc_sel,
+
+    input  wire logic                     cfg_ext_read_received,
+    input  wire logic                     cfg_ext_write_received,
+    input  wire logic [9:0]               cfg_ext_register_number,
+    input  wire logic [7:0]               cfg_ext_function_number,
+    input  wire logic [31:0]              cfg_ext_write_data,
+    input  wire logic [3:0]               cfg_ext_write_byte_enable,
+    output wire logic [31:0]              cfg_ext_read_data,
+    output wire logic                     cfg_ext_read_data_valid,
+
+    input  wire logic [3:0]               cfg_interrupt_msi_enable,
+    input  wire logic [11:0]              cfg_interrupt_msi_mmenable,
+    input  wire logic                     cfg_interrupt_msi_mask_update,
+    input  wire logic [31:0]              cfg_interrupt_msi_data,
+    output wire logic [1:0]               cfg_interrupt_msi_select,
+    output wire logic [31:0]              cfg_interrupt_msi_int,
+    output wire logic [31:0]              cfg_interrupt_msi_pending_status,
+    output wire logic                     cfg_interrupt_msi_pending_status_data_enable,
+    output wire logic [1:0]               cfg_interrupt_msi_pending_status_function_num,
+    input  wire logic                     cfg_interrupt_msi_sent,
+    input  wire logic                     cfg_interrupt_msi_fail,
+    output wire logic [2:0]               cfg_interrupt_msi_attr,
+    output wire logic                     cfg_interrupt_msi_tph_present,
+    output wire logic [1:0]               cfg_interrupt_msi_tph_type,
+    output wire logic [7:0]               cfg_interrupt_msi_tph_st_tag,
+    output wire logic [7:0]               cfg_interrupt_msi_function_number,
+
+    /*
+     * QSPI flash
+     */
+    output wire logic                     fpga_boot,
+    output wire logic                     qspi_clk,
+    input  wire logic [3:0]               qspi_dq_i,
+    output wire logic [3:0]               qspi_dq_o,
+    output wire logic [3:0]               qspi_dq_oe,
+    output wire logic                     qspi_cs
+);
+
+assign eth_port_i2c_scl_o = '1;
+assign eth_port_i2c_sda_o = '1;
+
+localparam logic PTP_TS_FMT_TOD = 1'b0;
+localparam PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 48;
+
+// flashing via PCIe VSEC
+pyrite_pcie_us_vsec_qspi #(
+    .EXT_CAP_ID(16'h000B),
+    .EXT_CAP_VERSION(4'h1),
+    .EXT_CAP_OFFSET(12'h480),
+    .EXT_CAP_NEXT(12'h000),
+    .EXT_CAP_VSEC_ID(16'h00DB),
+    .EXT_CAP_VSEC_REV(4'h1),
+
+    // FW ID
+    .FPGA_ID(FPGA_ID),
+    .FW_ID(FW_ID),
+    .FW_VER(FW_VER),
+    .BOARD_ID(BOARD_ID),
+    .BOARD_VER(BOARD_VER),
+    .BUILD_DATE(BUILD_DATE),
+    .GIT_HASH(GIT_HASH),
+    .RELEASE_INFO(RELEASE_INFO),
+
+    // Flash
+    .FLASH_SEG_COUNT(1),
+    .FLASH_SEG_DEFAULT(0),
+    .FLASH_SEG_FALLBACK(0),
+    .FLASH_SEG0_SIZE(32'h00000000),
+    .FLASH_DATA_W(4),
+    .FLASH_DUAL_QSPI(1'b0)
+)
+pyrite_inst (
+    .clk(pcie_clk),
+    .rst(pcie_rst),
+
+    /*
+     * PCIe
+     */
+    .cfg_ext_read_received(cfg_ext_read_received),
+    .cfg_ext_write_received(cfg_ext_write_received),
+    .cfg_ext_register_number(cfg_ext_register_number),
+    .cfg_ext_function_number(cfg_ext_function_number),
+    .cfg_ext_write_data(cfg_ext_write_data),
+    .cfg_ext_write_byte_enable(cfg_ext_write_byte_enable),
+    .cfg_ext_read_data(cfg_ext_read_data),
+    .cfg_ext_read_data_valid(cfg_ext_read_data_valid),
+
+    /*
+     * QSPI flash
+     */
+    .fpga_boot(fpga_boot),
+    .qspi_clk(qspi_clk),
+    .qspi_0_dq_i(qspi_dq_i),
+    .qspi_0_dq_o(qspi_dq_o),
+    .qspi_0_dq_oe(qspi_dq_oe),
+    .qspi_0_cs(qspi_cs),
+    .qspi_1_dq_i('0),
+    .qspi_1_dq_o(),
+    .qspi_1_dq_oe(),
+    .qspi_1_cs()
+);
+
+taxi_axis_if #(
+    .DATA_W(32),
+    .KEEP_EN(1),
+    .ID_EN(1),
+    .ID_W(4),
+    .USER_EN(1),
+    .USER_W(1)
+) axis_brd_ctrl_cmd(), axis_brd_ctrl_rsp();
+
+// QSFP28
+assign eth_port_resetl = '1;
+assign eth_port_lpmode = '0;
+
+wire eth_gty_tx_clk[GTY_CNT];
+wire eth_gty_tx_rst[GTY_CNT];
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_tx[GTY_CNT]();
+taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
+
+wire eth_gty_rx_clk[GTY_CNT];
+wire eth_gty_rx_rst[GTY_CNT];
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1+PTP_TS_W)) eth_gty_axis_rx[GTY_CNT]();
+
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[GTY_QUAD_CNT]();
+
+wire eth_gty_rx_status[GTY_CNT];
+
+assign qsfp_led[0][0] = eth_gty_rx_status[0];
+assign qsfp_led[0][1] = eth_gty_rx_status[1];
+assign qsfp_led[0][2] = eth_gty_rx_status[2];
+assign qsfp_led[0][3] = eth_gty_rx_status[3];
+assign qsfp_led[1][0] = eth_gty_rx_status[4];
+assign qsfp_led[1][1] = eth_gty_rx_status[5];
+assign qsfp_led[1][2] = eth_gty_rx_status[6];
+assign qsfp_led[1][3] = eth_gty_rx_status[7];
+
+wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood;
+
+wire eth_gty_mgt_refclk[GTY_CLK_CNT];
+wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
+
+wire eth_gty_rst[GTY_CLK_CNT];
+
+for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gt_clk
+
+    wire eth_gty_mgt_refclk_int;
+
+    if (SIM) begin
+
+        assign eth_gty_mgt_refclk[n] = eth_gty_mgt_refclk_p[n];
+        assign eth_gty_mgt_refclk_int = eth_gty_mgt_refclk_p[n];
+        assign eth_gty_mgt_refclk_bufg[n] = eth_gty_mgt_refclk_int;
+
+    end else begin
+
+        if (FAMILY == "virtexuplus") begin
+
+            IBUFDS_GTE4 ibufds_gte4_eth_gty_mgt_refclk_inst (
+                .I     (eth_gty_mgt_refclk_p[n]),
+                .IB    (eth_gty_mgt_refclk_n[n]),
+                .CEB   (1'b0),
+                .O     (eth_gty_mgt_refclk[n]),
+                .ODIV2 (eth_gty_mgt_refclk_int)
+            );
+
+        end else begin
+
+            IBUFDS_GTE3 ibufds_gte4_eth_gty_mgt_refclk_inst (
+                .I     (eth_gty_mgt_refclk_p[n]),
+                .IB    (eth_gty_mgt_refclk_n[n]),
+                .CEB   (1'b0),
+                .O     (eth_gty_mgt_refclk[n]),
+                .ODIV2 (eth_gty_mgt_refclk_int)
+            );
+
+        end
+
+        BUFG_GT bufg_gt_eth_gty_mgt_refclk_inst (
+            .CE      (&eth_gty_gtpowergood),
+            .CEMASK  (1'b1),
+            .CLR     (1'b0),
+            .CLRMASK (1'b1),
+            .DIV     (3'd0),
+            .I       (eth_gty_mgt_refclk_int),
+            .O       (eth_gty_mgt_refclk_bufg[n])
+        );
+
+    end
+
+    taxi_sync_reset #(
+        .N(4)
+    )
+    qsfp_sync_reset_inst (
+        .clk(eth_gty_mgt_refclk_bufg[n]),
+        .rst(rst_125mhz),
+        .out(eth_gty_rst[n])
+    );
+
+end
+
+wire ptp_clk = eth_gty_mgt_refclk_bufg[0];
+wire ptp_rst = eth_gty_rst[0];
+wire ptp_sample_clk = clk_125mhz;
+wire ptp_td_sd;
+wire ptp_pps;
+wire ptp_pps_str;
+
+assign led[0] = ptp_pps_str;
+assign led_green = ptp_pps_str;
+
+localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP0[4] = '{"QSFP0.1", "QSFP0.2", "QSFP0.3",  "QSFP0.4"};
+localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3",  "QSFP1.4"};
+
+for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
+
+    localparam CLK = n;
+    localparam CNT = 4;
+
+    taxi_apb_if #(
+        .ADDR_W(18),
+        .DATA_W(16)
+    )
+    gt_apb_ctrl();
+
+    taxi_eth_mac_25g_us #(
+        .SIM(SIM),
+        .VENDOR(VENDOR),
+        .FAMILY(FAMILY),
+
+        .CNT(CNT),
+
+        // GT config
+        .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
+
+        // GT type
+        .GT_TYPE("GTY"),
+
+        // GT parameters
+        .GT_TX_POLARITY(n == 0 ? 4'b0101 : 4'b0001),
+        .GT_RX_POLARITY(n == 0 ? 4'b1011 : 4'b0011),
+
+        // MAC/PHY config
+        .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
+        .DATA_W(MAC_DATA_W),
+        .PADDING_EN(1'b1),
+        .DIC_EN(1'b1),
+        .MIN_FRAME_LEN(64),
+        .PTP_TS_EN(PTP_TS_EN),
+        .PTP_TD_EN(PTP_TS_EN),
+        .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+        .PTP_TS_W(PTP_TS_W),
+        .PTP_TD_SDI_PIPELINE(2),
+        .PRBS31_EN(1'b0),
+        .TX_SERDES_PIPELINE(1),
+        .RX_SERDES_PIPELINE(1),
+        .COUNT_125US(125000/6.4),
+        .STAT_EN(0),
+        .STAT_TX_LEVEL(1),
+        .STAT_RX_LEVEL(1),
+        .STAT_ID_BASE(n*CNT*(16+16)),
+        .STAT_UPDATE_PERIOD(1024),
+        .STAT_STR_EN(0),
+        .STAT_PREFIX_STR(n == 0 ? STAT_PREFIX_STR_QSFP0 : STAT_PREFIX_STR_QSFP1)
+    )
+    mac_inst (
+        .xcvr_ctrl_clk(clk_125mhz),
+        .xcvr_ctrl_rst(eth_gty_rst[CLK]),
+
+        /*
+         * Transceiver control
+         */
+        .s_apb_ctrl(gt_apb_ctrl),
+
+        /*
+         * Common
+         */
+        .xcvr_gtpowergood_out(eth_gty_gtpowergood[n]),
+        .xcvr_gtrefclk00_in(eth_gty_mgt_refclk[CLK]),
+        .xcvr_qpll0pd_in(1'b0),
+        .xcvr_qpll0reset_in(1'b0),
+        .xcvr_qpll0pcierate_in(3'd0),
+        .xcvr_qpll0lock_out(),
+        .xcvr_qpll0clk_out(),
+        .xcvr_qpll0refclk_out(),
+        .xcvr_gtrefclk01_in(eth_gty_mgt_refclk[CLK]),
+        .xcvr_qpll1pd_in(1'b0),
+        .xcvr_qpll1reset_in(1'b0),
+        .xcvr_qpll1pcierate_in(3'd0),
+        .xcvr_qpll1lock_out(),
+        .xcvr_qpll1clk_out(),
+        .xcvr_qpll1refclk_out(),
+
+        /*
+         * Serial data
+         */
+        .xcvr_txp(eth_gty_tx_p[n*CNT +: CNT]),
+        .xcvr_txn(eth_gty_tx_n[n*CNT +: CNT]),
+        .xcvr_rxp(eth_gty_rx_p[n*CNT +: CNT]),
+        .xcvr_rxn(eth_gty_rx_n[n*CNT +: CNT]),
+
+        /*
+         * MAC clocks
+         */
+        .rx_clk(eth_gty_rx_clk[n*CNT +: CNT]),
+        .rx_rst_in('{CNT{1'b0}}),
+        .rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]),
+        .tx_clk(eth_gty_tx_clk[n*CNT +: CNT]),
+        .tx_rst_in('{CNT{1'b0}}),
+        .tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]),
+
+        /*
+         * Transmit interface (AXI stream)
+         */
+        .s_axis_tx(eth_gty_axis_tx[n*CNT +: CNT]),
+        .m_axis_tx_cpl(eth_gty_axis_tx_cpl[n*CNT +: CNT]),
+
+        /*
+         * Receive interface (AXI stream)
+         */
+        .m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]),
+
+        /*
+         * PTP clock
+         */
+        .ptp_clk(ptp_clk),
+        .ptp_rst(ptp_rst),
+        .ptp_sample_clk(ptp_sample_clk),
+        .ptp_td_sdi(ptp_td_sd),
+        .tx_ptp_ts_in('{CNT{'0}}),
+        .tx_ptp_ts_out(),
+        .tx_ptp_ts_step_out(),
+        .tx_ptp_locked(),
+        .rx_ptp_ts_in('{CNT{'0}}),
+        .rx_ptp_ts_out(),
+        .rx_ptp_ts_step_out(),
+        .rx_ptp_locked(),
+
+        /*
+         * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
+         */
+        .tx_lfc_req('{CNT{1'b0}}),
+        .tx_lfc_resend('{CNT{1'b0}}),
+        .rx_lfc_en('{CNT{1'b0}}),
+        .rx_lfc_req(),
+        .rx_lfc_ack('{CNT{1'b0}}),
+
+        /*
+         * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
+         */
+        .tx_pfc_req('{CNT{'0}}),
+        .tx_pfc_resend('{CNT{1'b0}}),
+        .rx_pfc_en('{CNT{'0}}),
+        .rx_pfc_req(),
+        .rx_pfc_ack('{CNT{'0}}),
+
+        /*
+         * Pause interface
+         */
+        .tx_lfc_pause_en('{CNT{1'b0}}),
+        .tx_pause_req('{CNT{1'b0}}),
+        .tx_pause_ack(),
+
+        /*
+         * Statistics
+         */
+        .stat_clk(clk_125mhz),
+        .stat_rst(rst_125mhz),
+        .m_axis_stat(axis_eth_stat[n]),
+
+        /*
+         * Status
+         */
+        .tx_start_packet(),
+        .stat_tx_byte(),
+        .stat_tx_pkt_len(),
+        .stat_tx_pkt_ucast(),
+        .stat_tx_pkt_mcast(),
+        .stat_tx_pkt_bcast(),
+        .stat_tx_pkt_vlan(),
+        .stat_tx_pkt_good(),
+        .stat_tx_pkt_bad(),
+        .stat_tx_err_oversize(),
+        .stat_tx_err_user(),
+        .stat_tx_err_underflow(),
+        .rx_start_packet(),
+        .rx_error_count(),
+        .rx_block_lock(),
+        .rx_high_ber(),
+        .rx_status(eth_gty_rx_status[n*CNT +: CNT]),
+        .stat_rx_byte(),
+        .stat_rx_pkt_len(),
+        .stat_rx_pkt_fragment(),
+        .stat_rx_pkt_jabber(),
+        .stat_rx_pkt_ucast(),
+        .stat_rx_pkt_mcast(),
+        .stat_rx_pkt_bcast(),
+        .stat_rx_pkt_vlan(),
+        .stat_rx_pkt_good(),
+        .stat_rx_pkt_bad(),
+        .stat_rx_err_oversize(),
+        .stat_rx_err_bad_fcs(),
+        .stat_rx_err_bad_block(),
+        .stat_rx_err_framing(),
+        .stat_rx_err_preamble(),
+        .stat_rx_fifo_drop('{CNT{1'b0}}),
+        .stat_tx_mcf(),
+        .stat_rx_mcf(),
+        .stat_tx_lfc_pkt(),
+        .stat_tx_lfc_xon(),
+        .stat_tx_lfc_xoff(),
+        .stat_tx_lfc_paused(),
+        .stat_tx_pfc_pkt(),
+        .stat_tx_pfc_xon(),
+        .stat_tx_pfc_xoff(),
+        .stat_tx_pfc_paused(),
+        .stat_rx_lfc_pkt(),
+        .stat_rx_lfc_xon(),
+        .stat_rx_lfc_xoff(),
+        .stat_rx_lfc_paused(),
+        .stat_rx_pfc_pkt(),
+        .stat_rx_pfc_xon(),
+        .stat_rx_pfc_xoff(),
+        .stat_rx_pfc_paused(),
+
+        /*
+         * Configuration
+         */
+        .cfg_tx_max_pkt_len('{CNT{16'd9218}}),
+        .cfg_tx_ifg('{CNT{8'd12}}),
+        .cfg_tx_enable('{CNT{1'b1}}),
+        .cfg_rx_max_pkt_len('{CNT{16'd9218}}),
+        .cfg_rx_enable('{CNT{1'b1}}),
+        .cfg_tx_prbs31_enable('{CNT{1'b0}}),
+        .cfg_rx_prbs31_enable('{CNT{1'b0}}),
+        .cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
+        .cfg_mcf_rx_check_eth_dst_mcast('{CNT{1'b1}}),
+        .cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
+        .cfg_mcf_rx_check_eth_dst_ucast('{CNT{1'b0}}),
+        .cfg_mcf_rx_eth_src('{CNT{48'd0}}),
+        .cfg_mcf_rx_check_eth_src('{CNT{1'b0}}),
+        .cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
+        .cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
+        .cfg_mcf_rx_check_opcode_lfc('{CNT{1'b1}}),
+        .cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
+        .cfg_mcf_rx_check_opcode_pfc('{CNT{1'b1}}),
+        .cfg_mcf_rx_forward('{CNT{1'b0}}),
+        .cfg_mcf_rx_enable('{CNT{1'b0}}),
+        .cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
+        .cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
+        .cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
+        .cfg_tx_lfc_opcode('{CNT{16'h0001}}),
+        .cfg_tx_lfc_en('{CNT{1'b0}}),
+        .cfg_tx_lfc_quanta('{CNT{16'hffff}}),
+        .cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
+        .cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
+        .cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
+        .cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
+        .cfg_tx_pfc_opcode('{CNT{16'h0101}}),
+        .cfg_tx_pfc_en('{CNT{1'b0}}),
+        .cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
+        .cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
+        .cfg_rx_lfc_opcode('{CNT{16'h0001}}),
+        .cfg_rx_lfc_en('{CNT{1'b0}}),
+        .cfg_rx_pfc_opcode('{CNT{16'h0101}}),
+        .cfg_rx_pfc_en('{CNT{1'b0}})
+    );
+
+end
+
+cndm_micro_pcie_us #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+
+    // FW ID
+    .FPGA_ID(FPGA_ID),
+    .FW_ID(FW_ID),
+    .FW_VER(FW_VER),
+    .BOARD_ID(BOARD_ID),
+    .BOARD_VER(BOARD_VER),
+    .BUILD_DATE(BUILD_DATE),
+    .GIT_HASH(GIT_HASH),
+    .RELEASE_INFO(RELEASE_INFO),
+
+    // Structural configuration
+    .PORTS($size(eth_gty_axis_tx)),
+    .BRD_CTRL_EN(1'b0),
+    .SYS_CLK_PER_NS_NUM(4),
+    .SYS_CLK_PER_NS_DEN(1),
+
+    // PTP configuration
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_FMT_TOD(1'b0),
+    .PTP_CLK_PER_NS_NUM(PTP_CLK_PER_NS_NUM),
+    .PTP_CLK_PER_NS_DEN(PTP_CLK_PER_NS_DEN),
+
+    // PCIe interface configuration
+    .RQ_SEQ_NUM_W(RQ_SEQ_NUM_W),
+
+    // AXI lite interface configuration (control)
+    .AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W),
+    .AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W)
+)
+cndm_inst (
+    /*
+     * PCIe
+     */
+    .pcie_clk(pcie_clk),
+    .pcie_rst(pcie_rst),
+    .s_axis_pcie_cq(s_axis_pcie_cq),
+    .m_axis_pcie_cc(m_axis_pcie_cc),
+    .m_axis_pcie_rq(m_axis_pcie_rq),
+    .s_axis_pcie_rc(s_axis_pcie_rc),
+
+    .pcie_rq_seq_num0(pcie_rq_seq_num0),
+    .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0),
+    .pcie_rq_seq_num1(pcie_rq_seq_num1),
+    .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1),
+
+    .cfg_max_payload(cfg_max_payload),
+    .cfg_max_read_req(cfg_max_read_req),
+    .cfg_rcb_status(cfg_rcb_status),
+
+    .cfg_mgmt_addr(cfg_mgmt_addr),
+    .cfg_mgmt_function_number(cfg_mgmt_function_number),
+    .cfg_mgmt_write(cfg_mgmt_write),
+    .cfg_mgmt_write_data(cfg_mgmt_write_data),
+    .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+    .cfg_mgmt_read(cfg_mgmt_read),
+    .cfg_mgmt_read_data(cfg_mgmt_read_data),
+    .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
+
+    .cfg_fc_ph(cfg_fc_ph),
+    .cfg_fc_pd(cfg_fc_pd),
+    .cfg_fc_nph(cfg_fc_nph),
+    .cfg_fc_npd(cfg_fc_npd),
+    .cfg_fc_cplh(cfg_fc_cplh),
+    .cfg_fc_cpld(cfg_fc_cpld),
+    .cfg_fc_sel(cfg_fc_sel),
+
+    .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+    .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+    .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+    .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+    .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+    .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+    .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+    .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+    .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+    .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+    .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+    .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+    .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+    .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+    .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+    .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
+
+    /*
+     * Board control
+     */
+    .m_axis_brd_ctrl_cmd(axis_brd_ctrl_cmd),
+    .s_axis_brd_ctrl_rsp(axis_brd_ctrl_rsp),
+
+    /*
+     * PTP
+     */
+    .ptp_clk(ptp_clk),
+    .ptp_rst(ptp_rst),
+    .ptp_sample_clk(ptp_sample_clk),
+    .ptp_td_sdo(ptp_td_sd),
+    .ptp_pps(ptp_pps),
+    .ptp_pps_str(ptp_pps_str),
+    .ptp_sync_locked(),
+    .ptp_sync_ts_rel(),
+    .ptp_sync_ts_rel_step(),
+    .ptp_sync_ts_tod(),
+    .ptp_sync_ts_tod_step(),
+    .ptp_sync_pps(),
+    .ptp_sync_pps_str(),
+
+    /*
+     * Ethernet
+     */
+    .mac_tx_clk(eth_gty_tx_clk),
+    .mac_tx_rst(eth_gty_tx_rst),
+    .mac_axis_tx(eth_gty_axis_tx),
+    .mac_axis_tx_cpl(eth_gty_axis_tx_cpl),
+
+    .mac_rx_clk(eth_gty_rx_clk),
+    .mac_rx_rst(eth_gty_rx_rst),
+    .mac_axis_rx(eth_gty_axis_rx)
+);
+
+endmodule
+
+`resetall

src/cndm/board/NT200A02/fpga/tb/fpga_core/Makefile

@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2020-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = fpga_core
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vsec_qspi.f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_SIM := "1'b1"
+export PARAM_VENDOR := "\"XILINX\""
+export PARAM_FAMILY := "\"virtexuplus\""
+
+# Board configuration
+export PARAM_PORT_CNT := 2
+export PARAM_GTY_QUAD_CNT := $(PARAM_PORT_CNT)
+export PARAM_GTY_CNT := $(shell echo $$(( 4 * $(PARAM_GTY_QUAD_CNT) )))
+export PARAM_GTY_CLK_CNT := $(PARAM_GTY_QUAD_CNT)
+
+# PTP configuration
+export PARAM_PTP_TS_EN := 1
+
+# AXI lite interface configuration (control)
+export PARAM_AXIL_CTRL_DATA_W := 32
+export PARAM_AXIL_CTRL_ADDR_W := 24
+
+# MAC configuration
+export PARAM_CFG_LOW_LATENCY := 1
+export PARAM_COMBINED_MAC_PCS := 1
+export PARAM_MAC_DATA_W := "64"
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/cndm/board/NT200A02/fpga/tb/fpga_core/baser.py

@@ -0,0 +1 @@
+../../lib/taxi/src/eth/tb/baser.py

src/cndm/board/NT200A02/fpga/tb/fpga_core/cndm.py

@@ -0,0 +1 @@
+../../lib/taxi/src/cndm/tb/cndm.py

src/cndm/board/NT200A02/fpga/tb/fpga_core/test_fpga_core.py

@@ -0,0 +1,523 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: MIT
+"""
+
+Copyright (c) 2020-2026 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import sys
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, FallingEdge, Timer
+
+from cocotbext.axi import AxiStreamBus
+from cocotbext.eth import XgmiiFrame
+from cocotbext.pcie.core import RootComplex
+from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
+
+try:
+    from baser import BaseRSerdesSource, BaseRSerdesSink
+    import cndm
+except ImportError:
+    # attempt import from current directory
+    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
+    try:
+        from baser import BaseRSerdesSource, BaseRSerdesSink
+        import cndm
+    finally:
+        del sys.path[0]
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        # Clocks
+        cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
+
+        # PCIe
+        self.rc = RootComplex()
+
+        self.rc.max_payload_size = 0x1  # 256 bytes
+        self.rc.max_read_request_size = 0x2  # 512 bytes
+
+        self.dev = UltraScalePlusPcieDevice(
+            # configuration options
+            pcie_generation=3,
+            pcie_link_width=16,
+            user_clk_frequency=250e6,
+            alignment="dword",
+            cq_straddle=False,
+            cc_straddle=False,
+            rq_straddle=False,
+            rc_straddle=False,
+            rc_4tlp_straddle=False,
+            pf_count=1,
+            max_payload_size=1024,
+            enable_client_tag=True,
+            enable_extended_tag=True,
+            enable_parity=False,
+            enable_rx_msg_interface=False,
+            enable_sriov=False,
+            enable_extended_configuration=False,
+
+            pf0_msi_enable=True,
+            pf0_msi_count=32,
+            pf1_msi_enable=False,
+            pf1_msi_count=1,
+            pf2_msi_enable=False,
+            pf2_msi_count=1,
+            pf3_msi_enable=False,
+            pf3_msi_count=1,
+            pf0_msix_enable=False,
+            pf0_msix_table_size=31,
+            pf0_msix_table_bir=4,
+            pf0_msix_table_offset=0x00000000,
+            pf0_msix_pba_bir=4,
+            pf0_msix_pba_offset=0x00008000,
+            pf1_msix_enable=False,
+            pf1_msix_table_size=0,
+            pf1_msix_table_bir=0,
+            pf1_msix_table_offset=0x00000000,
+            pf1_msix_pba_bir=0,
+            pf1_msix_pba_offset=0x00000000,
+            pf2_msix_enable=False,
+            pf2_msix_table_size=0,
+            pf2_msix_table_bir=0,
+            pf2_msix_table_offset=0x00000000,
+            pf2_msix_pba_bir=0,
+            pf2_msix_pba_offset=0x00000000,
+            pf3_msix_enable=False,
+            pf3_msix_table_size=0,
+            pf3_msix_table_bir=0,
+            pf3_msix_table_offset=0x00000000,
+            pf3_msix_pba_bir=0,
+            pf3_msix_pba_offset=0x00000000,
+
+            # signals
+            # Clock and Reset Interface
+            user_clk=dut.pcie_clk,
+            user_reset=dut.pcie_rst,
+            # user_lnk_up
+            # sys_clk
+            # sys_clk_gt
+            # sys_reset
+            # phy_rdy_out
+
+            # Requester reQuest Interface
+            rq_bus=AxiStreamBus.from_entity(dut.m_axis_pcie_rq),
+            pcie_rq_seq_num0=dut.pcie_rq_seq_num0,
+            pcie_rq_seq_num_vld0=dut.pcie_rq_seq_num_vld0,
+            pcie_rq_seq_num1=dut.pcie_rq_seq_num1,
+            pcie_rq_seq_num_vld1=dut.pcie_rq_seq_num_vld1,
+            # pcie_rq_tag0
+            # pcie_rq_tag1
+            # pcie_rq_tag_av
+            # pcie_rq_tag_vld0
+            # pcie_rq_tag_vld1
+
+            # Requester Completion Interface
+            rc_bus=AxiStreamBus.from_entity(dut.s_axis_pcie_rc),
+
+            # Completer reQuest Interface
+            cq_bus=AxiStreamBus.from_entity(dut.s_axis_pcie_cq),
+            # pcie_cq_np_req
+            # pcie_cq_np_req_count
+
+            # Completer Completion Interface
+            cc_bus=AxiStreamBus.from_entity(dut.m_axis_pcie_cc),
+
+            # Transmit Flow Control Interface
+            # pcie_tfc_nph_av=dut.pcie_tfc_nph_av,
+            # pcie_tfc_npd_av=dut.pcie_tfc_npd_av,
+
+            # Configuration Management Interface
+            cfg_mgmt_addr=dut.cfg_mgmt_addr,
+            cfg_mgmt_function_number=dut.cfg_mgmt_function_number,
+            cfg_mgmt_write=dut.cfg_mgmt_write,
+            cfg_mgmt_write_data=dut.cfg_mgmt_write_data,
+            cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable,
+            cfg_mgmt_read=dut.cfg_mgmt_read,
+            cfg_mgmt_read_data=dut.cfg_mgmt_read_data,
+            cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done,
+            # cfg_mgmt_debug_access
+
+            # Configuration Status Interface
+            # cfg_phy_link_down
+            # cfg_phy_link_status
+            # cfg_negotiated_width
+            # cfg_current_speed
+            cfg_max_payload=dut.cfg_max_payload,
+            cfg_max_read_req=dut.cfg_max_read_req,
+            # cfg_function_status
+            # cfg_vf_status
+            # cfg_function_power_state
+            # cfg_vf_power_state
+            # cfg_link_power_state
+            # cfg_err_cor_out
+            # cfg_err_nonfatal_out
+            # cfg_err_fatal_out
+            # cfg_local_error_out
+            # cfg_local_error_valid
+            # cfg_rx_pm_state
+            # cfg_tx_pm_state
+            # cfg_ltssm_state
+            cfg_rcb_status=dut.cfg_rcb_status,
+            # cfg_obff_enable
+            # cfg_pl_status_change
+            # cfg_tph_requester_enable
+            # cfg_tph_st_mode
+            # cfg_vf_tph_requester_enable
+            # cfg_vf_tph_st_mode
+
+            # Configuration Received Message Interface
+            # cfg_msg_received
+            # cfg_msg_received_data
+            # cfg_msg_received_type
+
+            # Configuration Transmit Message Interface
+            # cfg_msg_transmit
+            # cfg_msg_transmit_type
+            # cfg_msg_transmit_data
+            # cfg_msg_transmit_done
+
+            # Configuration Flow Control Interface
+            cfg_fc_ph=dut.cfg_fc_ph,
+            cfg_fc_pd=dut.cfg_fc_pd,
+            cfg_fc_nph=dut.cfg_fc_nph,
+            cfg_fc_npd=dut.cfg_fc_npd,
+            cfg_fc_cplh=dut.cfg_fc_cplh,
+            cfg_fc_cpld=dut.cfg_fc_cpld,
+            cfg_fc_sel=dut.cfg_fc_sel,
+
+            # Configuration Control Interface
+            # cfg_hot_reset_in
+            # cfg_hot_reset_out
+            # cfg_config_space_enable
+            # cfg_dsn
+            # cfg_bus_number
+            # cfg_ds_port_number
+            # cfg_ds_bus_number
+            # cfg_ds_device_number
+            # cfg_ds_function_number
+            # cfg_power_state_change_ack
+            # cfg_power_state_change_interrupt
+            # cfg_err_cor_in=dut.status_error_cor,
+            # cfg_err_uncor_in=dut.status_error_uncor,
+            # cfg_flr_in_process
+            # cfg_flr_done
+            # cfg_vf_flr_in_process
+            # cfg_vf_flr_func_num
+            # cfg_vf_flr_done
+            # cfg_pm_aspm_l1_entry_reject
+            # cfg_pm_aspm_tx_l0s_entry_disable
+            # cfg_req_pm_transition_l23_ready
+            # cfg_link_training_enable
+
+            # Configuration Interrupt Controller Interface
+            # cfg_interrupt_int
+            # cfg_interrupt_sent
+            # cfg_interrupt_pending
+            cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
+            cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
+            cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
+            cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
+            cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
+            cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
+            cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
+            cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
+            cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
+            cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
+            cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
+            # cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
+            # cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
+            # cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
+            # cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
+            # cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
+            # cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
+            # cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
+            # cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
+            # cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
+            # cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
+            # cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
+            cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
+            cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
+            cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
+            cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
+            cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
+
+            # Configuration Extend Interface
+            # cfg_ext_read_received
+            # cfg_ext_write_received
+            # cfg_ext_register_number
+            # cfg_ext_function_number
+            # cfg_ext_write_data
+            # cfg_ext_write_byte_enable
+            # cfg_ext_read_data
+            # cfg_ext_read_data_valid
+        )
+
+        # self.dev.log.setLevel(logging.DEBUG)
+
+        self.rc.make_port().connect(self.dev)
+
+        self.dev.functions[0].configure_bar(0, 2**int(dut.uut.cndm_inst.axil_ctrl_bar.ADDR_W))
+
+        # Ethernet
+        self.qsfp_sources = []
+        self.qsfp_sinks = []
+
+        for clk in dut.eth_gty_mgt_refclk_p:
+            cocotb.start_soon(Clock(clk, 3.102, units="ns").start())
+
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.uut.gt_quad]):
+            gt_inst = ch.ch_inst.gt.gt_inst
+
+            if ch.ch_inst.DATA_W.value == 64:
+                if ch.ch_inst.CFG_LOW_LATENCY.value:
+                    clk = 2.482
+                    gbx_cfg = (66, [64, 65])
+                else:
+                    clk = 2.56
+                    gbx_cfg = None
+            else:
+                if ch.ch_inst.CFG_LOW_LATENCY.value:
+                    clk = 3.102
+                    gbx_cfg = (66, [64, 65])
+                else:
+                    clk = 3.2
+                    gbx_cfg = None
+
+            cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())
+            cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start())
+
+            self.qsfp_sources.append(BaseRSerdesSource(
+                data=gt_inst.serdes_rx_data,
+                data_valid=gt_inst.serdes_rx_data_valid,
+                hdr=gt_inst.serdes_rx_hdr,
+                hdr_valid=gt_inst.serdes_rx_hdr_valid,
+                clock=gt_inst.rx_clk,
+                slip=gt_inst.serdes_rx_bitslip,
+                reverse=True,
+                gbx_cfg=gbx_cfg
+            ))
+            self.qsfp_sinks.append(BaseRSerdesSink(
+                data=gt_inst.serdes_tx_data,
+                data_valid=gt_inst.serdes_tx_data_valid,
+                hdr=gt_inst.serdes_tx_hdr,
+                hdr_valid=gt_inst.serdes_tx_hdr_valid,
+                gbx_sync=gt_inst.serdes_tx_gbx_sync,
+                clock=gt_inst.tx_clk,
+                reverse=True,
+                gbx_cfg=gbx_cfg
+            ))
+
+        self.loopback_enable = False
+        cocotb.start_soon(self._run_loopback())
+
+    async def init(self):
+
+        self.dut.rst_125mhz.setimmediatevalue(0)
+
+        await FallingEdge(self.dut.pcie_rst)
+        await Timer(100, 'ns')
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk_125mhz)
+
+        self.dut.rst_125mhz.value = 1
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk_125mhz)
+
+        self.dut.rst_125mhz.value = 0
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk_125mhz)
+
+        await self.rc.enumerate()
+
+    async def _run_loopback(self):
+        while True:
+            await RisingEdge(self.dut.pcie_clk)
+
+            if self.loopback_enable:
+                for src, snk in zip(self.qsfp_sources, self.qsfp_sinks):
+                    while not snk.empty():
+                        await src.send(await snk.recv())
+
+@cocotb.test()
+async def run_test(dut):
+
+    tb = TB(dut)
+
+    await tb.init()
+
+    tb.log.info("Init driver model")
+    driver = cndm.Driver()
+    await driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
+
+    tb.log.info("Init complete")
+
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk_125mhz)
+
+    for snk in tb.qsfp_sinks:
+        snk.clear()
+
+    tb.log.info("Send and receive single packet on each port")
+
+    for k in range(len(driver.ports)):
+        data = f"Corundum rocks on port {k}!".encode('ascii')
+
+        await driver.ports[k].start_xmit(data)
+
+        pkt = await tb.qsfp_sinks[k].recv()
+        tb.log.info("Got TX packet: %s", pkt)
+
+        assert pkt.get_payload() == data.ljust(60, b'\x00')
+        assert pkt.check_fcs()
+
+        await tb.qsfp_sources[k].send(pkt)
+
+        pkt = await driver.ports[k].recv()
+        tb.log.info("Got RX packet: %s", pkt)
+
+        assert bytes(pkt) == data.ljust(60, b'\x00')
+
+    tb.log.info("Multiple small packets")
+
+    count = 64
+    pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
+
+    tb.loopback_enable = True
+
+    for p in pkts:
+        await driver.ports[0].start_xmit(p)
+
+    for k in range(count):
+        pkt = await driver.ports[0].recv()
+
+        tb.log.info("Got RX packet: %s", pkt)
+
+        assert bytes(pkt) == pkts[k].ljust(60, b'\x00')
+
+    tb.loopback_enable = False
+
+    tb.log.info("Multiple large packets")
+
+    count = 64
+    pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
+
+    tb.loopback_enable = True
+
+    for p in pkts:
+        await driver.ports[0].start_xmit(p)
+
+    for k in range(count):
+        pkt = await driver.ports[0].recv()
+
+        tb.log.info("Got RX packet: %s", pkt)
+
+        assert bytes(pkt) == pkts[k].ljust(60, b'\x00')
+
+    tb.loopback_enable = False
+
+    await RisingEdge(dut.clk_125mhz)
+    await RisingEdge(dut.clk_125mhz)
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("mac_data_w", [32, 64])
+def test_fpga_core(request, mac_data_w):
+    dut = "fpga_core"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "cndm", "rtl", "cndm_micro_pcie_us.f"),
+        os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"),
+        os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"),
+        os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
+        os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),
+        os.path.join(taxi_src_dir, "pyrite", "rtl", "pyrite_pcie_us_vsec_qspi.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['SIM'] = "1'b1"
+    parameters['VENDOR'] = "\"XILINX\""
+    parameters['FAMILY'] = "\"virtexuplus\""
+
+    # Board configuration
+    parameters['PORT_CNT'] = 2
+    parameters['GTY_QUAD_CNT'] = parameters['PORT_CNT']
+    parameters['GTY_CNT'] = parameters['GTY_QUAD_CNT']*4
+    parameters['GTY_CLK_CNT'] = parameters['GTY_QUAD_CNT']
+
+    # PTP configuration
+    parameters['PTP_TS_EN'] = 1
+
+    # AXI lite interface configuration (control)
+    parameters['AXIL_CTRL_DATA_W'] = 32
+    parameters['AXIL_CTRL_ADDR_W'] = 24
+
+    # MAC configuration
+    parameters['CFG_LOW_LATENCY'] = 1
+    parameters['COMBINED_MAC_PCS'] = 1
+    parameters['MAC_DATA_W'] = mac_data_w
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/cndm/board/NT200A02/fpga/tb/fpga_core/test_fpga_core.sv

@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2026 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA core logic testbench
+ */
+module test_fpga_core #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter logic SIM = 1'b0,
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtexuplus",
+
+    // Board configuration
+    parameter PORT_CNT = 2,
+    parameter GTY_QUAD_CNT = PORT_CNT,
+    parameter GTY_CNT = GTY_QUAD_CNT*4,
+    parameter GTY_CLK_CNT = GTY_QUAD_CNT,
+
+    // FW ID
+    parameter FPGA_ID = 32'h4B2B093,
+    parameter FW_ID = 32'h0000C001,
+    parameter FW_VER = 32'h000_01_000,
+    parameter BOARD_ID = 32'h18f4_01c5,
+    parameter BOARD_VER = 32'h001_00_000,
+    parameter BUILD_DATE = 32'd602976000,
+    parameter GIT_HASH = 32'h5f87c2e8,
+    parameter RELEASE_INFO = 32'h00000000,
+
+    // PTP configuration
+    parameter logic PTP_TS_EN = 1'b1,
+    parameter PTP_CLK_PER_NS_NUM = 512,
+    parameter PTP_CLK_PER_NS_DEN = 165,
+
+    // PCIe interface configuration
+    parameter AXIS_PCIE_DATA_W = 512,
+    parameter AXIS_PCIE_RC_USER_W = AXIS_PCIE_DATA_W < 512 ? 75 : 161,
+    parameter AXIS_PCIE_RQ_USER_W = AXIS_PCIE_DATA_W < 512 ? 62 : 137,
+    parameter AXIS_PCIE_CQ_USER_W = AXIS_PCIE_DATA_W < 512 ? 85 : 183,
+    parameter AXIS_PCIE_CC_USER_W = AXIS_PCIE_DATA_W < 512 ? 33 : 81,
+
+    // AXI lite interface configuration (control)
+    parameter AXIL_CTRL_DATA_W = 32,
+    parameter AXIL_CTRL_ADDR_W = 24,
+
+    // MAC configuration
+    parameter logic CFG_LOW_LATENCY = 1'b1,
+    parameter logic COMBINED_MAC_PCS = 1'b1,
+    parameter MAC_DATA_W = 64
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam AXIS_PCIE_KEEP_W = (AXIS_PCIE_DATA_W/32);
+localparam RQ_SEQ_NUM_W = AXIS_PCIE_RQ_USER_W == 60 ? 4 : 6;
+
+logic clk_125mhz;
+logic rst_125mhz;
+
+logic [3:0]  led;
+logic [3:0]  qsfp_led[PORT_CNT];
+logic        led_red;
+logic        led_green;
+logic [1:0]  led_sync;
+logic        eth_led_yellow;
+logic        eth_led_green;
+
+logic eth_gty_mgt_refclk_p[GTY_CLK_CNT];
+logic eth_gty_mgt_refclk_n[GTY_CLK_CNT];
+logic eth_gty_mgt_refclk_out[GTY_CLK_CNT];
+
+logic [PORT_CNT-1:0] eth_port_resetl;
+logic [PORT_CNT-1:0] eth_port_modprsl;
+logic [PORT_CNT-1:0] eth_port_intl;
+logic [PORT_CNT-1:0] eth_port_lpmode;
+
+
+logic [PORT_CNT-1:0]  eth_port_i2c_scl_i;
+logic [PORT_CNT-1:0]  eth_port_i2c_scl_o;
+logic [PORT_CNT-1:0]  eth_port_i2c_sda_i;
+logic [PORT_CNT-1:0]  eth_port_i2c_sda_o;
+
+logic pcie_clk;
+logic pcie_rst;
+
+taxi_axis_if #(
+    .DATA_W(AXIS_PCIE_DATA_W),
+    .KEEP_EN(1),
+    .KEEP_W(AXIS_PCIE_KEEP_W),
+    .USER_EN(1),
+    .USER_W(AXIS_PCIE_CQ_USER_W)
+) s_axis_pcie_cq();
+
+taxi_axis_if #(
+    .DATA_W(AXIS_PCIE_DATA_W),
+    .KEEP_EN(1),
+    .KEEP_W(AXIS_PCIE_KEEP_W),
+    .USER_EN(1),
+    .USER_W(AXIS_PCIE_CC_USER_W)
+) m_axis_pcie_cc();
+
+taxi_axis_if #(
+    .DATA_W(AXIS_PCIE_DATA_W),
+    .KEEP_EN(1),
+    .KEEP_W(AXIS_PCIE_KEEP_W),
+    .USER_EN(1),
+    .USER_W(AXIS_PCIE_RQ_USER_W)
+) m_axis_pcie_rq();
+
+taxi_axis_if #(
+    .DATA_W(AXIS_PCIE_DATA_W),
+    .KEEP_EN(1),
+    .KEEP_W(AXIS_PCIE_KEEP_W),
+    .USER_EN(1),
+    .USER_W(AXIS_PCIE_RC_USER_W)
+) s_axis_pcie_rc();
+
+logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num0;
+logic pcie_rq_seq_num_vld0;
+logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num1;
+logic pcie_rq_seq_num_vld1;
+
+logic [2:0] cfg_max_payload;
+logic [2:0] cfg_max_read_req;
+logic [3:0] cfg_rcb_status;
+
+logic [9:0]  cfg_mgmt_addr;
+logic [7:0]  cfg_mgmt_function_number;
+logic        cfg_mgmt_write;
+logic [31:0] cfg_mgmt_write_data;
+logic [3:0]  cfg_mgmt_byte_enable;
+logic        cfg_mgmt_read;
+logic [31:0] cfg_mgmt_read_data;
+logic        cfg_mgmt_read_write_done;
+
+logic [7:0]  cfg_fc_ph;
+logic [11:0] cfg_fc_pd;
+logic [7:0]  cfg_fc_nph;
+logic [11:0] cfg_fc_npd;
+logic [7:0]  cfg_fc_cplh;
+logic [11:0] cfg_fc_cpld;
+logic [2:0]  cfg_fc_sel;
+
+logic        cfg_ext_read_received;
+logic        cfg_ext_write_received;
+logic [9:0]  cfg_ext_register_number;
+logic [7:0]  cfg_ext_function_number;
+logic [31:0] cfg_ext_write_data;
+logic [3:0]  cfg_ext_write_byte_enable;
+logic [31:0] cfg_ext_read_data;
+logic        cfg_ext_read_data_valid;
+
+logic [3:0]   cfg_interrupt_msi_enable;
+logic [11:0]  cfg_interrupt_msi_mmenable;
+logic         cfg_interrupt_msi_mask_update;
+logic [31:0]  cfg_interrupt_msi_data;
+logic [1:0]   cfg_interrupt_msi_select;
+logic [31:0]  cfg_interrupt_msi_int;
+logic [31:0]  cfg_interrupt_msi_pending_status;
+logic         cfg_interrupt_msi_pending_status_data_enable;
+logic [1:0]   cfg_interrupt_msi_pending_status_function_num;
+logic         cfg_interrupt_msi_sent;
+logic         cfg_interrupt_msi_fail;
+logic [2:0]   cfg_interrupt_msi_attr;
+logic         cfg_interrupt_msi_tph_present;
+logic [1:0]   cfg_interrupt_msi_tph_type;
+logic [7:0]   cfg_interrupt_msi_tph_st_tag;
+logic [7:0]   cfg_interrupt_msi_function_number;
+
+logic        fpga_boot;
+logic        qspi_clk;
+logic [3:0]  qspi_dq_i;
+logic [3:0]  qspi_dq_o;
+logic [3:0]  qspi_dq_oe;
+logic        qspi_cs;
+
+fpga_core #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+
+    // Board configuration
+    .PORT_CNT(PORT_CNT),
+    .GTY_QUAD_CNT(GTY_QUAD_CNT),
+    .GTY_CNT(GTY_CNT),
+    .GTY_CLK_CNT(GTY_CLK_CNT),
+
+    // FW ID
+    .FPGA_ID(FPGA_ID),
+    .FW_ID(FW_ID),
+    .FW_VER(FW_VER),
+    .BOARD_ID(BOARD_ID),
+    .BOARD_VER(BOARD_VER),
+    .BUILD_DATE(BUILD_DATE),
+    .GIT_HASH(GIT_HASH),
+    .RELEASE_INFO(RELEASE_INFO),
+
+    // PTP configuration
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_CLK_PER_NS_NUM(PTP_CLK_PER_NS_NUM),
+    .PTP_CLK_PER_NS_DEN(PTP_CLK_PER_NS_DEN),
+
+    // PCIe interface configuration
+    .RQ_SEQ_NUM_W(RQ_SEQ_NUM_W),
+
+    // AXI lite interface configuration (control)
+    .AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W),
+    .AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W),
+
+    // MAC configuration
+    .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
+    .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
+    .MAC_DATA_W(MAC_DATA_W)
+)
+uut (
+    /*
+     * Clock: 125MHz
+     * Synchronous reset
+     */
+    .clk_125mhz(clk_125mhz),
+    .rst_125mhz(rst_125mhz),
+
+    /*
+     * GPIO
+     */
+    .led(led),
+    .qsfp_led(qsfp_led),
+    .led_red(led_red),
+    .led_green(led_green),
+    .led_sync(led_sync),
+    .eth_led_yellow(eth_led_yellow),
+    .eth_led_green(eth_led_green),
+
+    /*
+     * Ethernet: QSFP28
+     */
+    .eth_gty_tx_p(),
+    .eth_gty_tx_n(),
+    .eth_gty_rx_p('{GTY_CNT{1'b0}}),
+    .eth_gty_rx_n('{GTY_CNT{1'b0}}),
+    .eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
+    .eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
+    .eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
+
+    .eth_port_resetl(eth_port_resetl),
+    .eth_port_modprsl(eth_port_modprsl),
+    .eth_port_intl(eth_port_intl),
+    .eth_port_lpmode(eth_port_lpmode),
+
+    .eth_port_i2c_scl_i(eth_port_i2c_scl_i),
+    .eth_port_i2c_scl_o(eth_port_i2c_scl_o),
+    .eth_port_i2c_sda_i(eth_port_i2c_sda_i),
+    .eth_port_i2c_sda_o(eth_port_i2c_sda_o),
+
+    /*
+     * PCIe
+     */
+    .pcie_clk(pcie_clk),
+    .pcie_rst(pcie_rst),
+    .s_axis_pcie_cq(s_axis_pcie_cq),
+    .m_axis_pcie_cc(m_axis_pcie_cc),
+    .m_axis_pcie_rq(m_axis_pcie_rq),
+    .s_axis_pcie_rc(s_axis_pcie_rc),
+
+    .pcie_rq_seq_num0(pcie_rq_seq_num0),
+    .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0),
+    .pcie_rq_seq_num1(pcie_rq_seq_num1),
+    .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1),
+
+    .cfg_max_payload(cfg_max_payload),
+    .cfg_max_read_req(cfg_max_read_req),
+    .cfg_rcb_status(cfg_rcb_status),
+
+    .cfg_mgmt_addr(cfg_mgmt_addr),
+    .cfg_mgmt_function_number(cfg_mgmt_function_number),
+    .cfg_mgmt_write(cfg_mgmt_write),
+    .cfg_mgmt_write_data(cfg_mgmt_write_data),
+    .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+    .cfg_mgmt_read(cfg_mgmt_read),
+    .cfg_mgmt_read_data(cfg_mgmt_read_data),
+    .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
+
+    .cfg_fc_ph(cfg_fc_ph),
+    .cfg_fc_pd(cfg_fc_pd),
+    .cfg_fc_nph(cfg_fc_nph),
+    .cfg_fc_npd(cfg_fc_npd),
+    .cfg_fc_cplh(cfg_fc_cplh),
+    .cfg_fc_cpld(cfg_fc_cpld),
+    .cfg_fc_sel(cfg_fc_sel),
+
+    .cfg_ext_read_received(cfg_ext_read_received),
+    .cfg_ext_write_received(cfg_ext_write_received),
+    .cfg_ext_register_number(cfg_ext_register_number),
+    .cfg_ext_function_number(cfg_ext_function_number),
+    .cfg_ext_write_data(cfg_ext_write_data),
+    .cfg_ext_write_byte_enable(cfg_ext_write_byte_enable),
+    .cfg_ext_read_data(cfg_ext_read_data),
+    .cfg_ext_read_data_valid(cfg_ext_read_data_valid),
+
+    .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+    .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+    .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+    .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+    .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+    .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+    .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+    .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+    .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+    .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+    .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+    .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+    .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+    .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+    .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+    .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
+
+    /*
+     * QSPI flash
+     */
+    .fpga_boot(fpga_boot),
+    .qspi_clk(qspi_clk),
+    .qspi_dq_i(qspi_dq_i),
+    .qspi_dq_o(qspi_dq_o),
+    .qspi_dq_oe(qspi_dq_oe),
+    .qspi_cs(qspi_cs)
+);
+
+endmodule
+
+`resetall

src/cndm/board/VCU118/fpga/rtl/fpga_core.sv

@@ -720,7 +720,7 @@ wire ptp_pps_str;
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3",  "QSFP1.4"};
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3",  "QSFP2.4"};
 
-for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
 
     localparam CNT = 4;
 

src/cndm/board/VCU118/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -293,8 +294,7 @@ class TB:
         self.qsfp_sources = []
         self.qsfp_sinks = []
 
-        for inst in dut.uut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.uut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64:

src/cndm/board/fb2CG/fpga/rtl/fpga_core.sv

@@ -293,7 +293,7 @@ wire qsfp_mgt_refclk_bufg[2];
 
 wire qsfp_rst[2];
 
-for (genvar n = 0; n < 2; n = n + 1) begin : gty_clk
+for (genvar n = 0; n < 2; n = n + 1) begin : gt_clk
 
     wire qsfp_mgt_refclk_int;
 
@@ -363,7 +363,7 @@ assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n;
 assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p;
 assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n;
 
-for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
 
     localparam CLK = n;
     localparam CNT = 4;

src/cndm/board/fb2CG/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -283,8 +284,7 @@ class TB:
         self.qsfp_sources = []
         self.qsfp_sinks = []
 
-        for inst in dut.uut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.uut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64:

src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv

@@ -146,7 +146,7 @@ assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n;
 assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p;
 assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n;
 
-for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
 
     localparam CNT = 4;
 

src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -46,8 +47,7 @@ class TB:
         self.qsfp_sources = []
         self.qsfp_sinks = []
 
-        for inst in dut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64:

src/eth/example/Alveo/fpga/rtl/fpga_au200.sv

@@ -252,6 +252,12 @@ assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_0_n;
 
 assign clk_156mhz_ref_int = eth_gty_mgt_refclk_out[0];
 
+wire uart_txd_int[1];
+wire uart_rxd_int[1];
+
+assign uart_txd = uart_txd_int[0];
+assign uart_rxd_int[0] = uart_rxd;
+
 fpga_core #(
     .SIM(SIM),
     .VENDOR(VENDOR),
@@ -289,8 +295,8 @@ core_inst (
     /*
      * UART
      */
-    .uart_txd(uart_txd),
+    .uart_txd(uart_txd_int),
-    .uart_rxd(uart_rxd),
+    .uart_rxd(uart_rxd_int),
 
     /*
      * Ethernet

src/eth/example/Alveo/fpga/rtl/fpga_au280.sv

@@ -215,6 +215,12 @@ assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_0_n;
 
 assign clk_156mhz_ref_int = eth_gty_mgt_refclk_out[0];
 
+wire uart_txd_int[1];
+wire uart_rxd_int[1];
+
+assign uart_txd = uart_txd_int[0];
+assign uart_rxd_int[0] = uart_rxd;
+
 fpga_core #(
     .SIM(SIM),
     .VENDOR(VENDOR),
@@ -252,8 +258,8 @@ core_inst (
     /*
      * UART
      */
-    .uart_txd(uart_txd),
+    .uart_txd(uart_txd_int),
-    .uart_rxd(uart_rxd),
+    .uart_rxd(uart_rxd_int),
 
     /*
      * Ethernet

src/eth/example/Alveo/fpga/rtl/fpga_au45n.sv

@@ -44,8 +44,8 @@ module fpga #
     /*
      * UART
      */
-    output wire logic [UART_CNT-1:0]  uart_txd,
+    output wire logic                 uart_txd[UART_CNT],
-    input  wire logic [UART_CNT-1:0]  uart_rxd,
+    input  wire logic                 uart_rxd[UART_CNT],
 
     /*
      * Ethernet: QSFP28

src/eth/example/Alveo/fpga/rtl/fpga_au50.sv

@@ -43,8 +43,8 @@ module fpga #
     /*
      * UART
      */
-    output wire logic [UART_CNT-1:0]  uart_txd,
+    output wire logic                 uart_txd[UART_CNT],
-    input  wire logic [UART_CNT-1:0]  uart_rxd,
+    input  wire logic                 uart_rxd[UART_CNT],
 
     /*
      * Ethernet: QSFP28

src/eth/example/Alveo/fpga/rtl/fpga_au55.sv

@@ -48,8 +48,8 @@ module fpga #
     /*
      * UART
      */
-    output wire logic [UART_CNT-1:0]  uart_txd,
+    output wire logic                 uart_txd[UART_CNT],
-    input  wire logic [UART_CNT-1:0]  uart_rxd,
+    input  wire logic                 uart_rxd[UART_CNT],
 
     /*
      * Ethernet: QSFP28

src/eth/example/Alveo/fpga/rtl/fpga_core.sv

@@ -59,8 +59,8 @@ module fpga_core #
     /*
      * UART
      */
-    output wire [UART_CNT-1:0]           uart_txd,
+    output wire                          uart_txd[UART_CNT],
-    input  wire [UART_CNT-1:0]           uart_rxd,
+    input  wire                          uart_rxd[UART_CNT],
 
     /*
      * Ethernet
@@ -249,7 +249,7 @@ wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
 
 wire eth_gty_rst[GTY_CLK_CNT];
 
-for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
+for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gt_clk
 
     wire eth_gty_mgt_refclk_int;
 
@@ -297,7 +297,7 @@ end
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3",  "QSFP1.4"};
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3",  "QSFP2.4"};
 
-for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
 
     localparam CLK = n;
     localparam CNT = 4;

src/eth/example/Alveo/fpga/rtl/fpga_x3522.sv

@@ -42,8 +42,8 @@ module fpga #
     /*
      * UART
      */
-    output wire logic [UART_CNT-1:0]  uart_txd,
+    output wire logic                 uart_txd[UART_CNT],
-    input  wire logic [UART_CNT-1:0]  uart_rxd,
+    input  wire logic                 uart_rxd[UART_CNT],
 
     /*
      * Ethernet: QSFP28

src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -42,8 +43,8 @@ class TB:
 
         cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
 
-        self.uart_source = UartSource(dut.uart_rxd, baud=3000000, bits=8, stop_bits=1)
+        self.uart_sources = [UartSource(pin, baud=3000000, bits=8, stop_bits=1) for pin in dut.uart_rxd]
-        self.uart_sink = UartSink(dut.uart_txd, baud=3000000, bits=8, stop_bits=1)
+        self.uart_sinks = [UartSink(pin, baud=3000000, bits=8, stop_bits=1) for pin in dut.uart_txd]
 
         self.qsfp_sources = []
         self.qsfp_sinks = []
@@ -51,8 +52,7 @@ class TB:
         for clk in dut.eth_gty_mgt_refclk_p:
             cocotb.start_soon(Clock(clk, 6.4, units="ns").start())
 
-        for inst in dut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64:

src/eth/example/HTG9200/fpga/rtl/fpga_core.sv

@@ -317,7 +317,7 @@ wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
 
 wire eth_gty_rst[GTY_CLK_CNT];
 
-for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
+for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gt_clk
 
     wire eth_gty_mgt_refclk_int;
 
@@ -378,7 +378,7 @@ localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP13[4] = '{"QSFP13.1", "QSFP13.2",
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP14[4] = '{"QSFP14.1", "QSFP14.2", "QSFP14.3",  "QSFP14.4"};
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP15[4] = '{"QSFP15.1", "QSFP15.2", "QSFP15.3",  "QSFP15.4"};
 
-for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
 
     localparam CLK = n;
     localparam CNT = 4;

src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -52,8 +53,7 @@ class TB:
         for clk in dut.eth_gty_mgt_refclk_p:
             cocotb.start_soon(Clock(clk, 6.206, units="ns").start())
 
-        for inst in dut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64:

src/eth/example/NT200A02/fpga/README.md

@@ -0,0 +1,52 @@
+# Taxi Example Design for NT200A01/NT200A02
+
+## Introduction
+
+This example design targets the Napatech NT200A01/NT200A02 FPGA board.
+
+The design places looped-back MACs on the QSFP28 ports.
+
+* QSFP28
+  * Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
+
+## Board details
+
+* FPGA
+  * NT200A01: xcvu095-ffva2104-2-e
+  * NT200A02: xcvu5p-flva2104-2-e
+* 25GBASE-R PHY: Soft PCS with GTY transceivers
+
+## Licensing
+
+* Toolchain
+  * Vivado Enterprise (requires license)
+* IP
+  * No licensed vendor IP or 3rd party IP
+
+## How to build
+
+Run `make` in the appropriate `fpga*` subdirectory to build the bitstream.  Ensure that the Xilinx Vivado toolchain components are in PATH.
+
+## How to test
+
+Run `make program` to program the board with Vivado.
+
+To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback.  Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
+
+## JTAG pinout
+
+Napatech boards use a non-standard connector for JTAG.  There are three debug connectors, and one of them carries the JTAG signals for the FPGA.
+
+        J16             J22
+        FPGA            AVR
+    TDI 7 8 GND     TDI 7 8 GND
+    TMS 5 6 HALT    TMS 5 6
+    TDO 3 4 Vref    TDO 3 4 Vref
+    TCK 1 2 GND     TCK 1 2 GND
+
+            J17
+        GND 2 1
+            4 3
+            6 5
+
+Note: J18.6 HALT must be driven low to access the JTAG chain.  So, either tie to to ground, or connect it to the HALT signal on DLC9/DLC10 cables.

src/eth/example/NT200A02/fpga/common/vivado.mk

@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: MIT
+###################################################################
+#
+# Xilinx Vivado FPGA Makefile
+#
+# Copyright (c) 2016-2025 Alex Forencich
+#
+###################################################################
+#
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - list of source files
+# INC_FILES - list of include files
+# XDC_FILES - list of timing constraint files
+# XCI_FILES - list of IP XCI files
+# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
+# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
+#
+# Note: both SYN_FILES and INC_FILES support file list files.  File list
+# files are files with a .f extension that contain a list of additional
+# files to include, one path relative to the .f file location per line.
+# The .f files are processed recursively, and then the complete file list
+# is de-duplicated, with later files in the list taking precedence.
+#
+# Example:
+#
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+#
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include $(CONFIG)
+
+FPGA_TOP ?= fpga
+PROJECT ?= $(FPGA_TOP)
+XDC_FILES ?= $(PROJECT).xdc
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
+INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
+
+###################################################################
+# Main Targets
+#
+# all: build everything (fpga)
+# fpga: build FPGA config
+# vivado: open project in Vivado
+# tmpclean: remove intermediate files
+# clean: remove output files and project files
+# distclean: remove archived output files
+###################################################################
+
+all: fpga
+
+fpga: $(PROJECT).bit
+
+vivado: $(PROJECT).xpr
+	vivado $(PROJECT).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+	-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+
+# create fresh project if Makefile or IP files have changed
+create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
+	echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
+	for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+# source config TCL scripts if any source file has changed
+update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
+	echo "open_project -quiet $(PROJECT).xpr" > $@
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+$(PROJECT).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
+	echo "open_project $(PROJECT).xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
+	echo "open_project $(PROJECT).xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "open_run impl_1" >> run_impl.tcl
+	echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
+	echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# output files (including potentially bit, bin, ltx, and xsa)
+$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
+	echo "open_project $(PROJECT).xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
+	echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
+	echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
+	if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi

src/eth/example/NT200A02/fpga/fpga_NT200A01/Makefile

@@ -0,0 +1,157 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xcvu095-ffva2104-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = virtexu
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga_nt200a01.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(RTL_DIR)/../pll/si5340_i2c_init.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/lss/rtl/taxi_i2c_master.sv
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+
+# XDC files
+XDC_FILES = ../fpga_nt200a01.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl
+
+# Configuration
+CONFIG_TCL_FILES = config.tcl
+
+include ../common/vivado.mk
+
+%_fallback.bit: %.bit
+	echo "open_project $*.xpr" > generate_fallback_bit.tcl
+	echo "open_run impl_1" >> generate_fallback_bit.tcl
+	echo "startgroup" >> generate_fallback_bit.tcl
+	echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl
+	echo "endgroup" >> generate_fallback_bit.tcl
+	echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
+	echo "undo" >> generate_fallback_bit.tcl
+	echo "exit" >> generate_fallback_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
+
+program: $(FPGA_TOP).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+%_fallback.mcs %_fallback.prm: %_fallback.bit
+	echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x03000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
+	echo "exit" >> generate_fallback_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
+	echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
+
+%_full.mcs %_full.prm: %_fallback.bit %.bit
+	echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x03000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
+	echo "exit" >> generate_full_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
+	echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw_manager" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+
+flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
+	echo "open_hw_manager" > flash$*.tcl
+	echo "connect_hw_server" >> flash$*.tcl
+	echo "open_hw_target" >> flash$*.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash$*.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
+	echo "exit" >> flash$*.tcl
+	vivado -nojournal -nolog -mode batch -source flash$*.tcl

src/eth/example/NT200A02/fpga/fpga_NT200A01/config.tcl

@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "1"
+dict set params MAC_DATA_W "64"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/eth/example/NT200A02/fpga/fpga_NT200A01_10g/Makefile

@@ -0,0 +1,157 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xcvu095-ffva2104-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = virtexu
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga_nt200a01.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(RTL_DIR)/../pll/si5340_i2c_init.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/lss/rtl/taxi_i2c_master.sv
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+
+# XDC files
+XDC_FILES = ../fpga_nt200a01.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_322.tcl
+
+# Configuration
+CONFIG_TCL_FILES = config.tcl
+
+include ../common/vivado.mk
+
+%_fallback.bit: %.bit
+	echo "open_project $*.xpr" > generate_fallback_bit.tcl
+	echo "open_run impl_1" >> generate_fallback_bit.tcl
+	echo "startgroup" >> generate_fallback_bit.tcl
+	echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl
+	echo "endgroup" >> generate_fallback_bit.tcl
+	echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
+	echo "undo" >> generate_fallback_bit.tcl
+	echo "exit" >> generate_fallback_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
+
+program: $(FPGA_TOP).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+%_fallback.mcs %_fallback.prm: %_fallback.bit
+	echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x03000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
+	echo "exit" >> generate_fallback_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
+	echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
+
+%_full.mcs %_full.prm: %_fallback.bit %.bit
+	echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x03000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
+	echo "exit" >> generate_full_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
+	echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw_manager" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+
+flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
+	echo "open_hw_manager" > flash$*.tcl
+	echo "connect_hw_server" >> flash$*.tcl
+	echo "open_hw_target" >> flash$*.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash$*.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
+	echo "exit" >> flash$*.tcl
+	vivado -nojournal -nolog -mode batch -source flash$*.tcl

src/eth/example/NT200A02/fpga/fpga_NT200A01_10g/config.tcl

@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "1"
+dict set params MAC_DATA_W "32"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/eth/example/NT200A02/fpga/fpga_NT200A02/Makefile

@@ -0,0 +1,157 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xcvu5p-flva2104-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = virtexuplus
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga_nt200a02.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(RTL_DIR)/../pll/si5340_i2c_init.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/lss/rtl/taxi_i2c_master.sv
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+
+# XDC files
+XDC_FILES = ../fpga_nt200a02.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl
+
+# Configuration
+CONFIG_TCL_FILES = config.tcl
+
+include ../common/vivado.mk
+
+%_fallback.bit: %.bit
+	echo "open_project $*.xpr" > generate_fallback_bit.tcl
+	echo "open_run impl_1" >> generate_fallback_bit.tcl
+	echo "startgroup" >> generate_fallback_bit.tcl
+	echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl
+	echo "endgroup" >> generate_fallback_bit.tcl
+	echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
+	echo "undo" >> generate_fallback_bit.tcl
+	echo "exit" >> generate_fallback_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
+
+program: $(FPGA_TOP).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+%_fallback.mcs %_fallback.prm: %_fallback.bit
+	echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x0C000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
+	echo "exit" >> generate_fallback_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
+	echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
+
+%_full.mcs %_full.prm: %_fallback.bit %.bit
+	echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x0C000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
+	echo "exit" >> generate_full_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
+	echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw_manager" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+
+flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
+	echo "open_hw_manager" > flash$*.tcl
+	echo "connect_hw_server" >> flash$*.tcl
+	echo "open_hw_target" >> flash$*.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash$*.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
+	echo "exit" >> flash$*.tcl
+	vivado -nojournal -nolog -mode batch -source flash$*.tcl

src/eth/example/NT200A02/fpga/fpga_NT200A02/config.tcl

@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "1"
+dict set params MAC_DATA_W "64"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/eth/example/NT200A02/fpga/fpga_NT200A02_10g/Makefile

@@ -0,0 +1,157 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xcvu5p-flva2104-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = virtexuplus
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga_nt200a02.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(RTL_DIR)/../pll/si5340_i2c_init.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/lss/rtl/taxi_i2c_master.sv
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+
+# XDC files
+XDC_FILES = ../fpga_nt200a02.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_322.tcl
+
+# Configuration
+CONFIG_TCL_FILES = config.tcl
+
+include ../common/vivado.mk
+
+%_fallback.bit: %.bit
+	echo "open_project $*.xpr" > generate_fallback_bit.tcl
+	echo "open_run impl_1" >> generate_fallback_bit.tcl
+	echo "startgroup" >> generate_fallback_bit.tcl
+	echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl
+	echo "endgroup" >> generate_fallback_bit.tcl
+	echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
+	echo "undo" >> generate_fallback_bit.tcl
+	echo "exit" >> generate_fallback_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
+
+program: $(FPGA_TOP).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+%_fallback.mcs %_fallback.prm: %_fallback.bit
+	echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x0C000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
+	echo "exit" >> generate_fallback_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
+	echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
+
+%_full.mcs %_full.prm: %_fallback.bit %.bit
+	echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x0C000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
+	echo "exit" >> generate_full_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
+	echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw_manager" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+
+flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
+	echo "open_hw_manager" > flash$*.tcl
+	echo "connect_hw_server" >> flash$*.tcl
+	echo "open_hw_target" >> flash$*.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash$*.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
+	echo "exit" >> flash$*.tcl
+	vivado -nojournal -nolog -mode batch -source flash$*.tcl

src/eth/example/NT200A02/fpga/fpga_NT200A02_10g/config.tcl

@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "1"
+dict set params MAC_DATA_W "32"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/eth/example/NT200A02/fpga/fpga_nt200a01.xdc

@@ -0,0 +1,262 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Napatech NT200A01 board
+# part: xcvu095-ffva2104-2-e
+
+# General configuration
+set_property CFGBVS GND                                [current_design]
+set_property CONFIG_VOLTAGE 1.8                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
+set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
+
+# System clocks
+# 50 MHz system clock
+set_property -dict {LOC AK34 IOSTANDARD LVCMOS18} [get_ports clk_50mhz] ;# U10
+create_clock -period 20.000 -name clk_50mhz [get_ports clk_50mhz]
+
+# 80 MHz EMCCLK
+#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_80mhz] ;# U9
+#create_clock -period 12.500 -name clk_80mhz [get_ports clk_80mhz]
+
+# 20 MHz reference clock
+#set_property -dict {LOC AM33 IOSTANDARD LVCMOS18} [get_ports clk_20mhz] ;# U201/U22
+#create_clock -period 12.500 -name clk_20mhz [get_ports clk_20mhz]
+
+# 100 MHz DDR4 C0 clock from Si5340 OUT0 via U167
+#set_property -dict {LOC BA19 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c0_p]
+#set_property -dict {LOC AY19 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c0_n]
+#create_clock -period 10.000 -name clk_ddr_c0 [get_ports clk_ddr_c0_p]
+
+# 100 MHz DDR4 C1 clock from Si5340 OUT0 via U167
+#set_property -dict {LOC BB39 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c1_p]
+#set_property -dict {LOC BB38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c1_n]
+#create_clock -period 10.000 -name clk_ddr_c1 [get_ports clk_ddr_c1_p]
+
+# 100 MHz DDR4 C2 clock from Si5340 OUT0 via U167
+#set_property -dict {LOC B10  IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c2_p]
+#set_property -dict {LOC C10  IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c2_n]
+#create_clock -period 10.000 -name clk_ddr_c2 [get_ports clk_ddr_c2_p]
+
+# LEDs
+set_property -dict {LOC R26  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[0]}] ;# D5
+set_property -dict {LOC M28  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[1]}] ;# D6
+set_property -dict {LOC R27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[2]}] ;# D7
+set_property -dict {LOC T24  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[3]}] ;# D8
+set_property -dict {LOC J27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][0]}] ;# D16
+set_property -dict {LOC K27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][1]}] ;# D17
+set_property -dict {LOC L25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][2]}] ;# D18
+set_property -dict {LOC L24  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][3]}] ;# D29
+set_property -dict {LOC B28  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][0]}] ;# D27
+set_property -dict {LOC C27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][1]}] ;# D28
+set_property -dict {LOC J25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][2]}] ;# D29
+set_property -dict {LOC K26  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][3]}] ;# D30
+set_property -dict {LOC D27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_red}] ;# D52
+set_property -dict {LOC D26  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_green}] ;# D52
+set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_sync[0]}] ;# D54
+set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_sync[1]}] ;# D56
+set_property -dict {LOC M15  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {eth_led_yellow}] ;# J28
+set_property -dict {LOC M13  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {eth_led_green}] ;# J28
+
+set_false_path -to [get_ports {led[*] qsfp_led[*][*] led_red led_green led_sync[*] eth_led_yellow eth_led_green}]
+set_output_delay 0 [get_ports {led[*] qsfp_led[*][*] led_red led_green led_sync[*] eth_led_yellow eth_led_green}]
+
+# Si5340 U18
+set_property -dict {LOC AT36 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5340_i2c_scl] ;# U23.14 SCLK
+set_property -dict {LOC AT35 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5340_i2c_sda] ;# U23.13 SDA
+set_property -dict {LOC AT37 IOSTANDARD LVCMOS18} [get_ports si5340_intr] ;# U18.33 INTR
+
+set_false_path -to [get_ports {si5340_i2c_scl si5340_i2c_sda}]
+set_output_delay 0 [get_ports {si5340_i2c_scl si5340_i2c_sda}]
+set_false_path -from [get_ports {si5340_i2c_scl si5340_i2c_sda si5340_intr}]
+set_input_delay 0 [get_ports {si5340_i2c_scl si5340_i2c_sda si5340_intr}]
+
+# Gigabit PHY (DP83867)
+#set_property -dict {LOC P12  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_gtx_clk] ;# U198.29 GTX_CLK via ?
+#set_property -dict {LOC P15  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_tx_ctl] ;# U198.37 TX_CTRL via ?
+#set_property -dict {LOC R11  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] ;# U198.28 TX_D0/SGMII_SIN via ?
+#set_property -dict {LOC R12  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] ;# U198.27 TX_D1/SGMII_SIP via ?
+#set_property -dict {LOC P11  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] ;# U198.26 TX_D2 via ?
+#set_property -dict {LOC N12  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] ;# U198.25 TX_D3 via ?
+#set_property -dict {LOC U13  IOSTANDARD LVCMOS18} [get_ports phy_rx_clk] ;# U198.32 RX_CLK via ?
+#set_property -dict {LOC U16  IOSTANDARD LVCMOS18} [get_ports phy_rx_ctl] ;# U198.38 RX_CTRL via ?
+#set_property -dict {LOC T11  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[0]}] ;# U198.33 RX_D0/SGMII_COP via ?
+#set_property -dict {LOC U11  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[1]}] ;# U198.34 RX_D1/SGMII_CON via ?
+#set_property -dict {LOC R13  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[2]}] ;# U198.35 RX_D2/SGMII_SOP via ?
+#set_property -dict {LOC V15  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[3]}] ;# U198.36 RX_D3/SGMII_SON via ?
+#set_property -dict {LOC J11  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_refclk] ;# U198.15 XI 25 MHz
+#set_property -dict {LOC T14  IOSTANDARD LVCMOS18} [get_ports phy_clk_out] ;# U198.18 CLK_OUT
+#set_property -dict {LOC M11  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_reset_n] ;# U198.43 RESET_N
+#set_property -dict {LOC V16  IOSTANDARD LVCMOS18} [get_ports phy_int_n] ;# U198.44 PWRDOWN/INTN
+#set_property -dict {LOC U12  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_mdc] ;# U198.16 MDC
+#set_property -dict {LOC J12  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_mdio] ;# U198.17 MDIO
+#set_property -dict {LOC L14  IOSTANDARD LVCMOS18} [get_ports phy_gpio0] ;# U198.39 GPIO_0
+#set_property -dict {LOC M12  IOSTANDARD LVCMOS18} [get_ports phy_gpio1] ;# U198.40 GPIO_1
+#set_property -dict {LOC L15  IOSTANDARD LVCMOS18} [get_ports phy_led0] ;# U198.47 LED_0
+#set_property -dict {LOC W14  IOSTANDARD LVCMOS18} [get_ports phy_led1] ;# U198.46 LED_1
+#set_property -dict {LOC K14  IOSTANDARD LVCMOS18} [get_ports phy_led2] ;# U198.45 LED_2
+
+# QSFP28 Interfaces
+set_property -dict {LOC R45 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC R46 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC M42 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC M43 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC U45 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC U46 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC P42 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC P43 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC N45 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC N46 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC K42 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC K43 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC W45 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC W46 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC T42 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC T43 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
+set_property -dict {LOC V38 } [get_ports qsfp0_mgt_refclk_p] ;# MGTREFCLK0P_129 from Si5340 U23 OUT1
+set_property -dict {LOC V39 } [get_ports qsfp0_mgt_refclk_n] ;# MGTREFCLK0N_129 from Si5340 U23 OUT1
+set_property -dict {LOC A26  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl]
+set_property -dict {LOC C25  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp0_modprsl]
+set_property -dict {LOC B26  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp0_intl]
+set_property -dict {LOC G25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode]
+set_property -dict {LOC B25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_scl]
+set_property -dict {LOC F25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_sda]
+
+# 322.265625 MHz MGT reference clock
+create_clock -period 3.103 -name qsfp0_mgt_refclk [get_ports qsfp0_mgt_refclk_p]
+
+set_false_path -to [get_ports {qsfp0_resetl qsfp0_lpmode}]
+set_output_delay 0 [get_ports {qsfp0_resetl qsfp0_lpmode}]
+set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
+set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
+
+set_false_path -to [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
+set_output_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
+set_false_path -from [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
+set_input_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
+
+set_property -dict {LOC G45 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP2_130 GTYE3_CHANNEL_X0Y26 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC G46 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN2_130 GTYE3_CHANNEL_X0Y26 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC D42 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP2_130 GTYE3_CHANNEL_X0Y26 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC D43 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN2_130 GTYE3_CHANNEL_X0Y26 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC J45 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC J46 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC F42 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC F43 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC E45 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP3_130 GTYE3_CHANNEL_X0Y27 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC E46 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN3_130 GTYE3_CHANNEL_X0Y27 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC B42 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP3_130 GTYE3_CHANNEL_X0Y27 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC B43 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN3_130 GTYE3_CHANNEL_X0Y27 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC L45 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC L46 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC H42 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC H43 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
+set_property -dict {LOC R40 } [get_ports qsfp1_mgt_refclk_p] ;# MGTREFCLK0P_130 from Si5340 U23 OUT2
+set_property -dict {LOC R41 } [get_ports qsfp1_mgt_refclk_n] ;# MGTREFCLK0N_130 from Si5340 U23 OUT2
+set_property -dict {LOC B27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl]
+set_property -dict {LOC H28  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_modprsl]
+set_property -dict {LOC N24  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_intl]
+set_property -dict {LOC H25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode]
+set_property -dict {LOC P27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_scl]
+set_property -dict {LOC R24  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_sda]
+
+# 322.265625 MHz MGT reference clock
+create_clock -period 3.103 -name qsfp1_mgt_refclk [get_ports qsfp1_mgt_refclk_p]
+
+set_false_path -to [get_ports {qsfp1_resetl qsfp1_lpmode}]
+set_output_delay 0 [get_ports {qsfp1_resetl qsfp1_lpmode}]
+set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}]
+set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}]
+
+set_false_path -to [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
+set_output_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
+set_false_path -from [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
+set_input_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
+
+# PCIe Interface
+#set_property -dict {LOC U4  } [get_ports {pcie_rx_p[0]}]  ;# MGTHRXP3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4
+#set_property -dict {LOC U3  } [get_ports {pcie_rx_n[0]}]  ;# MGTHRXN3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4
+#set_property -dict {LOC M7  } [get_ports {pcie_tx_p[0]}]  ;# MGTHTXP3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4
+#set_property -dict {LOC M6  } [get_ports {pcie_tx_n[0]}]  ;# MGTHTXN3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4
+#set_property -dict {LOC V2  } [get_ports {pcie_rx_p[1]}]  ;# MGTHRXP2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4
+#set_property -dict {LOC V1  } [get_ports {pcie_rx_n[1]}]  ;# MGTHRXN2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4
+#set_property -dict {LOC P7  } [get_ports {pcie_tx_p[1]}]  ;# MGTHTXP2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4
+#set_property -dict {LOC P6  } [get_ports {pcie_tx_n[1]}]  ;# MGTHTXN2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4
+#set_property -dict {LOC W4  } [get_ports {pcie_rx_p[2]}]  ;# MGTHRXP1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4
+#set_property -dict {LOC W3  } [get_ports {pcie_rx_n[2]}]  ;# MGTHRXN1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4
+#set_property -dict {LOC T7  } [get_ports {pcie_tx_p[2]}]  ;# MGTHTXP1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4
+#set_property -dict {LOC T6  } [get_ports {pcie_tx_n[2]}]  ;# MGTHTXN1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4
+#set_property -dict {LOC Y2  } [get_ports {pcie_rx_p[3]}]  ;# MGTHRXP0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4
+#set_property -dict {LOC Y1  } [get_ports {pcie_rx_n[3]}]  ;# MGTHRXN0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4
+#set_property -dict {LOC V7  } [get_ports {pcie_tx_p[3]}]  ;# MGTHTXP0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4
+#set_property -dict {LOC V6  } [get_ports {pcie_tx_n[3]}]  ;# MGTHTXN0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4
+#set_property -dict {LOC AA4 } [get_ports {pcie_rx_p[4]}]  ;# MGTHRXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3
+#set_property -dict {LOC AA3 } [get_ports {pcie_rx_n[4]}]  ;# MGTHRXN3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3
+#set_property -dict {LOC Y7  } [get_ports {pcie_tx_p[4]}]  ;# MGTHTXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3
+#set_property -dict {LOC Y6  } [get_ports {pcie_tx_n[4]}]  ;# MGTHTXN3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3
+#set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[5]}]  ;# MGTHRXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3
+#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[5]}]  ;# MGTHRXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3
+#set_property -dict {LOC AB7 } [get_ports {pcie_tx_p[5]}]  ;# MGTHTXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3
+#set_property -dict {LOC AB6 } [get_ports {pcie_tx_n[5]}]  ;# MGTHTXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3
+#set_property -dict {LOC AC4 } [get_ports {pcie_rx_p[6]}]  ;# MGTHRXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
+#set_property -dict {LOC AC3 } [get_ports {pcie_rx_n[6]}]  ;# MGTHRXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
+#set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[6]}]  ;# MGTHTXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
+#set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[6]}]  ;# MGTHTXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
+#set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[7]}]  ;# MGTHRXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
+#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[7]}]  ;# MGTHRXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
+#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[7]}]  ;# MGTHTXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
+#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[7]}]  ;# MGTHTXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
+#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[8]}]  ;# MGTHRXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[8]}]  ;# MGTHRXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}]  ;# MGTHTXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}]  ;# MGTHTXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[9]}]  ;# MGTHRXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[9]}]  ;# MGTHRXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AR5 } [get_ports {pcie_tx_p[9]}]  ;# MGTHTXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AR4 } [get_ports {pcie_tx_n[9]}]  ;# MGTHTXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[10]}] ;# MGTHRXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[10]}] ;# MGTHRXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTHTXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTHTXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[11]}] ;# MGTHRXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[11]}] ;# MGTHRXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AU5 } [get_ports {pcie_tx_p[11]}] ;# MGTHTXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AU4 } [get_ports {pcie_tx_n[11]}] ;# MGTHTXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
+#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[12]}] ;# MGTHRXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[12]}] ;# MGTHRXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC AW5 } [get_ports {pcie_tx_p[12]}] ;# MGTHTXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC AW4 } [get_ports {pcie_tx_n[12]}] ;# MGTHTXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[13]}] ;# MGTHRXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[13]}] ;# MGTHRXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC BA5 } [get_ports {pcie_tx_p[13]}] ;# MGTHTXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC BA4 } [get_ports {pcie_tx_n[13]}] ;# MGTHTXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC AY2 } [get_ports {pcie_rx_p[14]}] ;# MGTHRXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC AY1 } [get_ports {pcie_rx_n[14]}] ;# MGTHRXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC BC5 } [get_ports {pcie_tx_p[14]}] ;# MGTHTXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC BC4 } [get_ports {pcie_tx_n[14]}] ;# MGTHTXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC BB2 } [get_ports {pcie_rx_p[15]}] ;# MGTHRXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC BB1 } [get_ports {pcie_rx_n[15]}] ;# MGTHRXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC BE5 } [get_ports {pcie_tx_p[15]}] ;# MGTHTXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC BE4 } [get_ports {pcie_tx_n[15]}] ;# MGTHTXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
+#set_property -dict {LOC AR9 } [get_ports pcie_refclk_0_p] ;# MGTREFCLK0P_224
+#set_property -dict {LOC AR8 } [get_ports pcie_refclk_0_n] ;# MGTREFCLK0N_224
+#set_property -dict {LOC AC9 } [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_227
+#set_property -dict {LOC AC8 } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_227
+#set_property -dict {LOC AM17 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset]
+
+# 100 MHz MGT reference clock
+#create_clock -period 10.000 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p]
+#create_clock -period 10.000 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
+
+#set_false_path -from [get_ports {pcie_reset}]
+#set_input_delay 0 [get_ports {pcie_reset}]

src/eth/example/NT200A02/fpga/fpga_nt200a02.xdc

@@ -0,0 +1,259 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Napatech NT200A02 board
+# part: xcvu5p-flva2104-2-e
+
+# General configuration
+set_property CFGBVS GND                                [current_design]
+set_property CONFIG_VOLTAGE 1.8                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
+set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
+
+# System clocks
+# 50 MHz system clock
+set_property -dict {LOC AK34 IOSTANDARD LVCMOS18} [get_ports clk_50mhz] ;# U10
+create_clock -period 20.000 -name clk_50mhz [get_ports clk_50mhz]
+
+# 80 MHz EMCCLK
+#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_80mhz] ;# U9
+#create_clock -period 12.500 -name clk_80mhz [get_ports clk_80mhz]
+
+# 20 MHz reference clock
+#set_property -dict {LOC AM33 IOSTANDARD LVCMOS18} [get_ports clk_20mhz] ;# U201/U22
+#create_clock -period 12.500 -name clk_20mhz [get_ports clk_20mhz]
+
+# 100 MHz DDR4 C0 clock from Si5340 OUT0 via U167
+#set_property -dict {LOC BA19 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c0_p]
+#set_property -dict {LOC AY19 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c0_n]
+#create_clock -period 10.000 -name clk_ddr_c0 [get_ports clk_ddr_c0_p]
+
+# 100 MHz DDR4 C1 clock from Si5340 OUT0 via U167
+#set_property -dict {LOC BB39 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c1_p]
+#set_property -dict {LOC BB38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c1_n]
+#create_clock -period 10.000 -name clk_ddr_c1 [get_ports clk_ddr_c1_p]
+
+# 100 MHz DDR4 C2 clock from Si5340 OUT0 via U167
+#set_property -dict {LOC B10  IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c2_p]
+#set_property -dict {LOC C10  IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_c2_n]
+#create_clock -period 10.000 -name clk_ddr_c2 [get_ports clk_ddr_c2_p]
+
+# LEDs
+set_property -dict {LOC R26  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[0]}] ;# D5
+set_property -dict {LOC M28  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[1]}] ;# D6
+set_property -dict {LOC R27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[2]}] ;# D7
+set_property -dict {LOC T24  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[3]}] ;# D8
+set_property -dict {LOC J27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][0]}] ;# D16
+set_property -dict {LOC K27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][1]}] ;# D17
+set_property -dict {LOC L25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][2]}] ;# D18
+set_property -dict {LOC L24  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[0][3]}] ;# D29
+set_property -dict {LOC B28  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][0]}] ;# D27
+set_property -dict {LOC C27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][1]}] ;# D28
+set_property -dict {LOC J25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][2]}] ;# D29
+set_property -dict {LOC K26  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {qsfp_led[1][3]}] ;# D30
+set_property -dict {LOC D27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_red}] ;# D52
+set_property -dict {LOC D26  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_green}] ;# D52
+set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_sync[0]}] ;# D54
+set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_sync[1]}] ;# D56
+set_property -dict {LOC M15  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {eth_led_yellow}] ;# J28
+set_property -dict {LOC M13  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {eth_led_green}] ;# J28
+
+set_false_path -to [get_ports {led[*] qsfp_led[*][*] led_red led_green led_sync[*] eth_led_yellow eth_led_green}]
+set_output_delay 0 [get_ports {led[*] qsfp_led[*][*] led_red led_green led_sync[*] eth_led_yellow eth_led_green}]
+
+# Si5340 U18
+set_property -dict {LOC AT36 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5340_i2c_scl] ;# U23.14 SCLK
+set_property -dict {LOC AT35 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5340_i2c_sda] ;# U23.13 SDA
+set_property -dict {LOC AT37 IOSTANDARD LVCMOS18} [get_ports si5340_intr] ;# U18.33 INTR
+
+set_false_path -to [get_ports {si5340_i2c_scl si5340_i2c_sda}]
+set_output_delay 0 [get_ports {si5340_i2c_scl si5340_i2c_sda}]
+set_false_path -from [get_ports {si5340_i2c_scl si5340_i2c_sda si5340_intr}]
+set_input_delay 0 [get_ports {si5340_i2c_scl si5340_i2c_sda si5340_intr}]
+
+# Gigabit PHY (DP83867)
+#set_property -dict {LOC P12  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_gtx_clk] ;# U198.29 GTX_CLK via ?
+#set_property -dict {LOC P15  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_tx_ctl] ;# U198.37 TX_CTRL via ?
+#set_property -dict {LOC R11  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] ;# U198.28 TX_D0/SGMII_SIN via ?
+#set_property -dict {LOC R12  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] ;# U198.27 TX_D1/SGMII_SIP via ?
+#set_property -dict {LOC P11  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] ;# U198.26 TX_D2 via ?
+#set_property -dict {LOC N12  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] ;# U198.25 TX_D3 via ?
+#set_property -dict {LOC U13  IOSTANDARD LVCMOS18} [get_ports phy_rx_clk] ;# U198.32 RX_CLK via ?
+#set_property -dict {LOC U16  IOSTANDARD LVCMOS18} [get_ports phy_rx_ctl] ;# U198.38 RX_CTRL via ?
+#set_property -dict {LOC T11  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[0]}] ;# U198.33 RX_D0/SGMII_COP via ?
+#set_property -dict {LOC U11  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[1]}] ;# U198.34 RX_D1/SGMII_CON via ?
+#set_property -dict {LOC R13  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[2]}] ;# U198.35 RX_D2/SGMII_SOP via ?
+#set_property -dict {LOC V15  IOSTANDARD LVCMOS18} [get_ports {phy_rxd[3]}] ;# U198.36 RX_D3/SGMII_SON via ?
+#set_property -dict {LOC J11  IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports phy_refclk] ;# U198.15 XI 25 MHz
+#set_property -dict {LOC T14  IOSTANDARD LVCMOS18} [get_ports phy_clk_out] ;# U198.18 CLK_OUT
+#set_property -dict {LOC M11  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_reset_n] ;# U198.43 RESET_N
+#set_property -dict {LOC V16  IOSTANDARD LVCMOS18} [get_ports phy_int_n] ;# U198.44 PWRDOWN/INTN
+#set_property -dict {LOC U12  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_mdc] ;# U198.16 MDC
+#set_property -dict {LOC J12  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports phy_mdio] ;# U198.17 MDIO
+#set_property -dict {LOC L14  IOSTANDARD LVCMOS18} [get_ports phy_gpio0] ;# U198.39 GPIO_0
+#set_property -dict {LOC M12  IOSTANDARD LVCMOS18} [get_ports phy_gpio1] ;# U198.40 GPIO_1
+#set_property -dict {LOC L15  IOSTANDARD LVCMOS18} [get_ports phy_led0] ;# U198.47 LED_0
+#set_property -dict {LOC W14  IOSTANDARD LVCMOS18} [get_ports phy_led1] ;# U198.46 LED_1
+#set_property -dict {LOC K14  IOSTANDARD LVCMOS18} [get_ports phy_led2] ;# U198.45 LED_2
+
+# QSFP28 Interfaces
+set_property -dict {LOC R45 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC R46 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC M42 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC M43 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC U45 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC U46 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC P42 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC P43 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC N45 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC N46 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC K42 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC K43 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC W45 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC W46 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC T42 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC T43 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
+set_property -dict {LOC V38 } [get_ports qsfp0_mgt_refclk_p] ;# MGTREFCLK0P_131 from Si5340 U23 OUT1
+set_property -dict {LOC V39 } [get_ports qsfp0_mgt_refclk_n] ;# MGTREFCLK0N_131 from Si5340 U23 OUT1
+set_property -dict {LOC A26  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl]
+set_property -dict {LOC C25  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp0_modprsl]
+set_property -dict {LOC B26  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp0_intl]
+set_property -dict {LOC G25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode]
+set_property -dict {LOC B25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_scl]
+set_property -dict {LOC F25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_sda]
+
+# 322.265625 MHz MGT reference clock
+create_clock -period 3.103 -name qsfp0_mgt_refclk [get_ports qsfp0_mgt_refclk_p]
+
+set_false_path -to [get_ports {qsfp0_resetl qsfp0_lpmode}]
+set_output_delay 0 [get_ports {qsfp0_resetl qsfp0_lpmode}]
+set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
+set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
+
+set_false_path -to [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
+set_output_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
+set_false_path -from [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
+set_input_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
+
+set_property -dict {LOC G45 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC G46 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC D42 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC D43 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC J45 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC J46 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC F42 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC F43 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC E45 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC E46 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC B42 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC B43 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC L45 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC L46 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC H42 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC H43 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
+set_property -dict {LOC R40 } [get_ports qsfp1_mgt_refclk_p] ;# MGTREFCLK0P_132 from Si5340 U23 OUT2
+set_property -dict {LOC R41 } [get_ports qsfp1_mgt_refclk_n] ;# MGTREFCLK0N_132 from Si5340 U23 OUT2
+set_property -dict {LOC B27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl]
+set_property -dict {LOC H28  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_modprsl]
+set_property -dict {LOC N24  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_intl]
+set_property -dict {LOC H25  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode]
+set_property -dict {LOC P27  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_scl]
+set_property -dict {LOC R24  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_sda]
+
+# 322.265625 MHz MGT reference clock
+create_clock -period 3.103 -name qsfp1_mgt_refclk [get_ports qsfp1_mgt_refclk_p]
+
+set_false_path -to [get_ports {qsfp1_resetl qsfp1_lpmode}]
+set_output_delay 0 [get_ports {qsfp1_resetl qsfp1_lpmode}]
+set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}]
+set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}]
+
+set_false_path -to [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
+set_output_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
+set_false_path -from [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
+set_input_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
+
+# PCIe Interface
+#set_property -dict {LOC AA4 } [get_ports {pcie_rx_p[0]}]  ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC AA3 } [get_ports {pcie_rx_n[0]}]  ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC Y7  } [get_ports {pcie_tx_p[0]}]  ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC Y6  } [get_ports {pcie_tx_n[0]}]  ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[1]}]  ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[1]}]  ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC AB7 } [get_ports {pcie_tx_p[1]}]  ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC AB6 } [get_ports {pcie_tx_n[1]}]  ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC AC4 } [get_ports {pcie_rx_p[2]}]  ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC AC3 } [get_ports {pcie_rx_n[2]}]  ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[2]}]  ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[2]}]  ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[3]}]  ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[3]}]  ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[3]}]  ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[3]}]  ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[4]}]  ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[4]}]  ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[4]}]  ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[4]}]  ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[5]}]  ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[5]}]  ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[5]}]  ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[5]}]  ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[6]}]  ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[6]}]  ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}]  ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}]  ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[7]}]  ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[7]}]  ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AN5 } [get_ports {pcie_tx_p[7]}]  ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AN4 } [get_ports {pcie_tx_n[7]}]  ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[8]}]  ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[8]}]  ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}]  ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}]  ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[9]}]  ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[9]}]  ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AR5 } [get_ports {pcie_tx_p[9]}]  ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AR4 } [get_ports {pcie_tx_n[9]}]  ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AU5 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AU4 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AW5 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AW4 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC BA5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC BA4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AY2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AY1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC BC5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC BC4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC BB2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC BB1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC BE5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC BE4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AG9 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_226
+#set_property -dict {LOC AG8 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_226
+#set_property -dict {LOC AM17 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset]
+
+# 100 MHz MGT reference clock
+#create_clock -period 10.000 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p]
+
+#set_false_path -from [get_ports {pcie_reset}]
+#set_input_delay 0 [get_ports {pcie_reset}]

src/eth/example/NT200A02/fpga/lib/taxi

@@ -0,0 +1 @@
+../../../../../../

src/eth/example/NT200A02/fpga/pll/Si5340-RevD-NT200-Registers.txt

@@ -0,0 +1,351 @@
+# Si534x/7x/8x/9x Registers Script
+# 
+# Part: Si5340
+# Project File: X:\Projects\taxi-corundum\src\eth\example\NT200A02\fpga\pll\Si5340-RevD-NT200-Project.slabtimeproj
+# Design ID: NT200
+# Includes Pre/Post Download Control Register Writes: Yes
+# Die Revision: B1
+# Creator: ClockBuilder Pro v4.1 [2021-09-22]
+# Created On: 2026-04-04 21:47:23 GMT-07:00
+Address,Data
+# 
+# Start configuration preamble
+0x0B24,0xC0
+0x0B25,0x00
+# Rev D stuck divider fix
+0x0502,0x01
+0x0505,0x03
+0x0957,0x17
+0x0B4E,0x1A
+# End configuration preamble
+# 
+# Delay 300 msec
+#    Delay is worst case time for device to complete any calibration
+#    that is running due to device state change previous to this script
+#    being processed.
+# 
+# Start configuration registers
+0x0006,0x00
+0x0007,0x00
+0x0008,0x00
+0x000B,0x74
+0x0017,0xD0
+0x0018,0xFF
+0x0021,0x0F
+0x0022,0x00
+0x002B,0x02
+0x002C,0x20
+0x002D,0x00
+0x002E,0x00
+0x002F,0x00
+0x0030,0x00
+0x0031,0x00
+0x0032,0x00
+0x0033,0x00
+0x0034,0x00
+0x0035,0x00
+0x0036,0x00
+0x0037,0x00
+0x0038,0x00
+0x0039,0x00
+0x003A,0x00
+0x003B,0x00
+0x003C,0x00
+0x003D,0x00
+0x0041,0x00
+0x0042,0x00
+0x0043,0x00
+0x0044,0x00
+0x009E,0x00
+0x0102,0x01
+0x0112,0x06
+0x0113,0x09
+0x0114,0x3B
+0x0115,0x28
+0x0117,0x06
+0x0118,0x09
+0x0119,0x3B
+0x011A,0x29
+0x0126,0x06
+0x0127,0x09
+0x0128,0x3B
+0x0129,0x29
+0x012B,0x06
+0x012C,0x09
+0x012D,0x3B
+0x012E,0x29
+0x013F,0x00
+0x0140,0x00
+0x0141,0x40
+0x0206,0x00
+0x0208,0x00
+0x0209,0x00
+0x020A,0x00
+0x020B,0x00
+0x020C,0x00
+0x020D,0x00
+0x020E,0x00
+0x020F,0x00
+0x0210,0x00
+0x0211,0x00
+0x0212,0x00
+0x0213,0x00
+0x0214,0x00
+0x0215,0x00
+0x0216,0x00
+0x0217,0x00
+0x0218,0x00
+0x0219,0x00
+0x021A,0x00
+0x021B,0x00
+0x021C,0x00
+0x021D,0x00
+0x021E,0x00
+0x021F,0x00
+0x0220,0x00
+0x0221,0x00
+0x0222,0x00
+0x0223,0x00
+0x0224,0x00
+0x0225,0x00
+0x0226,0x00
+0x0227,0x00
+0x0228,0x00
+0x0229,0x00
+0x022A,0x00
+0x022B,0x00
+0x022C,0x00
+0x022D,0x00
+0x022E,0x00
+0x022F,0x00
+0x0235,0xA0
+0x0236,0x2A
+0x0237,0xCD
+0x0238,0xD8
+0x0239,0xAD
+0x023A,0x00
+0x023B,0x00
+0x023C,0x80
+0x023D,0x96
+0x023E,0x98
+0x0250,0x00
+0x0251,0x00
+0x0252,0x00
+0x0253,0x00
+0x0254,0x00
+0x0255,0x00
+0x025C,0x00
+0x025D,0x00
+0x025E,0x00
+0x025F,0x00
+0x0260,0x00
+0x0261,0x00
+0x026B,0x4E
+0x026C,0x54
+0x026D,0x32
+0x026E,0x30
+0x026F,0x30
+0x0270,0x00
+0x0271,0x00
+0x0272,0x00
+0x0302,0x00
+0x0303,0x00
+0x0304,0x00
+0x0305,0x00
+0x0306,0x0F
+0x0307,0x00
+0x0308,0x00
+0x0309,0x00
+0x030A,0x00
+0x030B,0x80
+0x030C,0x00
+0x030D,0xAA
+0x030E,0xD2
+0x030F,0x8C
+0x0310,0xDD
+0x0311,0x0A
+0x0312,0x00
+0x0313,0xFC
+0x0314,0x8D
+0x0315,0x0E
+0x0316,0x80
+0x0317,0x00
+0x0318,0x00
+0x0319,0x00
+0x031A,0x00
+0x031B,0x00
+0x031C,0x00
+0x031D,0x00
+0x031E,0x00
+0x031F,0x00
+0x0320,0x00
+0x0321,0x00
+0x0322,0x00
+0x0323,0x00
+0x0324,0x00
+0x0325,0x00
+0x0326,0x00
+0x0327,0x00
+0x0328,0x00
+0x0329,0x00
+0x032A,0x00
+0x032B,0x00
+0x032C,0x00
+0x032D,0x00
+0x0338,0x00
+0x0339,0x1F
+0x033B,0x00
+0x033C,0x00
+0x033D,0x00
+0x033E,0x00
+0x033F,0x00
+0x0340,0x00
+0x0341,0x00
+0x0342,0x00
+0x0343,0x00
+0x0344,0x00
+0x0345,0x00
+0x0346,0x00
+0x0347,0x00
+0x0348,0x00
+0x0349,0x00
+0x034A,0x00
+0x034B,0x00
+0x034C,0x00
+0x034D,0x00
+0x034E,0x00
+0x034F,0x00
+0x0350,0x00
+0x0351,0x00
+0x0352,0x00
+0x0359,0x00
+0x035A,0x00
+0x035B,0x00
+0x035C,0x00
+0x035D,0x00
+0x035E,0x00
+0x035F,0x00
+0x0360,0x00
+0x0802,0x00
+0x0803,0x00
+0x0804,0x00
+0x0805,0x00
+0x0806,0x00
+0x0807,0x00
+0x0808,0x00
+0x0809,0x00
+0x080A,0x00
+0x080B,0x00
+0x080C,0x00
+0x080D,0x00
+0x080E,0x00
+0x080F,0x00
+0x0810,0x00
+0x0811,0x00
+0x0812,0x00
+0x0813,0x00
+0x0814,0x00
+0x0815,0x00
+0x0816,0x00
+0x0817,0x00
+0x0818,0x00
+0x0819,0x00
+0x081A,0x00
+0x081B,0x00
+0x081C,0x00
+0x081D,0x00
+0x081E,0x00
+0x081F,0x00
+0x0820,0x00
+0x0821,0x00
+0x0822,0x00
+0x0823,0x00
+0x0824,0x00
+0x0825,0x00
+0x0826,0x00
+0x0827,0x00
+0x0828,0x00
+0x0829,0x00
+0x082A,0x00
+0x082B,0x00
+0x082C,0x00
+0x082D,0x00
+0x082E,0x00
+0x082F,0x00
+0x0830,0x00
+0x0831,0x00
+0x0832,0x00
+0x0833,0x00
+0x0834,0x00
+0x0835,0x00
+0x0836,0x00
+0x0837,0x00
+0x0838,0x00
+0x0839,0x00
+0x083A,0x00
+0x083B,0x00
+0x083C,0x00
+0x083D,0x00
+0x083E,0x00
+0x083F,0x00
+0x0840,0x00
+0x0841,0x00
+0x0842,0x00
+0x0843,0x00
+0x0844,0x00
+0x0845,0x00
+0x0846,0x00
+0x0847,0x00
+0x0848,0x00
+0x0849,0x00
+0x084A,0x00
+0x084B,0x00
+0x084C,0x00
+0x084D,0x00
+0x084E,0x00
+0x084F,0x00
+0x0850,0x00
+0x0851,0x00
+0x0852,0x00
+0x0853,0x00
+0x0854,0x00
+0x0855,0x00
+0x0856,0x00
+0x0857,0x00
+0x0858,0x00
+0x0859,0x00
+0x085A,0x00
+0x085B,0x00
+0x085C,0x00
+0x085D,0x00
+0x085E,0x00
+0x085F,0x00
+0x0860,0x00
+0x0861,0x00
+0x090E,0x02
+0x091C,0x04
+0x0943,0x00
+0x0949,0x00
+0x094A,0x00
+0x094E,0x49
+0x094F,0x02
+0x095E,0x00
+0x0A02,0x00
+0x0A03,0x03
+0x0A04,0x01
+0x0A05,0x03
+0x0A14,0x00
+0x0A1A,0x00
+0x0A20,0x00
+0x0A26,0x00
+0x0B44,0x0F
+0x0B4A,0x0C
+0x0B57,0x0E
+0x0B58,0x01
+# End configuration registers
+# 
+# Start configuration postamble
+0x001C,0x01
+0x0B24,0xC3
+0x0B25,0x02
+# End configuration postamble

src/eth/example/NT200A02/fpga/pll/si5340_i2c_init.py

@@ -0,0 +1,642 @@
+#!/usr/bin/env python
+"""
+Generates an I2C init module for multiple chips
+"""
+
+from jinja2 import Template
+
+
+def si5340_cmds(regs, dev_addr=0x77):
+    cur_page = None
+    cur_addr = None
+
+    cmds = []
+
+    print(f"Reading register list file '{regs}'...")
+
+    with open(regs, "r") as f:
+        for line in f:
+            line = line.strip()
+            if not line or line == "Address,Data":
+                continue
+            if line[0] == '#':
+                cmds.append(f"// {line[1:].strip()}")
+
+                if line.startswith("# Delay"):
+                    cmds.append("cmd_delay(10); // delay 300 ms")
+                    cur_addr = None
+
+                continue
+
+            d = line.split(",")
+            addr = int(d[0], 0)
+            page = (addr >> 8) & 0xff
+            data = int(d[1], 0)
+
+            if page != cur_page:
+                cmds.append(f"cmd_start(7'h{dev_addr:02x});")
+                cmds.append("cmd_wr(8'h01);")
+                cmds.append(f"cmd_wr(8'h{page:02x}); // set page {page:#04x}")
+                cur_page = page
+                cur_addr = None
+
+            if addr != cur_addr:
+                cmds.append(f"cmd_start(7'h{dev_addr:02x});")
+                cmds.append(f"cmd_wr(8'h{addr & 0xff:02x});")
+                cur_addr = addr
+
+            cmds.append(f"cmd_wr(8'h{data:02x}); // write {data:#04x} to {addr:#06x}")
+            cur_addr += 1
+
+    return cmds
+
+
+def mux_cmds(val, dev_addr):
+    cmds = []
+    cmds.append(f"cmd_start(7'h{dev_addr:02x});")
+    cmds.append(f"cmd_wr(8'h{val:02x});")
+    cmds.append("cmd_stop(); // I2C stop")
+    return cmds
+
+
+def main():
+    cmds = []
+
+    cmds.append("// Initial delay")
+    cmds.append("cmd_delay(6); // delay 30 ms")
+
+    cmds.extend(si5340_cmds("Si5340-RevD-NT200-Registers.txt", 0x74))
+
+    generate(cmds, output="si5340_i2c_init.sv")
+
+
+def generate(cmds=None, name=None, output=None):
+    if cmds is None:
+        raise Exception("Command list is required")
+
+    if name is None:
+        name = "si5340_i2c_init"
+
+    if output is None:
+        output = name + ".sv"
+
+    print(f"Generating Si5340 I2C init module {name}...")
+
+    cmds = cmds.copy()
+    cmds.append("cmd_halt(); // end")
+
+    cmd_str = ""
+    cmd_count = 0
+
+    for cmd in cmds:
+        if cmd.startswith('//'):
+            cmd_str += f"    {cmd}\n"
+        else:
+            cmd_str += f"    init_data[{cmd_count}] = {cmd}\n"
+            cmd_count += 1
+
+    t = Template(u"""// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2015-2026 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * {{name}}
+ */
+module {{name}} #
+(
+    parameter logic SIM_SPEEDUP = 1'b0
+)
+(
+    input  wire logic  clk,
+    input  wire logic  rst,
+
+    /*
+     * I2C master interface
+     */
+    taxi_axis_if.src   m_axis_cmd,
+    taxi_axis_if.src   m_axis_tx,
+
+    /*
+     * Status
+     */
+    output wire logic  busy,
+
+    /*
+     * Configuration
+     */
+    input  wire logic  start
+);
+
+/*
+
+Generic module for I2C bus initialization.  Good for use when multiple devices
+on an I2C bus must be initialized on system start without intervention of a
+general-purpose processor.
+
+Copy this file and change init_data and INIT_DATA_LEN as needed.
+
+This module can be used in two modes: simple device initialization, or multiple
+device initialization.  In multiple device mode, the same initialization sequence
+can be performed on multiple different device addresses.
+
+To use single device mode, only use the start write to address and write data commands.
+The module will generate the I2C commands in sequential order.  Terminate the list
+with a 0 entry.
+
+To use the multiple device mode, use the start data and start address block commands
+to set up lists of initialization data and device addresses.  The module enters
+multiple device mode upon seeing a start data block command.  The module stores the
+offset of the start of the data block and then skips ahead until it reaches a start
+address block command.  The module will store the offset to the address block and
+read the first address in the block.  Then it will jump back to the data block
+and execute it, substituting the stored address for each current address write
+command.  Upon reaching the start address block command, the module will read out the
+next address and start again at the top of the data block.  If the module encounters
+a start data block command while looking for an address, then it will store a new data
+offset and then look for a start address block command.  Terminate the list with a 0
+entry.  Normal address commands will operate normally inside a data block.
+
+Commands:
+
+00 0000000 : stop
+00 0000001 : exit multiple device mode
+00 0000011 : start write to current address
+00 0001000 : start address block
+00 0001001 : start data block
+00 001dddd : delay 2**(16+d) cycles
+00 1000001 : send I2C stop
+01 aaaaaaa : start write to address
+1 dddddddd : write 8-bit data
+
+Examples
+
+write 0x11223344 to register 0x0004 on device at 0x50
+
+01 1010000  start write to 0x50
+1 00000000  write address 0x0004
+1 00000100
+1 00010001  write data 0x11223344
+1 00100010
+1 00110011
+1 01000100
+0 00000000  stop
+
+write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53
+
+00 0001001  start data block
+00 0000011  start write to current address
+1 00000000  write address 0x0004
+1 00000100
+1 00010001  write data 0x11223344
+1 00100010
+1 00110011
+1 01000100
+00 0001000  start address block
+01 1010000  address 0x50
+01 1010001  address 0x51
+01 1010010  address 0x52
+01 1010011  address 0x53
+00 0000001  exit multi-dev mode
+00 0000000  stop
+
+*/
+
+// check configuration
+if (m_axis_cmd.DATA_W < 12)
+    $fatal(0, "Command interface width must be at least 12 bits (instance %m)");
+
+if (m_axis_tx.DATA_W != 8)
+    $fatal(0, "Data interface width must be 8 bits (instance %m)");
+
+function [8:0] cmd_start(input [6:0] addr);
+    cmd_start = {2'b01, addr};
+endfunction
+
+function [8:0] cmd_wr(input [7:0] data);
+    cmd_wr = {1'b1, data};
+endfunction
+
+function [8:0] cmd_stop();
+    cmd_stop = {2'b00, 7'b1000001};
+endfunction
+
+function [8:0] cmd_delay(input [3:0] d);
+    cmd_delay = {2'b00, 3'b001, d};
+endfunction
+
+function [8:0] cmd_halt();
+    cmd_halt = 9'd0;
+endfunction
+
+function [8:0] blk_start_data();
+    blk_start_data = {2'b00, 7'b0001001};
+endfunction
+
+function [8:0] blk_start_addr();
+    blk_start_addr = {2'b00, 7'b0001000};
+endfunction
+
+function [8:0] cmd_start_cur();
+    cmd_start_cur = {2'b00, 7'b0000011};
+endfunction
+
+function [8:0] cmd_exit();
+    cmd_exit = {2'b00, 7'b0000001};
+endfunction
+
+// init_data ROM
+localparam INIT_DATA_LEN = {{cmd_count}};
+
+reg [8:0] init_data [INIT_DATA_LEN-1:0];
+
+initial begin
+{{cmd_str-}}
+end
+
+typedef enum logic [2:0] {
+    STATE_IDLE,
+    STATE_RUN,
+    STATE_TABLE_1,
+    STATE_TABLE_2,
+    STATE_TABLE_3
+} state_t;
+
+state_t state_reg = STATE_IDLE, state_next;
+
+localparam AW = $clog2(INIT_DATA_LEN);
+
+logic [8:0] init_data_reg = '0;
+
+logic [AW-1:0] address_reg = '0, address_next;
+logic [AW-1:0] address_ptr_reg = '0, address_ptr_next;
+logic [AW-1:0] data_ptr_reg = '0, data_ptr_next;
+
+logic [6:0] cur_address_reg = '0, cur_address_next;
+
+logic [31:0] delay_counter_reg = '0, delay_counter_next;
+
+logic [6:0] m_axis_cmd_address_reg = '0, m_axis_cmd_address_next;
+logic m_axis_cmd_start_reg = 1'b0, m_axis_cmd_start_next;
+logic m_axis_cmd_write_reg = 1'b0, m_axis_cmd_write_next;
+logic m_axis_cmd_stop_reg = 1'b0, m_axis_cmd_stop_next;
+logic m_axis_cmd_valid_reg = 1'b0, m_axis_cmd_valid_next;
+
+logic [7:0] m_axis_tx_tdata_reg = '0, m_axis_tx_tdata_next;
+logic m_axis_tx_tvalid_reg = 1'b0, m_axis_tx_tvalid_next;
+
+logic start_flag_reg = 1'b0, start_flag_next;
+
+logic busy_reg = 1'b0;
+
+assign m_axis_cmd.tdata[6:0] = m_axis_cmd_address_reg;
+assign m_axis_cmd.tdata[7]   = m_axis_cmd_start_reg;
+assign m_axis_cmd.tdata[8]   = 1'b0; // read
+assign m_axis_cmd.tdata[9]   = m_axis_cmd_write_reg;
+assign m_axis_cmd.tdata[10]  = 1'b0; // write multi
+assign m_axis_cmd.tdata[11]  = m_axis_cmd_stop_reg;
+assign m_axis_cmd.tvalid = m_axis_cmd_valid_reg;
+assign m_axis_cmd.tlast = 1'b1;
+assign m_axis_cmd.tid = '0;
+assign m_axis_cmd.tdest = '0;
+assign m_axis_cmd.tuser = '0;
+
+assign m_axis_tx.tdata = m_axis_tx_tdata_reg;
+assign m_axis_tx.tvalid = m_axis_tx_tvalid_reg;
+assign m_axis_tx.tlast = 1'b1;
+assign m_axis_tx.tid = '0;
+assign m_axis_tx.tdest = '0;
+assign m_axis_tx.tuser = '0;
+
+assign busy = busy_reg;
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    address_next = address_reg;
+    address_ptr_next = address_ptr_reg;
+    data_ptr_next = data_ptr_reg;
+
+    cur_address_next = cur_address_reg;
+
+    delay_counter_next = delay_counter_reg;
+
+    m_axis_cmd_address_next = m_axis_cmd_address_reg;
+    m_axis_cmd_start_next = m_axis_cmd_start_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
+    m_axis_cmd_write_next = m_axis_cmd_write_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
+    m_axis_cmd_stop_next = m_axis_cmd_stop_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
+    m_axis_cmd_valid_next = m_axis_cmd_valid_reg && !m_axis_cmd.tready;
+
+    m_axis_tx_tdata_next = m_axis_tx_tdata_reg;
+    m_axis_tx_tvalid_next = m_axis_tx_tvalid_reg && !m_axis_tx.tready;
+
+    start_flag_next = start_flag_reg;
+
+    if (m_axis_cmd.tvalid || m_axis_tx.tvalid) begin
+        // wait for output registers to clear
+        state_next = state_reg;
+    end else if (delay_counter_reg != 0) begin
+        // delay
+        delay_counter_next = delay_counter_reg - 1;
+        state_next = state_reg;
+    end else begin
+        case (state_reg)
+            STATE_IDLE: begin
+                // wait for start signal
+                if (!start_flag_reg && start) begin
+                    address_next = '0;
+                    start_flag_next = 1'b1;
+                    state_next = STATE_RUN;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_RUN: begin
+                // process commands
+                if (init_data_reg[8] == 1'b1) begin
+                    // write data
+                    m_axis_cmd_write_next = 1'b1;
+                    m_axis_cmd_stop_next = 1'b0;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    m_axis_tx_tdata_next = init_data_reg[7:0];
+                    m_axis_tx_tvalid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg[8:7] == 2'b01) begin
+                    // write address
+                    m_axis_cmd_address_next = init_data_reg[6:0];
+                    m_axis_cmd_start_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg[8:4] == 5'b00001) begin
+                    // delay
+                    if (SIM_SPEEDUP) begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]);
+                    end else begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]+16);
+                    end
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'b001000001) begin
+                    // send stop
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end
+            end
+            STATE_TABLE_1: begin
+                // find address table start
+                if (init_data_reg == 9'b000001000) begin
+                    // address table start
+                    address_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_2;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 1) begin
+                    // exit mode
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end
+            end
+            STATE_TABLE_2: begin
+                // find next address
+                if (init_data_reg[8:7] == 2'b01) begin
+                    // write address command
+                    // store address and move to data table
+                    cur_address_next = init_data_reg[6:0];
+                    address_ptr_next = address_reg + 1;
+                    address_next = data_ptr_reg;
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 9'd1) begin
+                    // exit mode
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_2;
+                end
+            end
+            STATE_TABLE_3: begin
+                // process data table with selected address
+                if (init_data_reg[8] == 1'b1) begin
+                    // write data
+                    m_axis_cmd_write_next = 1'b1;
+                    m_axis_cmd_stop_next = 1'b0;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    m_axis_tx_tdata_next = init_data_reg[7:0];
+                    m_axis_tx_tvalid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg[8:7] == 2'b01) begin
+                    // write address
+                    m_axis_cmd_address_next = init_data_reg[6:0];
+                    m_axis_cmd_start_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b000000011) begin
+                    // write current address
+                    m_axis_cmd_address_next = cur_address_reg;
+                    m_axis_cmd_start_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg[8:4] == 5'b00001) begin
+                    // delay
+                    if (SIM_SPEEDUP) begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]);
+                    end else begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]+16);
+                    end
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b001000001) begin
+                    // send stop
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 9'b000001000) begin
+                    // address table start
+                    address_next = address_ptr_reg;
+                    state_next = STATE_TABLE_2;
+                end else if (init_data_reg == 9'd1) begin
+                    // exit mode
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_3;
+                end
+            end
+            default: begin
+                // invalid state
+                state_next = STATE_IDLE;
+            end
+        endcase
+    end
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+
+    // read init_data ROM
+    init_data_reg <= init_data[address_next];
+
+    address_reg <= address_next;
+    address_ptr_reg <= address_ptr_next;
+    data_ptr_reg <= data_ptr_next;
+
+    cur_address_reg <= cur_address_next;
+
+    delay_counter_reg <= delay_counter_next;
+
+    m_axis_cmd_address_reg <= m_axis_cmd_address_next;
+    m_axis_cmd_start_reg <= m_axis_cmd_start_next;
+    m_axis_cmd_write_reg <= m_axis_cmd_write_next;
+    m_axis_cmd_stop_reg <= m_axis_cmd_stop_next;
+    m_axis_cmd_valid_reg <= m_axis_cmd_valid_next;
+
+    m_axis_tx_tdata_reg <= m_axis_tx_tdata_next;
+    m_axis_tx_tvalid_reg <= m_axis_tx_tvalid_next;
+
+    start_flag_reg <= start && start_flag_next;
+
+    busy_reg <= (state_reg != STATE_IDLE);
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+
+        init_data_reg <= '0;
+
+        address_reg <= '0;
+        address_ptr_reg <= '0;
+        data_ptr_reg <= '0;
+
+        cur_address_reg <= '0;
+
+        delay_counter_reg <= '0;
+
+        m_axis_cmd_valid_reg <= 1'b0;
+
+        m_axis_tx_tvalid_reg <= 1'b0;
+
+        start_flag_reg <= 1'b0;
+
+        busy_reg <= 1'b0;
+    end
+end
+
+endmodule
+
+`resetall
+""")
+
+    print(f"Writing file '{output}'...")
+
+    with open(output, 'w') as f:
+        f.write(t.render(
+            cmd_str=cmd_str,
+            cmd_count=cmd_count,
+            name=name
+        ))
+        f.flush()
+
+    print("Done")
+
+
+if __name__ == "__main__":
+    main()

src/eth/example/NT200A02/fpga/rtl/fpga_core.sv

@@ -0,0 +1,483 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2014-2026 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA core logic
+ */
+module fpga_core #
+(
+    // simulation (set to avoid vendor primitives)
+    parameter logic SIM = 1'b0,
+    // vendor ("GENERIC", "XILINX", "ALTERA")
+    parameter string VENDOR = "XILINX",
+    // device family
+    parameter string FAMILY = "virtexuplus",
+    // Board configuration
+    parameter PORT_CNT = 2,
+    parameter GTY_QUAD_CNT = PORT_CNT,
+    parameter GTY_CNT = GTY_QUAD_CNT*4,
+    parameter GTY_CLK_CNT = GTY_QUAD_CNT,
+    // 10G/25G MAC configuration
+    parameter logic CFG_LOW_LATENCY = 1'b1,
+    parameter logic COMBINED_MAC_PCS = 1'b1,
+    parameter MAC_DATA_W = 64
+
+)
+(
+    /*
+     * Clock: 125 MHz
+     * Synchronous reset
+     */
+    input  wire logic                 clk_125mhz,
+    input  wire logic                 rst_125mhz,
+
+    /*
+     * GPIO
+     */
+    output wire logic [3:0]           led,
+    output wire logic [3:0]           qsfp_led[PORT_CNT],
+    output wire logic                 led_red,
+    output wire logic                 led_green,
+    output wire logic [1:0]           led_sync,
+    output wire logic                 eth_led_yellow,
+    output wire logic                 eth_led_green,
+
+    /*
+     * Ethernet: QSFP28
+     */
+    output wire logic                 eth_gty_tx_p[GTY_CNT],
+    output wire logic                 eth_gty_tx_n[GTY_CNT],
+    input  wire logic                 eth_gty_rx_p[GTY_CNT],
+    input  wire logic                 eth_gty_rx_n[GTY_CNT],
+    input  wire logic                 eth_gty_mgt_refclk_p[GTY_CLK_CNT],
+    input  wire logic                 eth_gty_mgt_refclk_n[GTY_CLK_CNT],
+    output wire logic                 eth_gty_mgt_refclk_out[GTY_CLK_CNT],
+
+    output wire logic [PORT_CNT-1:0]  eth_port_resetl,
+    input  wire logic [PORT_CNT-1:0]  eth_port_modprsl,
+    input  wire logic [PORT_CNT-1:0]  eth_port_intl,
+    output wire logic [PORT_CNT-1:0]  eth_port_lpmode,
+
+    input  wire logic [PORT_CNT-1:0]  eth_port_i2c_scl_i,
+    output wire logic [PORT_CNT-1:0]  eth_port_i2c_scl_o,
+    input  wire logic [PORT_CNT-1:0]  eth_port_i2c_sda_i,
+    output wire logic [PORT_CNT-1:0]  eth_port_i2c_sda_o
+);
+
+assign eth_port_i2c_scl_o = '1;
+assign eth_port_i2c_sda_o = '1;
+
+// QSFP28
+assign eth_port_resetl = '1;
+assign eth_port_lpmode = '0;
+
+wire eth_gty_tx_clk[GTY_CNT];
+wire eth_gty_tx_rst[GTY_CNT];
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_tx[GTY_CNT]();
+taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
+
+wire eth_gty_rx_clk[GTY_CNT];
+wire eth_gty_rx_rst[GTY_CNT];
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_rx[GTY_CNT]();
+
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[GTY_QUAD_CNT]();
+
+wire eth_gty_rx_status[GTY_CNT];
+
+assign qsfp_led[0][0] = eth_gty_rx_status[0];
+assign qsfp_led[0][1] = eth_gty_rx_status[1];
+assign qsfp_led[0][2] = eth_gty_rx_status[2];
+assign qsfp_led[0][3] = eth_gty_rx_status[3];
+assign qsfp_led[1][0] = eth_gty_rx_status[4];
+assign qsfp_led[1][1] = eth_gty_rx_status[5];
+assign qsfp_led[1][2] = eth_gty_rx_status[6];
+assign qsfp_led[1][3] = eth_gty_rx_status[7];
+
+wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood;
+
+wire eth_gty_mgt_refclk[GTY_CLK_CNT];
+wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
+
+wire eth_gty_rst[GTY_CLK_CNT];
+
+for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
+
+    wire eth_gty_mgt_refclk_int;
+
+    if (SIM) begin
+
+        assign eth_gty_mgt_refclk[n] = eth_gty_mgt_refclk_p[n];
+        assign eth_gty_mgt_refclk_int = eth_gty_mgt_refclk_p[n];
+        assign eth_gty_mgt_refclk_bufg[n] = eth_gty_mgt_refclk_int;
+
+    end else begin
+
+        if (FAMILY == "virtexuplus") begin
+
+            IBUFDS_GTE4 ibufds_gte4_eth_gty_mgt_refclk_inst (
+                .I     (eth_gty_mgt_refclk_p[n]),
+                .IB    (eth_gty_mgt_refclk_n[n]),
+                .CEB   (1'b0),
+                .O     (eth_gty_mgt_refclk[n]),
+                .ODIV2 (eth_gty_mgt_refclk_int)
+            );
+
+        end else begin
+
+            IBUFDS_GTE3 ibufds_gte4_eth_gty_mgt_refclk_inst (
+                .I     (eth_gty_mgt_refclk_p[n]),
+                .IB    (eth_gty_mgt_refclk_n[n]),
+                .CEB   (1'b0),
+                .O     (eth_gty_mgt_refclk[n]),
+                .ODIV2 (eth_gty_mgt_refclk_int)
+            );
+
+        end
+
+        BUFG_GT bufg_gt_eth_gty_mgt_refclk_inst (
+            .CE      (&eth_gty_gtpowergood),
+            .CEMASK  (1'b1),
+            .CLR     (1'b0),
+            .CLRMASK (1'b1),
+            .DIV     (3'd0),
+            .I       (eth_gty_mgt_refclk_int),
+            .O       (eth_gty_mgt_refclk_bufg[n])
+        );
+
+    end
+
+    taxi_sync_reset #(
+        .N(4)
+    )
+    qsfp_sync_reset_inst (
+        .clk(eth_gty_mgt_refclk_bufg[n]),
+        .rst(rst_125mhz),
+        .out(eth_gty_rst[n])
+    );
+
+end
+
+localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP0[4] = '{"QSFP0.1", "QSFP0.2", "QSFP0.3",  "QSFP0.4"};
+localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3",  "QSFP1.4"};
+
+for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
+
+    localparam CNT = 4;
+
+    taxi_apb_if #(
+        .ADDR_W(18),
+        .DATA_W(16)
+    )
+    gt_apb_ctrl();
+
+    taxi_eth_mac_25g_us #(
+        .SIM(SIM),
+        .VENDOR(VENDOR),
+        .FAMILY(FAMILY),
+
+        .CNT(4),
+
+        // GT config
+        .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
+
+        // GT type
+        .GT_TYPE("GTY"),
+
+        // GT parameters
+        .GT_TX_POLARITY(n == 0 ? 4'b0101 : 4'b0001),
+        .GT_RX_POLARITY(n == 0 ? 4'b1011 : 4'b0011),
+
+        // MAC/PHY config
+        .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
+        .DATA_W(MAC_DATA_W),
+        .PADDING_EN(1'b1),
+        .DIC_EN(1'b1),
+        .MIN_FRAME_LEN(64),
+        .PTP_TS_EN(1'b0),
+        .PTP_TD_EN(1'b0),
+        .PTP_TS_FMT_TOD(1'b1),
+        .PTP_TS_W(96),
+        .PTP_TD_SDI_PIPELINE(2),
+        .PRBS31_EN(1'b0),
+        .TX_SERDES_PIPELINE(1),
+        .RX_SERDES_PIPELINE(1),
+        .COUNT_125US(125000/6.4),
+        .STAT_EN(0),
+        .STAT_TX_LEVEL(1),
+        .STAT_RX_LEVEL(1),
+        .STAT_ID_BASE(n*CNT*(16+16)),
+        .STAT_UPDATE_PERIOD(1024),
+        .STAT_STR_EN(0),
+        .STAT_PREFIX_STR(n == 0 ? STAT_PREFIX_STR_QSFP0 : STAT_PREFIX_STR_QSFP1)
+    )
+    mac_inst (
+        .xcvr_ctrl_clk(clk_125mhz),
+        .xcvr_ctrl_rst(eth_gty_rst[n]),
+
+        /*
+         * Transceiver control
+         */
+        .s_apb_ctrl(gt_apb_ctrl),
+
+        /*
+         * Common
+         */
+        .xcvr_gtpowergood_out(eth_gty_gtpowergood[n]),
+        .xcvr_gtrefclk00_in(eth_gty_mgt_refclk[n]),
+        .xcvr_qpll0pd_in(1'b0),
+        .xcvr_qpll0reset_in(1'b0),
+        .xcvr_qpll0pcierate_in(3'd0),
+        .xcvr_qpll0lock_out(),
+        .xcvr_qpll0clk_out(),
+        .xcvr_qpll0refclk_out(),
+        .xcvr_gtrefclk01_in(eth_gty_mgt_refclk[n]),
+        .xcvr_qpll1pd_in(1'b0),
+        .xcvr_qpll1reset_in(1'b0),
+        .xcvr_qpll1pcierate_in(3'd0),
+        .xcvr_qpll1lock_out(),
+        .xcvr_qpll1clk_out(),
+        .xcvr_qpll1refclk_out(),
+
+        /*
+         * Serial data
+         */
+        .xcvr_txp(eth_gty_tx_p[n*CNT +: CNT]),
+        .xcvr_txn(eth_gty_tx_n[n*CNT +: CNT]),
+        .xcvr_rxp(eth_gty_rx_p[n*CNT +: CNT]),
+        .xcvr_rxn(eth_gty_rx_n[n*CNT +: CNT]),
+
+        /*
+         * MAC clocks
+         */
+        .rx_clk(eth_gty_rx_clk[n*CNT +: CNT]),
+        .rx_rst_in('{CNT{1'b0}}),
+        .rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]),
+        .tx_clk(eth_gty_tx_clk[n*CNT +: CNT]),
+        .tx_rst_in('{CNT{1'b0}}),
+        .tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]),
+
+        /*
+         * Transmit interface (AXI stream)
+         */
+        .s_axis_tx(eth_gty_axis_tx[n*CNT +: CNT]),
+        .m_axis_tx_cpl(eth_gty_axis_tx_cpl[n*CNT +: CNT]),
+
+        /*
+         * Receive interface (AXI stream)
+         */
+        .m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]),
+
+        /*
+         * PTP clock
+         */
+        .ptp_clk(1'b0),
+        .ptp_rst(1'b0),
+        .ptp_sample_clk(1'b0),
+        .ptp_td_sdi(1'b0),
+        .tx_ptp_ts_in('{CNT{'0}}),
+        .tx_ptp_ts_out(),
+        .tx_ptp_ts_step_out(),
+        .tx_ptp_locked(),
+        .rx_ptp_ts_in('{CNT{'0}}),
+        .rx_ptp_ts_out(),
+        .rx_ptp_ts_step_out(),
+        .rx_ptp_locked(),
+
+        /*
+         * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
+         */
+        .tx_lfc_req('{CNT{1'b0}}),
+        .tx_lfc_resend('{CNT{1'b0}}),
+        .rx_lfc_en('{CNT{1'b0}}),
+        .rx_lfc_req(),
+        .rx_lfc_ack('{CNT{1'b0}}),
+
+        /*
+         * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
+         */
+        .tx_pfc_req('{CNT{'0}}),
+        .tx_pfc_resend('{CNT{1'b0}}),
+        .rx_pfc_en('{CNT{'0}}),
+        .rx_pfc_req(),
+        .rx_pfc_ack('{CNT{'0}}),
+
+        /*
+         * Pause interface
+         */
+        .tx_lfc_pause_en('{CNT{1'b0}}),
+        .tx_pause_req('{CNT{1'b0}}),
+        .tx_pause_ack(),
+
+        /*
+         * Statistics
+         */
+        .stat_clk(clk_125mhz),
+        .stat_rst(rst_125mhz),
+        .m_axis_stat(axis_eth_stat[n]),
+
+        /*
+         * Status
+         */
+        .tx_start_packet(),
+        .stat_tx_byte(),
+        .stat_tx_pkt_len(),
+        .stat_tx_pkt_ucast(),
+        .stat_tx_pkt_mcast(),
+        .stat_tx_pkt_bcast(),
+        .stat_tx_pkt_vlan(),
+        .stat_tx_pkt_good(),
+        .stat_tx_pkt_bad(),
+        .stat_tx_err_oversize(),
+        .stat_tx_err_user(),
+        .stat_tx_err_underflow(),
+        .rx_start_packet(),
+        .rx_error_count(),
+        .rx_block_lock(),
+        .rx_high_ber(),
+        .rx_status(eth_gty_rx_status[n*CNT +: CNT]),
+        .stat_rx_byte(),
+        .stat_rx_pkt_len(),
+        .stat_rx_pkt_fragment(),
+        .stat_rx_pkt_jabber(),
+        .stat_rx_pkt_ucast(),
+        .stat_rx_pkt_mcast(),
+        .stat_rx_pkt_bcast(),
+        .stat_rx_pkt_vlan(),
+        .stat_rx_pkt_good(),
+        .stat_rx_pkt_bad(),
+        .stat_rx_err_oversize(),
+        .stat_rx_err_bad_fcs(),
+        .stat_rx_err_bad_block(),
+        .stat_rx_err_framing(),
+        .stat_rx_err_preamble(),
+        .stat_rx_fifo_drop('{CNT{1'b0}}),
+        .stat_tx_mcf(),
+        .stat_rx_mcf(),
+        .stat_tx_lfc_pkt(),
+        .stat_tx_lfc_xon(),
+        .stat_tx_lfc_xoff(),
+        .stat_tx_lfc_paused(),
+        .stat_tx_pfc_pkt(),
+        .stat_tx_pfc_xon(),
+        .stat_tx_pfc_xoff(),
+        .stat_tx_pfc_paused(),
+        .stat_rx_lfc_pkt(),
+        .stat_rx_lfc_xon(),
+        .stat_rx_lfc_xoff(),
+        .stat_rx_lfc_paused(),
+        .stat_rx_pfc_pkt(),
+        .stat_rx_pfc_xon(),
+        .stat_rx_pfc_xoff(),
+        .stat_rx_pfc_paused(),
+
+        /*
+         * Configuration
+         */
+        .cfg_tx_max_pkt_len('{CNT{16'd9218}}),
+        .cfg_tx_ifg('{CNT{8'd12}}),
+        .cfg_tx_enable('{CNT{1'b1}}),
+        .cfg_rx_max_pkt_len('{CNT{16'd9218}}),
+        .cfg_rx_enable('{CNT{1'b1}}),
+        .cfg_tx_prbs31_enable('{CNT{1'b0}}),
+        .cfg_rx_prbs31_enable('{CNT{1'b0}}),
+        .cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
+        .cfg_mcf_rx_check_eth_dst_mcast('{CNT{1'b1}}),
+        .cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
+        .cfg_mcf_rx_check_eth_dst_ucast('{CNT{1'b0}}),
+        .cfg_mcf_rx_eth_src('{CNT{48'd0}}),
+        .cfg_mcf_rx_check_eth_src('{CNT{1'b0}}),
+        .cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
+        .cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
+        .cfg_mcf_rx_check_opcode_lfc('{CNT{1'b1}}),
+        .cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
+        .cfg_mcf_rx_check_opcode_pfc('{CNT{1'b1}}),
+        .cfg_mcf_rx_forward('{CNT{1'b0}}),
+        .cfg_mcf_rx_enable('{CNT{1'b0}}),
+        .cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
+        .cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
+        .cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
+        .cfg_tx_lfc_opcode('{CNT{16'h0001}}),
+        .cfg_tx_lfc_en('{CNT{1'b0}}),
+        .cfg_tx_lfc_quanta('{CNT{16'hffff}}),
+        .cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
+        .cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
+        .cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
+        .cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
+        .cfg_tx_pfc_opcode('{CNT{16'h0101}}),
+        .cfg_tx_pfc_en('{CNT{1'b0}}),
+        .cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
+        .cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
+        .cfg_rx_lfc_opcode('{CNT{16'h0001}}),
+        .cfg_rx_lfc_en('{CNT{1'b0}}),
+        .cfg_rx_pfc_opcode('{CNT{16'h0101}}),
+        .cfg_rx_pfc_en('{CNT{1'b0}})
+    );
+
+end
+
+for (genvar n = 0; n < GTY_CNT; n = n + 1) begin : qsfp_ch
+
+    taxi_axis_async_fifo #(
+        .DEPTH(16384),
+        .RAM_PIPELINE(2),
+        .FRAME_FIFO(1),
+        .USER_BAD_FRAME_VALUE(1'b1),
+        .USER_BAD_FRAME_MASK(1'b1),
+        .DROP_OVERSIZE_FRAME(1),
+        .DROP_BAD_FRAME(1),
+        .DROP_WHEN_FULL(1)
+    )
+    ch_fifo (
+        /*
+         * AXI4-Stream input (sink)
+         */
+        .s_clk(eth_gty_rx_clk[n]),
+        .s_rst(eth_gty_rx_rst[n]),
+        .s_axis(eth_gty_axis_rx[n]),
+
+        /*
+         * AXI4-Stream output (source)
+         */
+        .m_clk(eth_gty_tx_clk[n]),
+        .m_rst(eth_gty_tx_rst[n]),
+        .m_axis(eth_gty_axis_tx[n]),
+
+        /*
+         * Pause
+         */
+        .s_pause_req(1'b0),
+        .s_pause_ack(),
+        .m_pause_req(1'b0),
+        .m_pause_ack(),
+
+        /*
+         * Status
+         */
+        .s_status_depth(),
+        .s_status_depth_commit(),
+        .s_status_overflow(),
+        .s_status_bad_frame(),
+        .s_status_good_frame(),
+        .m_status_depth(),
+        .m_status_depth_commit(),
+        .m_status_overflow(),
+        .m_status_bad_frame(),
+        .m_status_good_frame()
+    );
+
+end
+
+endmodule
+
+`resetall

src/eth/example/NT200A02/fpga/rtl/fpga_nt200a01.sv

@@ -0,0 +1,412 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2014-2026 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA top-level module
+ */
+module fpga #
+(
+    // simulation (set to avoid vendor primitives)
+    parameter logic SIM = 1'b0,
+    // vendor ("GENERIC", "XILINX", "ALTERA")
+    parameter string VENDOR = "XILINX",
+    // device family
+    parameter string FAMILY = "virtexu",
+    // 10G/25G MAC configuration
+    parameter logic CFG_LOW_LATENCY = 1'b1,
+    parameter logic COMBINED_MAC_PCS = 1'b1,
+    parameter MAC_DATA_W = 64
+)
+(
+    /*
+     * Clock: 50MHz
+     */
+    input  wire logic         clk_50mhz,
+
+    /*
+     * GPIO
+     */
+    output wire logic [3:0]   led,
+    output wire logic [3:0]   qsfp_led[2],
+    output wire logic         led_red,
+    output wire logic         led_green,
+    output wire logic [1:0]   led_sync,
+    output wire logic         eth_led_yellow,
+    output wire logic         eth_led_green,
+
+    /*
+     * I2C
+     */
+    inout  wire logic         si5340_i2c_scl,
+    inout  wire logic         si5340_i2c_sda,
+    input  wire logic         si5340_intr,
+
+    /*
+     * Ethernet: QSFP28
+     */
+    output wire logic         qsfp0_tx_p[4],
+    output wire logic         qsfp0_tx_n[4],
+    input  wire logic         qsfp0_rx_p[4],
+    input  wire logic         qsfp0_rx_n[4],
+    input  wire logic         qsfp0_mgt_refclk_p,
+    input  wire logic         qsfp0_mgt_refclk_n,
+    output wire logic         qsfp0_resetl,
+    input  wire logic         qsfp0_modprsl,
+    input  wire logic         qsfp0_intl,
+    output wire logic         qsfp0_lpmode,
+    inout  wire logic         qsfp0_i2c_scl,
+    inout  wire logic         qsfp0_i2c_sda,
+
+    output wire logic         qsfp1_tx_p[4],
+    output wire logic         qsfp1_tx_n[4],
+    input  wire logic         qsfp1_rx_p[4],
+    input  wire logic         qsfp1_rx_n[4],
+    input  wire logic         qsfp1_mgt_refclk_p,
+    input  wire logic         qsfp1_mgt_refclk_n,
+    output wire logic         qsfp1_resetl,
+    input  wire logic         qsfp1_modprsl,
+    input  wire logic         qsfp1_intl,
+    output wire logic         qsfp1_lpmode,
+    inout  wire logic         qsfp1_i2c_scl,
+    inout  wire logic         qsfp1_i2c_sda
+);
+
+// Clock and reset
+
+wire clk_125mhz_mmcm_out;
+
+// Internal 125 MHz clock
+wire clk_125mhz_int;
+wire rst_125mhz_int;
+
+wire mmcm_rst = 1'b0;
+wire mmcm_locked;
+wire mmcm_clkfb;
+
+// MMCM instance
+MMCME3_BASE #(
+    // 50 MHz input
+    .CLKIN1_PERIOD(20.000),
+    .REF_JITTER1(0.010),
+    // 50 MHz input / 1 = 50 MHz PFD (range 10 MHz to 500 MHz)
+    .DIVCLK_DIVIDE(1),
+    // 50 MHz PFD * 20 = 1000 MHz VCO (range 600 MHz to 1440 MHz)
+    .CLKFBOUT_MULT_F(20),
+    .CLKFBOUT_PHASE(0),
+    // 1000 MHz / 8 = 125 MHz, 0 degrees
+    .CLKOUT0_DIVIDE_F(8),
+    .CLKOUT0_DUTY_CYCLE(0.5),
+    .CLKOUT0_PHASE(0),
+    // Not used
+    .CLKOUT1_DIVIDE(1),
+    .CLKOUT1_DUTY_CYCLE(0.5),
+    .CLKOUT1_PHASE(0),
+    // Not used
+    .CLKOUT2_DIVIDE(1),
+    .CLKOUT2_DUTY_CYCLE(0.5),
+    .CLKOUT2_PHASE(0),
+    // Not used
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.5),
+    .CLKOUT3_PHASE(0),
+    // Not used
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.5),
+    .CLKOUT4_PHASE(0),
+    .CLKOUT4_CASCADE("FALSE"),
+    // Not used
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.5),
+    .CLKOUT5_PHASE(0),
+    // Not used
+    .CLKOUT6_DIVIDE(1),
+    .CLKOUT6_DUTY_CYCLE(0.5),
+    .CLKOUT6_PHASE(0),
+
+    // optimized bandwidth
+    .BANDWIDTH("OPTIMIZED"),
+    // don't wait for lock during startup
+    .STARTUP_WAIT("FALSE")
+)
+clk_mmcm_inst (
+    // 50 MHz input
+    .CLKIN1(clk_50mhz),
+    // direct clkfb feeback
+    .CLKFBIN(mmcm_clkfb),
+    .CLKFBOUT(mmcm_clkfb),
+    .CLKFBOUTB(),
+    // 125 MHz, 0 degrees
+    .CLKOUT0(clk_125mhz_mmcm_out),
+    .CLKOUT0B(),
+    // Not used
+    .CLKOUT1(),
+    .CLKOUT1B(),
+    // Not used
+    .CLKOUT2(),
+    .CLKOUT2B(),
+    // Not used
+    .CLKOUT3(),
+    .CLKOUT3B(),
+    // Not used
+    .CLKOUT4(),
+    // Not used
+    .CLKOUT5(),
+    // Not used
+    .CLKOUT6(),
+    // reset input
+    .RST(mmcm_rst),
+    // don't power down
+    .PWRDWN(1'b0),
+    // locked output
+    .LOCKED(mmcm_locked)
+);
+
+BUFG
+clk_125mhz_bufg_inst (
+    .I(clk_125mhz_mmcm_out),
+    .O(clk_125mhz_int)
+);
+
+taxi_sync_reset #(
+    .N(4)
+)
+sync_reset_125mhz_inst (
+    .clk(clk_125mhz_int),
+    .rst(~mmcm_locked),
+    .out(rst_125mhz_int)
+);
+
+// GPIO
+wire qsfp0_modprsl_int;
+wire qsfp0_intl_int;
+wire qsfp0_i2c_scl_i;
+wire qsfp0_i2c_scl_o;
+wire qsfp0_i2c_sda_i;
+wire qsfp0_i2c_sda_o;
+
+wire qsfp1_modprsl_int;
+wire qsfp1_intl_int;
+wire qsfp1_i2c_scl_i;
+wire qsfp1_i2c_scl_o;
+wire qsfp1_i2c_sda_i;
+wire qsfp1_i2c_sda_o;
+
+logic qsfp0_i2c_scl_o_reg;
+logic qsfp0_i2c_sda_o_reg;
+
+logic qsfp1_i2c_scl_o_reg;
+logic qsfp1_i2c_sda_o_reg;
+
+always_ff @(posedge clk_125mhz_int) begin
+    qsfp0_i2c_scl_o_reg <= qsfp0_i2c_scl_o;
+    qsfp0_i2c_sda_o_reg <= qsfp0_i2c_sda_o;
+
+    qsfp1_i2c_scl_o_reg <= qsfp1_i2c_scl_o;
+    qsfp1_i2c_sda_o_reg <= qsfp1_i2c_sda_o;
+end
+
+taxi_sync_signal #(
+    .WIDTH(8),
+    .N(2)
+)
+sync_signal_inst (
+    .clk(clk_125mhz_int),
+    .in({qsfp0_modprsl, qsfp0_intl, qsfp0_i2c_scl, qsfp0_i2c_sda,
+        qsfp1_modprsl, qsfp1_intl, qsfp1_i2c_scl, qsfp1_i2c_sda}),
+    .out({qsfp0_modprsl_int, qsfp0_intl_int, qsfp0_i2c_scl_i, qsfp0_i2c_sda_i,
+        qsfp1_modprsl_int, qsfp1_intl_int, qsfp1_i2c_scl_i, qsfp1_i2c_sda_i})
+);
+
+assign qsfp0_i2c_scl = qsfp0_i2c_scl_o_reg ? 1'bz : 1'b0;
+assign qsfp0_i2c_sda = qsfp0_i2c_sda_o_reg ? 1'bz : 1'b0;
+
+assign qsfp1_i2c_scl = qsfp1_i2c_scl_o_reg ? 1'bz : 1'b0;
+assign qsfp1_i2c_sda = qsfp1_i2c_sda_o_reg ? 1'bz : 1'b0;
+
+// I2C
+wire si5340_i2c_scl_i;
+wire si5340_i2c_scl_o;
+wire si5340_i2c_sda_i;
+wire si5340_i2c_sda_o;
+
+assign si5340_i2c_scl_i = si5340_i2c_scl;
+assign si5340_i2c_scl = si5340_i2c_scl_o ? 1'bz : 1'b0;
+assign si5340_i2c_sda_i = si5340_i2c_sda;
+assign si5340_i2c_sda = si5340_i2c_sda_o ? 1'bz : 1'b0;
+
+// wire i2c_init_scl_i = i2c_scl_i;
+// wire i2c_init_scl_o;
+// wire i2c_init_sda_i = i2c_sda_i;
+// wire i2c_init_sda_o;
+
+// wire i2c_int_scl_i = i2c_scl_i;
+// wire i2c_int_scl_o;
+// wire i2c_int_sda_i = i2c_sda_i;
+// wire i2c_int_sda_o;
+
+// assign si5340_i2c_scl_o = si5340_i2c_init_scl_o & si5340_i2c_int_scl_o;
+// assign si5340_i2c_sda_o = si5340_i2c_init_sda_o & si5340_i2c_int_sda_o;
+
+// Si5340 init
+taxi_axis_if #(.DATA_W(12)) si5340_i2c_cmd();
+taxi_axis_if #(.DATA_W(8)) si5340_i2c_tx();
+taxi_axis_if #(.DATA_W(8)) si5340_i2c_rx();
+
+assign si5340_i2c_rx.tready = 1'b1;
+
+wire si5340_i2c_busy;
+
+taxi_i2c_master
+si5340_i2c_master_inst (
+    .clk(clk_125mhz_int),
+    .rst(rst_125mhz_int),
+
+    /*
+     * Host interface
+     */
+    .s_axis_cmd(si5340_i2c_cmd),
+    .s_axis_tx(si5340_i2c_tx),
+    .m_axis_rx(si5340_i2c_rx),
+
+    /*
+     * I2C interface
+     */
+    .scl_i(si5340_i2c_scl_i),
+    .scl_o(si5340_i2c_scl_o),
+    .sda_i(si5340_i2c_sda_i),
+    .sda_o(si5340_i2c_sda_o),
+
+    /*
+     * Status
+     */
+    .busy(),
+    .bus_control(),
+    .bus_active(),
+    .missed_ack(),
+
+    /*
+     * Configuration
+     */
+    .prescale(SIM ? 32 : 312),
+    .stop_on_idle(1)
+);
+
+si5340_i2c_init #(
+    .SIM_SPEEDUP(SIM)
+)
+si5340_i2c_init_inst (
+    .clk(clk_125mhz_int),
+    .rst(rst_125mhz_int),
+
+    /*
+     * I2C master interface
+     */
+    .m_axis_cmd(si5340_i2c_cmd),
+    .m_axis_tx(si5340_i2c_tx),
+
+    /*
+     * Status
+     */
+    .busy(si5340_i2c_busy),
+
+    /*
+     * Configuration
+     */
+    .start(1'b1)
+);
+
+localparam PORT_CNT = 2;
+localparam GTY_QUAD_CNT = PORT_CNT;
+localparam GTY_CNT = GTY_QUAD_CNT*4;
+localparam GTY_CLK_CNT = GTY_QUAD_CNT;
+
+wire eth_gty_tx_p[GTY_CNT];
+wire eth_gty_tx_n[GTY_CNT];
+wire eth_gty_rx_p[GTY_CNT];
+wire eth_gty_rx_n[GTY_CNT];
+wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
+wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
+wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
+
+assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4];
+assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4];
+assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p;
+assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n;
+
+assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4];
+assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4];
+assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p;
+assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n;
+
+assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_p;
+assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_n;
+assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_p;
+assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_n;
+
+fpga_core #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .PORT_CNT(PORT_CNT),
+    .GTY_QUAD_CNT(GTY_QUAD_CNT),
+    .GTY_CNT(GTY_CNT),
+    .GTY_CLK_CNT(GTY_CLK_CNT),
+    .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
+    .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
+    .MAC_DATA_W(MAC_DATA_W)
+)
+core_inst (
+    /*
+     * Clock: 125 MHz
+     * Synchronous reset
+     */
+    .clk_125mhz(clk_125mhz_int),
+    .rst_125mhz(rst_125mhz_int),
+
+    /*
+     * GPIO
+     */
+     .led(led),
+     .qsfp_led(qsfp_led),
+     .led_red(led_red),
+     .led_green(led_green),
+     .led_sync(led_sync),
+     .eth_led_yellow(eth_led_yellow),
+     .eth_led_green(eth_led_green),
+
+    /*
+     * Ethernet: QSFP28
+     */
+    .eth_gty_tx_p(eth_gty_tx_p),
+    .eth_gty_tx_n(eth_gty_tx_n),
+    .eth_gty_rx_p(eth_gty_rx_p),
+    .eth_gty_rx_n(eth_gty_rx_n),
+    .eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
+    .eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
+    .eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
+
+    .eth_port_resetl({qsfp1_resetl, qsfp0_resetl}),
+    .eth_port_modprsl({qsfp1_modprsl, qsfp0_modprsl}),
+    .eth_port_intl({qsfp1_intl, qsfp0_intl}),
+    .eth_port_lpmode({qsfp1_lpmode, qsfp0_lpmode}),
+
+    .eth_port_i2c_scl_i({qsfp1_i2c_scl_i, qsfp0_i2c_scl_i}),
+    .eth_port_i2c_scl_o({qsfp1_i2c_scl_o, qsfp0_i2c_scl_o}),
+    .eth_port_i2c_sda_i({qsfp1_i2c_sda_i, qsfp0_i2c_sda_i}),
+    .eth_port_i2c_sda_o({qsfp1_i2c_sda_o, qsfp0_i2c_sda_o})
+);
+
+endmodule
+
+`resetall

src/eth/example/NT200A02/fpga/rtl/fpga_nt200a02.sv

@@ -0,0 +1,412 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2014-2026 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA top-level module
+ */
+module fpga #
+(
+    // simulation (set to avoid vendor primitives)
+    parameter logic SIM = 1'b0,
+    // vendor ("GENERIC", "XILINX", "ALTERA")
+    parameter string VENDOR = "XILINX",
+    // device family
+    parameter string FAMILY = "virtexuplus",
+    // 10G/25G MAC configuration
+    parameter logic CFG_LOW_LATENCY = 1'b1,
+    parameter logic COMBINED_MAC_PCS = 1'b1,
+    parameter MAC_DATA_W = 64
+)
+(
+    /*
+     * Clock: 50MHz
+     */
+    input  wire logic         clk_50mhz,
+
+    /*
+     * GPIO
+     */
+    output wire logic [3:0]   led,
+    output wire logic [3:0]   qsfp_led[2],
+    output wire logic         led_red,
+    output wire logic         led_green,
+    output wire logic [1:0]   led_sync,
+    output wire logic         eth_led_yellow,
+    output wire logic         eth_led_green,
+
+    /*
+     * I2C
+     */
+    inout  wire logic         si5340_i2c_scl,
+    inout  wire logic         si5340_i2c_sda,
+    input  wire logic         si5340_intr,
+
+    /*
+     * Ethernet: QSFP28
+     */
+    output wire logic         qsfp0_tx_p[4],
+    output wire logic         qsfp0_tx_n[4],
+    input  wire logic         qsfp0_rx_p[4],
+    input  wire logic         qsfp0_rx_n[4],
+    input  wire logic         qsfp0_mgt_refclk_p,
+    input  wire logic         qsfp0_mgt_refclk_n,
+    output wire logic         qsfp0_resetl,
+    input  wire logic         qsfp0_modprsl,
+    input  wire logic         qsfp0_intl,
+    output wire logic         qsfp0_lpmode,
+    inout  wire logic         qsfp0_i2c_scl,
+    inout  wire logic         qsfp0_i2c_sda,
+
+    output wire logic         qsfp1_tx_p[4],
+    output wire logic         qsfp1_tx_n[4],
+    input  wire logic         qsfp1_rx_p[4],
+    input  wire logic         qsfp1_rx_n[4],
+    input  wire logic         qsfp1_mgt_refclk_p,
+    input  wire logic         qsfp1_mgt_refclk_n,
+    output wire logic         qsfp1_resetl,
+    input  wire logic         qsfp1_modprsl,
+    input  wire logic         qsfp1_intl,
+    output wire logic         qsfp1_lpmode,
+    inout  wire logic         qsfp1_i2c_scl,
+    inout  wire logic         qsfp1_i2c_sda
+);
+
+// Clock and reset
+
+wire clk_125mhz_mmcm_out;
+
+// Internal 125 MHz clock
+wire clk_125mhz_int;
+wire rst_125mhz_int;
+
+wire mmcm_rst = 1'b0;
+wire mmcm_locked;
+wire mmcm_clkfb;
+
+// MMCM instance
+MMCME4_BASE #(
+    // 50 MHz input
+    .CLKIN1_PERIOD(20.000),
+    .REF_JITTER1(0.010),
+    // 50 MHz input / 1 = 50 MHz PFD (range 10 MHz to 500 MHz)
+    .DIVCLK_DIVIDE(1),
+    // 50 MHz PFD * 20 = 1000 MHz VCO (range 800 MHz to 1600 MHz)
+    .CLKFBOUT_MULT_F(20),
+    .CLKFBOUT_PHASE(0),
+    // 1000 MHz / 8 = 125 MHz, 0 degrees
+    .CLKOUT0_DIVIDE_F(8),
+    .CLKOUT0_DUTY_CYCLE(0.5),
+    .CLKOUT0_PHASE(0),
+    // Not used
+    .CLKOUT1_DIVIDE(1),
+    .CLKOUT1_DUTY_CYCLE(0.5),
+    .CLKOUT1_PHASE(0),
+    // Not used
+    .CLKOUT2_DIVIDE(1),
+    .CLKOUT2_DUTY_CYCLE(0.5),
+    .CLKOUT2_PHASE(0),
+    // Not used
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.5),
+    .CLKOUT3_PHASE(0),
+    // Not used
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.5),
+    .CLKOUT4_PHASE(0),
+    .CLKOUT4_CASCADE("FALSE"),
+    // Not used
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.5),
+    .CLKOUT5_PHASE(0),
+    // Not used
+    .CLKOUT6_DIVIDE(1),
+    .CLKOUT6_DUTY_CYCLE(0.5),
+    .CLKOUT6_PHASE(0),
+
+    // optimized bandwidth
+    .BANDWIDTH("OPTIMIZED"),
+    // don't wait for lock during startup
+    .STARTUP_WAIT("FALSE")
+)
+clk_mmcm_inst (
+    // 50 MHz input
+    .CLKIN1(clk_50mhz),
+    // direct clkfb feeback
+    .CLKFBIN(mmcm_clkfb),
+    .CLKFBOUT(mmcm_clkfb),
+    .CLKFBOUTB(),
+    // 125 MHz, 0 degrees
+    .CLKOUT0(clk_125mhz_mmcm_out),
+    .CLKOUT0B(),
+    // Not used
+    .CLKOUT1(),
+    .CLKOUT1B(),
+    // Not used
+    .CLKOUT2(),
+    .CLKOUT2B(),
+    // Not used
+    .CLKOUT3(),
+    .CLKOUT3B(),
+    // Not used
+    .CLKOUT4(),
+    // Not used
+    .CLKOUT5(),
+    // Not used
+    .CLKOUT6(),
+    // reset input
+    .RST(mmcm_rst),
+    // don't power down
+    .PWRDWN(1'b0),
+    // locked output
+    .LOCKED(mmcm_locked)
+);
+
+BUFG
+clk_125mhz_bufg_inst (
+    .I(clk_125mhz_mmcm_out),
+    .O(clk_125mhz_int)
+);
+
+taxi_sync_reset #(
+    .N(4)
+)
+sync_reset_125mhz_inst (
+    .clk(clk_125mhz_int),
+    .rst(~mmcm_locked),
+    .out(rst_125mhz_int)
+);
+
+// GPIO
+wire qsfp0_modprsl_int;
+wire qsfp0_intl_int;
+wire qsfp0_i2c_scl_i;
+wire qsfp0_i2c_scl_o;
+wire qsfp0_i2c_sda_i;
+wire qsfp0_i2c_sda_o;
+
+wire qsfp1_modprsl_int;
+wire qsfp1_intl_int;
+wire qsfp1_i2c_scl_i;
+wire qsfp1_i2c_scl_o;
+wire qsfp1_i2c_sda_i;
+wire qsfp1_i2c_sda_o;
+
+logic qsfp0_i2c_scl_o_reg;
+logic qsfp0_i2c_sda_o_reg;
+
+logic qsfp1_i2c_scl_o_reg;
+logic qsfp1_i2c_sda_o_reg;
+
+always_ff @(posedge clk_125mhz_int) begin
+    qsfp0_i2c_scl_o_reg <= qsfp0_i2c_scl_o;
+    qsfp0_i2c_sda_o_reg <= qsfp0_i2c_sda_o;
+
+    qsfp1_i2c_scl_o_reg <= qsfp1_i2c_scl_o;
+    qsfp1_i2c_sda_o_reg <= qsfp1_i2c_sda_o;
+end
+
+taxi_sync_signal #(
+    .WIDTH(8),
+    .N(2)
+)
+sync_signal_inst (
+    .clk(clk_125mhz_int),
+    .in({qsfp0_modprsl, qsfp0_intl, qsfp0_i2c_scl, qsfp0_i2c_sda,
+        qsfp1_modprsl, qsfp1_intl, qsfp1_i2c_scl, qsfp1_i2c_sda}),
+    .out({qsfp0_modprsl_int, qsfp0_intl_int, qsfp0_i2c_scl_i, qsfp0_i2c_sda_i,
+        qsfp1_modprsl_int, qsfp1_intl_int, qsfp1_i2c_scl_i, qsfp1_i2c_sda_i})
+);
+
+assign qsfp0_i2c_scl = qsfp0_i2c_scl_o_reg ? 1'bz : 1'b0;
+assign qsfp0_i2c_sda = qsfp0_i2c_sda_o_reg ? 1'bz : 1'b0;
+
+assign qsfp1_i2c_scl = qsfp1_i2c_scl_o_reg ? 1'bz : 1'b0;
+assign qsfp1_i2c_sda = qsfp1_i2c_sda_o_reg ? 1'bz : 1'b0;
+
+// I2C
+wire si5340_i2c_scl_i;
+wire si5340_i2c_scl_o;
+wire si5340_i2c_sda_i;
+wire si5340_i2c_sda_o;
+
+assign si5340_i2c_scl_i = si5340_i2c_scl;
+assign si5340_i2c_scl = si5340_i2c_scl_o ? 1'bz : 1'b0;
+assign si5340_i2c_sda_i = si5340_i2c_sda;
+assign si5340_i2c_sda = si5340_i2c_sda_o ? 1'bz : 1'b0;
+
+// wire i2c_init_scl_i = i2c_scl_i;
+// wire i2c_init_scl_o;
+// wire i2c_init_sda_i = i2c_sda_i;
+// wire i2c_init_sda_o;
+
+// wire i2c_int_scl_i = i2c_scl_i;
+// wire i2c_int_scl_o;
+// wire i2c_int_sda_i = i2c_sda_i;
+// wire i2c_int_sda_o;
+
+// assign si5340_i2c_scl_o = si5340_i2c_init_scl_o & si5340_i2c_int_scl_o;
+// assign si5340_i2c_sda_o = si5340_i2c_init_sda_o & si5340_i2c_int_sda_o;
+
+// Si5340 init
+taxi_axis_if #(.DATA_W(12)) si5340_i2c_cmd();
+taxi_axis_if #(.DATA_W(8)) si5340_i2c_tx();
+taxi_axis_if #(.DATA_W(8)) si5340_i2c_rx();
+
+assign si5340_i2c_rx.tready = 1'b1;
+
+wire si5340_i2c_busy;
+
+taxi_i2c_master
+si5340_i2c_master_inst (
+    .clk(clk_125mhz_int),
+    .rst(rst_125mhz_int),
+
+    /*
+     * Host interface
+     */
+    .s_axis_cmd(si5340_i2c_cmd),
+    .s_axis_tx(si5340_i2c_tx),
+    .m_axis_rx(si5340_i2c_rx),
+
+    /*
+     * I2C interface
+     */
+    .scl_i(si5340_i2c_scl_i),
+    .scl_o(si5340_i2c_scl_o),
+    .sda_i(si5340_i2c_sda_i),
+    .sda_o(si5340_i2c_sda_o),
+
+    /*
+     * Status
+     */
+    .busy(),
+    .bus_control(),
+    .bus_active(),
+    .missed_ack(),
+
+    /*
+     * Configuration
+     */
+    .prescale(SIM ? 32 : 312),
+    .stop_on_idle(1)
+);
+
+si5340_i2c_init #(
+    .SIM_SPEEDUP(SIM)
+)
+si5340_i2c_init_inst (
+    .clk(clk_125mhz_int),
+    .rst(rst_125mhz_int),
+
+    /*
+     * I2C master interface
+     */
+    .m_axis_cmd(si5340_i2c_cmd),
+    .m_axis_tx(si5340_i2c_tx),
+
+    /*
+     * Status
+     */
+    .busy(si5340_i2c_busy),
+
+    /*
+     * Configuration
+     */
+    .start(1'b1)
+);
+
+localparam PORT_CNT = 2;
+localparam GTY_QUAD_CNT = PORT_CNT;
+localparam GTY_CNT = GTY_QUAD_CNT*4;
+localparam GTY_CLK_CNT = GTY_QUAD_CNT;
+
+wire eth_gty_tx_p[GTY_CNT];
+wire eth_gty_tx_n[GTY_CNT];
+wire eth_gty_rx_p[GTY_CNT];
+wire eth_gty_rx_n[GTY_CNT];
+wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
+wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
+wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
+
+assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4];
+assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4];
+assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p;
+assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n;
+
+assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4];
+assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4];
+assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p;
+assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n;
+
+assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_p;
+assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_n;
+assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_p;
+assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_n;
+
+fpga_core #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .PORT_CNT(PORT_CNT),
+    .GTY_QUAD_CNT(GTY_QUAD_CNT),
+    .GTY_CNT(GTY_CNT),
+    .GTY_CLK_CNT(GTY_CLK_CNT),
+    .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
+    .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
+    .MAC_DATA_W(MAC_DATA_W)
+)
+core_inst (
+    /*
+     * Clock: 125 MHz
+     * Synchronous reset
+     */
+    .clk_125mhz(clk_125mhz_int),
+    .rst_125mhz(rst_125mhz_int),
+
+    /*
+     * GPIO
+     */
+     .led(led),
+     .qsfp_led(qsfp_led),
+     .led_red(led_red),
+     .led_green(led_green),
+     .led_sync(led_sync),
+     .eth_led_yellow(eth_led_yellow),
+     .eth_led_green(eth_led_green),
+
+    /*
+     * Ethernet: QSFP28
+     */
+    .eth_gty_tx_p(eth_gty_tx_p),
+    .eth_gty_tx_n(eth_gty_tx_n),
+    .eth_gty_rx_p(eth_gty_rx_p),
+    .eth_gty_rx_n(eth_gty_rx_n),
+    .eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
+    .eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
+    .eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
+
+    .eth_port_resetl({qsfp1_resetl, qsfp0_resetl}),
+    .eth_port_modprsl({qsfp1_modprsl, qsfp0_modprsl}),
+    .eth_port_intl({qsfp1_intl, qsfp0_intl}),
+    .eth_port_lpmode({qsfp1_lpmode, qsfp0_lpmode}),
+
+    .eth_port_i2c_scl_i({qsfp1_i2c_scl_i, qsfp0_i2c_scl_i}),
+    .eth_port_i2c_scl_o({qsfp1_i2c_scl_o, qsfp0_i2c_scl_o}),
+    .eth_port_i2c_sda_i({qsfp1_i2c_sda_i, qsfp0_i2c_sda_i}),
+    .eth_port_i2c_sda_o({qsfp1_i2c_sda_o, qsfp0_i2c_sda_o})
+);
+
+endmodule
+
+`resetall

src/eth/example/NT200A02/fpga/tb/fpga_core/Makefile

@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2020-2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = fpga_core
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = $(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_SIM := "1'b1"
+export PARAM_VENDOR := "\"XILINX\""
+export PARAM_FAMILY := "\"virtexuplus\""
+export PARAM_PORT_CNT := 2
+export PARAM_GTY_QUAD_CNT := $(PARAM_PORT_CNT)
+export PARAM_GTY_CNT := $(shell echo $$(( 4 * $(PARAM_GTY_QUAD_CNT) )))
+export PARAM_GTY_CLK_CNT := $(PARAM_GTY_QUAD_CNT)
+export PARAM_CFG_LOW_LATENCY := "1'b1"
+export PARAM_COMBINED_MAC_PCS := "1'b1"
+export PARAM_MAC_DATA_W := "64"
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/example/NT200A02/fpga/tb/fpga_core/baser.py

@@ -0,0 +1 @@
+../../lib/taxi/src/eth/tb/baser.py

src/eth/example/NT200A02/fpga/tb/fpga_core/test_fpga_core.py

@@ -0,0 +1,244 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: MIT
+"""
+
+Copyright (c) 2020-2026 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import sys
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Combine
+
+from cocotbext.eth import XgmiiFrame
+
+try:
+    from baser import BaseRSerdesSource, BaseRSerdesSink
+except ImportError:
+    # attempt import from current directory
+    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
+    try:
+        from baser import BaseRSerdesSource, BaseRSerdesSink
+    finally:
+        del sys.path[0]
+
+
+class TB:
+    def __init__(self, dut, speed=1000e6):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
+
+        self.qsfp_sources = []
+        self.qsfp_sinks = []
+
+        for clk in dut.eth_gty_mgt_refclk_p:
+            cocotb.start_soon(Clock(clk, 3.102, units="ns").start())
+
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]):
+            gt_inst = ch.ch_inst.gt.gt_inst
+
+            if ch.ch_inst.DATA_W.value == 64:
+                if ch.ch_inst.CFG_LOW_LATENCY.value:
+                    clk = 2.482
+                    gbx_cfg = (66, [64, 65])
+                else:
+                    clk = 2.56
+                    gbx_cfg = None
+            else:
+                if ch.ch_inst.CFG_LOW_LATENCY.value:
+                    clk = 3.102
+                    gbx_cfg = (66, [64, 65])
+                else:
+                    clk = 3.2
+                    gbx_cfg = None
+
+            cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())
+            cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start())
+
+            self.qsfp_sources.append(BaseRSerdesSource(
+                data=gt_inst.serdes_rx_data,
+                data_valid=gt_inst.serdes_rx_data_valid,
+                hdr=gt_inst.serdes_rx_hdr,
+                hdr_valid=gt_inst.serdes_rx_hdr_valid,
+                clock=gt_inst.rx_clk,
+                slip=gt_inst.serdes_rx_bitslip,
+                reverse=True,
+                gbx_cfg=gbx_cfg
+            ))
+            self.qsfp_sinks.append(BaseRSerdesSink(
+                data=gt_inst.serdes_tx_data,
+                data_valid=gt_inst.serdes_tx_data_valid,
+                hdr=gt_inst.serdes_tx_hdr,
+                hdr_valid=gt_inst.serdes_tx_hdr_valid,
+                gbx_sync=gt_inst.serdes_tx_gbx_sync,
+                clock=gt_inst.tx_clk,
+                reverse=True,
+                gbx_cfg=gbx_cfg
+            ))
+
+    async def init(self):
+
+        self.dut.rst_125mhz.setimmediatevalue(0)
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk_125mhz)
+
+        self.dut.rst_125mhz.value = 1
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk_125mhz)
+
+        self.dut.rst_125mhz.value = 0
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk_125mhz)
+
+
+async def mac_test(tb, source, sink):
+    tb.log.info("Test MAC")
+
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk_125mhz)
+
+    sink.clear()
+
+    tb.log.info("Multiple small packets")
+
+    count = 64
+
+    pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
+
+    for p in pkts:
+        await source.send(XgmiiFrame.from_payload(p))
+
+    for k in range(count):
+        rx_frame = await sink.recv()
+
+        tb.log.info("RX frame: %s", rx_frame)
+
+        assert rx_frame.get_payload() == pkts[k]
+        assert rx_frame.check_fcs()
+
+    tb.log.info("Multiple large packets")
+
+    count = 32
+
+    pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
+
+    for p in pkts:
+        await source.send(XgmiiFrame.from_payload(p))
+
+    for k in range(count):
+        rx_frame = await sink.recv()
+
+        tb.log.info("RX frame: %s", rx_frame)
+
+        assert rx_frame.get_payload() == pkts[k]
+        assert rx_frame.check_fcs()
+
+    tb.log.info("MAC test done")
+
+
+@cocotb.test()
+async def run_test(dut):
+
+    tb = TB(dut)
+
+    await tb.init()
+
+    tests = []
+
+    tb.log.info("Start BASE-T MAC loopback test")
+
+    for k in range(len(tb.qsfp_sources)):
+        tb.log.info("Start QSFP %d MAC loopback test", k)
+
+        tests.append(cocotb.start_soon(mac_test(tb, tb.qsfp_sources[k], tb.qsfp_sinks[k])))
+
+    await Combine(*tests)
+
+    await RisingEdge(dut.clk_125mhz)
+    await RisingEdge(dut.clk_125mhz)
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("mac_data_w", [32, 64])
+def test_fpga_core(request, mac_data_w):
+    dut = "fpga_core"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"),
+        os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"),
+        os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
+        os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['SIM'] = "1'b1"
+    parameters['VENDOR'] = "\"XILINX\""
+    parameters['FAMILY'] = "\"virtexuplus\""
+    parameters['PORT_CNT'] = 2
+    parameters['GTY_QUAD_CNT'] = parameters['PORT_CNT']
+    parameters['GTY_CNT'] = parameters['GTY_QUAD_CNT']*4
+    parameters['GTY_CLK_CNT'] = parameters['GTY_QUAD_CNT']
+    parameters['CFG_LOW_LATENCY'] = "1'b1"
+    parameters['COMBINED_MAC_PCS'] = "1'b1"
+    parameters['MAC_DATA_W'] = mac_data_w
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/example/NT40E3/fpga/README.md

@@ -0,0 +1,49 @@
+# Taxi Example Design for NT20E3/NT40E3
+
+## Introduction
+
+This example design targets the Napatech NT20E3/NT40E3 FPGA board.
+
+The design places looped-back MACs on the SFP+ cages.
+
+*  SFP+ cages
+    *  Looped-back 10GBASE-R MACs via GTH transceivers
+
+## Board details
+
+*  FPGA: XC7VX330T-2FFG1157
+
+## Licensing
+
+*  Toolchain
+    *  Vivado Enterprise (requires license)
+*  IP
+    *  No licensed vendor IP or 3rd party IP
+
+## How to build
+
+Run `make` in the appropriate `fpga*` subdirectory to build the bitstream.  Ensure that the Xilinx Vivado toolchain components are in PATH.
+
+## How to test
+
+Run `make program` to program the board with Vivado.
+
+To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback.  Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
+
+## JTAG pinout
+
+Napatech boards use a non-standard connector for JTAG.  There are three debug connectors, and one of them carries the JTAG signals for the FPGA.
+
+        J18             J24
+        FPGA            AVR
+    TDI 7 8 GND     TDI 7 8 GND
+    TMS 5 6 HALT    TMS 5 6
+    TDO 3 4 Vref    TDO 3 4 Vref
+    TCK 1 2 GND     TCK 1 2 GND
+
+            J20
+        GND 2 1
+            4 3
+            6 5
+
+Note: J18.6 HALT must be driven low to access the JTAG chain.  So, either tie to to ground, or connect it to the HALT signal on DLC9/DLC10 cables.

src/eth/example/NT40E3/fpga/common/vivado.mk

@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: MIT
+###################################################################
+#
+# Xilinx Vivado FPGA Makefile
+#
+# Copyright (c) 2016-2025 Alex Forencich
+#
+###################################################################
+#
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - list of source files
+# INC_FILES - list of include files
+# XDC_FILES - list of timing constraint files
+# XCI_FILES - list of IP XCI files
+# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
+# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
+#
+# Note: both SYN_FILES and INC_FILES support file list files.  File list
+# files are files with a .f extension that contain a list of additional
+# files to include, one path relative to the .f file location per line.
+# The .f files are processed recursively, and then the complete file list
+# is de-duplicated, with later files in the list taking precedence.
+#
+# Example:
+#
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+#
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include $(CONFIG)
+
+FPGA_TOP ?= fpga
+PROJECT ?= $(FPGA_TOP)
+XDC_FILES ?= $(PROJECT).xdc
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
+INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
+
+###################################################################
+# Main Targets
+#
+# all: build everything (fpga)
+# fpga: build FPGA config
+# vivado: open project in Vivado
+# tmpclean: remove intermediate files
+# clean: remove output files and project files
+# distclean: remove archived output files
+###################################################################
+
+all: fpga
+
+fpga: $(PROJECT).bit
+
+vivado: $(PROJECT).xpr
+	vivado $(PROJECT).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+	-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+
+# create fresh project if Makefile or IP files have changed
+create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
+	echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
+	for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+# source config TCL scripts if any source file has changed
+update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
+	echo "open_project -quiet $(PROJECT).xpr" > $@
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+$(PROJECT).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
+	echo "open_project $(PROJECT).xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
+	echo "open_project $(PROJECT).xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "open_run impl_1" >> run_impl.tcl
+	echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
+	echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# output files (including potentially bit, bin, ltx, and xsa)
+$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
+	echo "open_project $(PROJECT).xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
+	echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
+	echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
+	if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi

src/eth/example/NT40E3/fpga/fpga.xdc

@@ -0,0 +1,256 @@
+# XDC constraints for the Napatech NT40E3
+# part: xc7vx330tffg1157-2
+
+# General configuration
+set_property CFGBVS GND                                [current_design]
+set_property CONFIG_VOLTAGE 1.8                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+# set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE    [current_design]
+set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DIV-1  [current_design]
+# set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
+# set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
+
+# 80 MHz EMC clock
+set_property -dict {LOC AP33 IOSTANDARD LVCMOS18} [get_ports clk_80mhz]
+create_clock -period 12.5 -name clk_80mhz [get_ports clk_80mhz]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_80mhz_ibufg]
+
+# 233.33 MHz DDR3 MIG clock
+#set_property -dict {LOC J30 IOSTANDARD LVDS} [get_ports clk_ddr_233mhz_p]
+#set_property -dict {LOC J31 IOSTANDARD LVDS} [get_ports clk_ddr_233mhz_n]
+#create_clock -period 4.285 -name clk_ddr_233mhz [get_ports clk_ddr_233mhz_p]
+
+# LEDs
+set_property -dict {LOC AC12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_led[0]}]
+set_property -dict {LOC AE9  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_led[1]}]
+set_property -dict {LOC AE8  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_led[2]}]
+set_property -dict {LOC AC10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_led[3]}]
+set_property -dict {LOC AD30 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[0]}]
+set_property -dict {LOC AD31 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[1]}]
+set_property -dict {LOC AG30 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[2]}]
+set_property -dict {LOC AH30 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[3]}]
+set_property -dict {LOC AB27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_red}]
+set_property -dict {LOC AB28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_green}]
+set_property -dict {LOC AJ26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_sync[0]}]
+set_property -dict {LOC AP29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_sync[1]}]
+
+set_false_path -to [get_ports {sfp_led[*] led[*] led_red led_green led_sync[*]}]
+set_output_delay 0 [get_ports {sfp_led[*] led[*] led_red led_green led_sync[*]}]
+
+# Time sync
+#set_property -dict {LOC AB31 IOSTANDARD LVCMOS18} [get_ports {sync_ext_in}]
+#set_property -dict {LOC AB32 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {sync_ext_out}]
+#set_property -dict {LOC AB30 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_ext_in_en}]
+#set_property -dict {LOC AA30 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_ext_out_en[0]}]
+#set_property -dict {LOC W32  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_ext_out_en[1]}]
+#set_property -dict {LOC Y32  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_ext_term[0]}]
+#set_property -dict {LOC AA31 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_ext_term[1]}]
+#set_property -dict {LOC V30  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_ext_vsel[0]}]
+#set_property -dict {LOC U30  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_ext_vsel[1]}]
+
+#set_property -dict {LOC AK26 IOSTANDARD LVCMOS18} [get_ports {sync_int_1_in}]
+#set_property -dict {LOC AK27 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {sync_int_1_out}]
+#set_property -dict {LOC AH24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_int_1_in_en}]
+#set_property -dict {LOC AH25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_int_1_out_en[0]}]
+#set_property -dict {LOC AJ25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_int_1_out_en[1]}]
+#set_property -dict {LOC AL25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_int_1_term[0]}]
+#set_property -dict {LOC AL26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_int_1_term[1]}]
+#set_property -dict {LOC AG25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_int_1_vsel[0]}]
+#set_property -dict {LOC AJ27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_int_1_vsel[1]}]
+
+#set_property -dict {LOC AM27 IOSTANDARD LVCMOS18} [get_ports {sync_int_2_in}]
+#set_property -dict {LOC AN29 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {sync_int_2_out}]
+#set_property -dict {LOC AN28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_int_2_in_en}]
+#set_property -dict {LOC AM28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_int_2_out_en[0]}]
+#set_property -dict {LOC AP25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_int_2_out_en[1]}]
+#set_property -dict {LOC AP26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_int_2_term[0]}]
+#set_property -dict {LOC AN27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_int_2_term[1]}]
+#set_property -dict {LOC AN25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_int_2_vsel[0]}]
+#set_property -dict {LOC AM25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sync_int_2_vsel[1]}]
+
+#set_false_path -from [get_ports {sync_ext_in}]
+#set_input_delay 0 [get_ports {sync_ext_in}]
+#set_false_path -to [get_ports {sync_ext_out sync_ext_in_en sync_ext_out_en[*] sync_ext_term[*] sync_ext_vsel[*]}]
+#set_output_delay 0 [get_ports {sync_ext_out sync_ext_in_en sync_ext_out_en[*] sync_ext_term[*] sync_ext_vsel[*]}]
+
+#set_false_path -from [get_ports {sync_int_1_in}]
+#set_input_delay 0 [get_ports {sync_int_1_in}]
+#set_false_path -to [get_ports {sync_int_1_out sync_int_1_in_en sync_int_1_out_en[*] sync_int_1_term[*] sync_int_1_vsel[*]}]
+#set_output_delay 0 [get_ports {sync_int_1_out sync_int_1_in_en sync_int_1_out_en[*] sync_int_1_term[*] sync_int_1_vsel[*]}]
+
+#set_false_path -from [get_ports {sync_int_2_in}]
+#set_input_delay 0 [get_ports {sync_int_2_in}]
+#set_false_path -to [get_ports {sync_int_2_out sync_int_2_in_en sync_int_2_out_en[*] sync_int_2_term[*] sync_int_2_vsel[*]}]
+#set_output_delay 0 [get_ports {sync_int_2_out sync_int_2_in_en sync_int_2_out_en[*] sync_int_2_term[*] sync_int_2_vsel[*]}]
+
+# AVR BMC U2
+#set_property -dict {LOC AC23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pc4] ;# U2.J7 PC4
+#set_property -dict {LOC AD24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pc5] ;# U2.H7 PC5
+#set_property -dict {LOC AC24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pc6] ;# U2.G7 PC6
+#set_property -dict {LOC AD25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pc7] ;# U2.J8 PC7
+
+#set_property -dict {LOC AC25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pd4] ;# U2.H9 PD4
+#set_property -dict {LOC AE24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pd5] ;# U2.H8 PD5
+#set_property -dict {LOC AE23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pd6] ;# U2.G9 PD6
+#set_property -dict {LOC AF26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pd7] ;# U2.G8 PD7
+
+#set_property -dict {LOC AF29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pj0] ;# U2.C5 PJ0
+#set_property -dict {LOC AC28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pj1] ;# U2.D5 PJ1
+#set_property -dict {LOC AC29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pj2] ;# U2.E5 PJ2
+#set_property -dict {LOC AE28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pj3] ;# U2.A4 PJ3
+#set_property -dict {LOC AE29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pj4] ;# U2.B4 PJ4
+#set_property -dict {LOC AD29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pj5] ;# U2.C4 PJ5
+#set_property -dict {LOC AH28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pj6] ;# U2.D4 PJ6
+#set_property -dict {LOC AD26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pj7] ;# U2.E4 PJ7
+
+#set_property -dict {LOC AH27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pdi_data] ;# U2.F4 PDI_DATA
+#set_property -dict {LOC AH29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports avr_pdi_clk] ;# U2.F3 PDI_CLK
+
+# Si5338 U18
+set_property -dict {LOC AF33 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5338_i2c_scl] ;# U18.12 SCL
+set_property -dict {LOC AF34 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5338_i2c_sda] ;# U18.19 SDA
+set_property -dict {LOC AC27 IOSTANDARD LVCMOS18} [get_ports si5338_intr] ;# U18.8 INTR
+
+set_false_path -to [get_ports {si5338_i2c_scl si5338_i2c_sda}]
+set_output_delay 0 [get_ports {si5338_i2c_scl si5338_i2c_sda}]
+set_false_path -from [get_ports {si5338_i2c_scl si5338_i2c_sda si5338_intr}]
+set_input_delay 0 [get_ports {si5338_i2c_scl si5338_i2c_sda si5338_intr}]
+
+# 10/100 PHY (DP83630)
+#set_property -dict {LOC AJ16 IOSTANDARD LVCMOS18} [get_ports phy_tx_clk] ;# U5.1 TX_CLK via U53.4/13
+#set_property -dict {LOC AN14 IOSTANDARD LVCMOS18} [get_ports phy_tx_en] ;# U5.2 TX_EN via U51.4/13
+#set_property -dict {LOC AN18 IOSTANDARD LVCMOS18} [get_ports {phy_txd[0]}] ;# U5.3 TXD_0 via U50.4/13
+#set_property -dict {LOC AL16 IOSTANDARD LVCMOS18} [get_ports {phy_txd[1]}] ;# U5.4 TXD_1 via U50.5/12
+#set_property -dict {LOC AM16 IOSTANDARD LVCMOS18} [get_ports {phy_txd[2]}] ;# U5.5 TXD_2 via U50.6/11
+#set_property -dict {LOC AP17 IOSTANDARD LVCMOS18} [get_ports {phy_txd[3]}] ;# U5.6 TXD_3 via U50.7/10
+#set_property -dict {LOC AH15 IOSTANDARD LVCMOS18} [get_ports phy_rx_clk] ;# U5.38 RX_CLK via U55.5/12
+#set_property -dict {LOC AK18 IOSTANDARD LVCMOS18} [get_ports phy_rx_dv] ;# U5.39 RX_DV via U55.6/11
+#set_property -dict {LOC AL18 IOSTANDARD LVCMOS18} [get_ports phy_rx_er] ;# U5.41 RX_ER via U55.7/10
+#set_property -dict {LOC AP14 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[0]}] ;# U5.46 RXD_0 via U53.5/12
+#set_property -dict {LOC AM17 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[1]}] ;# U5.45 RXD_1 via U53.6/11
+#set_property -dict {LOC AN17 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[2]}] ;# U5.44 RXD_2 via U53.7/10
+#set_property -dict {LOC AL15 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[3]}] ;# U5.43 RXD_3 via U55.4/13
+#set_property -dict {LOC AL14 IOSTANDARD LVCMOS18} [get_ports phy_crs] ;# U5.40 CRS/CRS_DV via U57.5/12
+#set_property -dict {LOC AK14 IOSTANDARD LVCMOS18} [get_ports phy_col] ;# U5.42 COL via U57.4/13
+#set_property -dict {LOC AF16 IOSTANDARD LVCMOS18} [get_ports phy_refclk] ;# U5.34 X1
+#set_property -dict {LOC AC15 IOSTANDARD LVCMOS18} [get_ports phy_reset_n] ;# U5.29 RESET_N
+#set_property -dict {LOC AD15 IOSTANDARD LVCMOS18} [get_ports phy_int_n] ;# U5.7 PWRDOWN/INTN
+#set_property -dict {LOC AJ17 IOSTANDARD LVCMOS18} [get_ports phy_mdc] ;# U5.31 MDC
+#set_property -dict {LOC AK17 IOSTANDARD LVCMOS18} [get_ports phy_mdio] ;# U5.30 MDIO
+#set_property -dict {LOC AF13 IOSTANDARD LVCMOS18} [get_ports phy_gpio1] ;# U5.21 GPIO1
+#set_property -dict {LOC AG13 IOSTANDARD LVCMOS18} [get_ports phy_gpio2] ;# U5.22 GPIO2
+#set_property -dict {LOC AE17 IOSTANDARD LVCMOS18} [get_ports phy_gpio3] ;# U5.23 GPIO3
+#set_property -dict {LOC AE16 IOSTANDARD LVCMOS18} [get_ports phy_gpio4] ;# U5.25 GPIO4
+#set_property -dict {LOC AE14 IOSTANDARD LVCMOS18} [get_ports phy_gpio5] ;# U5.26 GPIO5/LED_ACT
+#set_property -dict {LOC AF14 IOSTANDARD LVCMOS18} [get_ports phy_gpio6] ;# U5.27 GPIO6/LED_SPEED/FX_SD
+#set_property -dict {LOC AC17 IOSTANDARD LVCMOS18} [get_ports phy_gpio7] ;# U5.28 GPIO7/LED_LINK
+#set_property -dict {LOC AD17 IOSTANDARD LVCMOS18} [get_ports phy_gpio8] ;# U5.36 GPIO8
+#set_property -dict {LOC AD14 IOSTANDARD LVCMOS18} [get_ports phy_gpio9] ;# U5.37 GPIO9
+#set_property -dict {LOC AG17 IOSTANDARD LVCMOS18} [get_ports phy_gpio12] ;# U5.24 GPIO12/CLK_OUT via U57.7/10
+#set_property -dict {LOC AJ14 IOSTANDARD LVCMOS18} [get_ports phy_isolate] ;# OE on U50, U51, U53, U55, U57
+
+# SFP+ Interfaces (J1-J4)
+set_property -dict {LOC B6  } [get_ports {sfp_rx_p[0]}] ;# MGTHRXP3_118 GTHE2_CHANNEL_X1Y39 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC B5  } [get_ports {sfp_rx_n[0]}] ;# MGTHRXN3_118 GTHE2_CHANNEL_X1Y39 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC A4  } [get_ports {sfp_tx_p[0]}] ;# MGTHTXP3_118 GTHE2_CHANNEL_X1Y39 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC A3  } [get_ports {sfp_tx_n[0]}] ;# MGTHTXN3_118 GTHE2_CHANNEL_X1Y39 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC D6  } [get_ports {sfp_rx_p[1]}] ;# MGTHRXP2_118 GTHE2_CHANNEL_X1Y38 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC D5  } [get_ports {sfp_rx_n[1]}] ;# MGTHRXN2_118 GTHE2_CHANNEL_X1Y38 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC B2  } [get_ports {sfp_tx_p[1]}] ;# MGTHTXP2_118 GTHE2_CHANNEL_X1Y38 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC B1  } [get_ports {sfp_tx_n[1]}] ;# MGTHTXN2_118 GTHE2_CHANNEL_X1Y38 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC H6  } [get_ports {sfp_mgt_refclk_p[0]}] ;# MGTREFCLK1P_118 from U20.10
+set_property -dict {LOC H5  } [get_ports {sfp_mgt_refclk_n[0]}] ;# MGTREFCLK1N_118 from U20.9
+set_property -dict {LOC W4  } [get_ports {sfp_rx_p[2]}] ;# MGTHRXP1_116 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC W3  } [get_ports {sfp_rx_n[2]}] ;# MGTHRXN1_116 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC V2  } [get_ports {sfp_tx_p[2]}] ;# MGTHTXP1_116 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC V1  } [get_ports {sfp_tx_n[2]}] ;# MGTHTXN1_116 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC AA4 } [get_ports {sfp_rx_p[3]}] ;# MGTHRXP0_116 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC AA3 } [get_ports {sfp_rx_n[3]}] ;# MGTHRXN0_116 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC Y2  } [get_ports {sfp_tx_p[3]}] ;# MGTHTXP0_116 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC Y1  } [get_ports {sfp_tx_n[3]}] ;# MGTHTXN0_116 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
+set_property -dict {LOC T6  } [get_ports {sfp_mgt_refclk_p[1]}] ;# MGTREFCLK0P_116 from U20.20
+set_property -dict {LOC T5  } [get_ports {sfp_mgt_refclk_n[1]}] ;# MGTREFCLK0N_116 from U20.21
+set_property -dict {LOC AG12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_mod_abs[0]}]
+set_property -dict {LOC AJ11 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_mod_abs[1]}]
+set_property -dict {LOC AK9  IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_mod_abs[2]}]
+set_property -dict {LOC AN10 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_mod_abs[3]}]
+set_property -dict {LOC AF10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[0][0]}]
+set_property -dict {LOC AG10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[0][1]}]
+set_property -dict {LOC AJ12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[1][0]}]
+set_property -dict {LOC AK12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[1][1]}]
+set_property -dict {LOC AL11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[2][0]}]
+set_property -dict {LOC AM11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[2][1]}]
+set_property -dict {LOC AP12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[3][0]}]
+set_property -dict {LOC AP11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[3][1]}]
+set_property -dict {LOC AH10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[0]}]
+set_property -dict {LOC AK8  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[1]}]
+set_property -dict {LOC AM12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[2]}]
+set_property -dict {LOC AM13 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[3]}]
+# set_property -dict {LOC AF9  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_scl[0]}]
+# set_property -dict {LOC AD9  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_sda[0]}]
+# set_property -dict {LOC AD12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_scl[1]}]
+# set_property -dict {LOC AF8  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_sda[1]}]
+# set_property -dict {LOC AF11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_scl[2]}]
+# set_property -dict {LOC AD11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_sda[2]}]
+# set_property -dict {LOC AG8  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_scl[3]}]
+# set_property -dict {LOC AG11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_sda[3]}]
+
+# 156.25 MHz MGT reference clock
+create_clock -period 6.4 -name {sfp_mgt_refclk_0} [get_ports {sfp_mgt_refclk_p[0]}]
+create_clock -period 6.4 -name {sfp_mgt_refclk_1} [get_ports {sfp_mgt_refclk_p[1]}]
+
+set_false_path -from [get_ports {sfp_mod_abs[*]}]
+set_input_delay 0 [get_ports {sfp_mod_abs[*]}]
+set_false_path -to [get_ports {sfp_rs[*][*]}]
+set_output_delay 0 [get_ports {sfp_rs[*][*]}]
+set_false_path -to [get_ports {get_ports sfp_tx_disable[*]}]
+set_output_delay 0 [get_ports {get_ports sfp_tx_disable[*]}]
+# set_false_path -to [get_ports {sfp_i2c_scl[*] sfp_i2c_sda[*]}]
+# set_output_delay 0 [get_ports {sfp_i2c_scl[*] sfp_i2c_sda[*]}]
+# set_false_path -from [get_ports {sfp_i2c_scl[*] sfp_i2c_sda[*]}]
+# set_input_delay 0 [get_ports {sfp_i2c_scl[*] sfp_i2c_sda[*]}]
+
+# PCIe Interface
+#set_property -dict {LOC AC4 } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_115 GTHE2_CHANNEL_X0Y11 / GTHE2_COMMON_X0Y2
+#set_property -dict {LOC AC3 } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_115 GTHE2_CHANNEL_X0Y11 / GTHE2_COMMON_X0Y2
+#set_property -dict {LOC AB2 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_115 GTHE2_CHANNEL_X0Y11 / GTHE2_COMMON_X0Y2
+#set_property -dict {LOC AB1 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_115 GTHE2_CHANNEL_X0Y11 / GTHE2_COMMON_X0Y2
+#set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_115 GTHE2_CHANNEL_X0Y10 / GTHE2_COMMON_X0Y2
+#set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_115 GTHE2_CHANNEL_X0Y10 / GTHE2_COMMON_X0Y2
+#set_property -dict {LOC AD2 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_115 GTHE2_CHANNEL_X0Y10 / GTHE2_COMMON_X0Y2
+#set_property -dict {LOC AD1 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_115 GTHE2_CHANNEL_X0Y10 / GTHE2_COMMON_X0Y2
+#set_property -dict {LOC AF6 } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_115 GTHE2_CHANNEL_X0Y9 / GTHE2_COMMON_X0Y2
+#set_property -dict {LOC AF5 } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_115 GTHE2_CHANNEL_X0Y9 / GTHE2_COMMON_X0Y2
+#set_property -dict {LOC AF2 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_115 GTHE2_CHANNEL_X0Y9 / GTHE2_COMMON_X0Y2
+#set_property -dict {LOC AF1 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_115 GTHE2_CHANNEL_X0Y9 / GTHE2_COMMON_X0Y2
+#set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_115 GTHE2_CHANNEL_X0Y8 / GTHE2_COMMON_X0Y2
+#set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_115 GTHE2_CHANNEL_X0Y8 / GTHE2_COMMON_X0Y2
+#set_property -dict {LOC AH2 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_115 GTHE2_CHANNEL_X0Y8 / GTHE2_COMMON_X0Y2
+#set_property -dict {LOC AH1 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_115 GTHE2_CHANNEL_X0Y8 / GTHE2_COMMON_X0Y2
+#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[4]}] ;# MGTHRXP3_114 GTHE2_CHANNEL_X0Y7 / GTHE2_COMMON_X0Y1
+#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[4]}] ;# MGTHRXN3_114 GTHE2_CHANNEL_X0Y7 / GTHE2_COMMON_X0Y1
+#set_property -dict {LOC AK2 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_114 GTHE2_CHANNEL_X0Y7 / GTHE2_COMMON_X0Y1
+#set_property -dict {LOC AK1 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_114 GTHE2_CHANNEL_X0Y7 / GTHE2_COMMON_X0Y1
+#set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[5]}] ;# MGTHRXP2_114 GTHE2_CHANNEL_X0Y6 / GTHE2_COMMON_X0Y1
+#set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[5]}] ;# MGTHRXN2_114 GTHE2_CHANNEL_X0Y6 / GTHE2_COMMON_X0Y1
+#set_property -dict {LOC AM2 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_114 GTHE2_CHANNEL_X0Y6 / GTHE2_COMMON_X0Y1
+#set_property -dict {LOC AM1 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_114 GTHE2_CHANNEL_X0Y6 / GTHE2_COMMON_X0Y1
+#set_property -dict {LOC AM6 } [get_ports {pcie_rx_p[6]}] ;# MGTHRXP1_114 GTHE2_CHANNEL_X0Y5 / GTHE2_COMMON_X0Y1
+#set_property -dict {LOC AM5 } [get_ports {pcie_rx_n[6]}] ;# MGTHRXN1_114 GTHE2_CHANNEL_X0Y5 / GTHE2_COMMON_X0Y1
+#set_property -dict {LOC AN4 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_114 GTHE2_CHANNEL_X0Y5 / GTHE2_COMMON_X0Y1
+#set_property -dict {LOC AN3 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_114 GTHE2_CHANNEL_X0Y5 / GTHE2_COMMON_X0Y1
+#set_property -dict {LOC AP6 } [get_ports {pcie_rx_p[7]}] ;# MGTHRXP0_114 GTHE2_CHANNEL_X0Y4 / GTHE2_COMMON_X0Y1
+#set_property -dict {LOC AP5 } [get_ports {pcie_rx_n[7]}] ;# MGTHRXN0_114 GTHE2_CHANNEL_X0Y4 / GTHE2_COMMON_X0Y1
+#set_property -dict {LOC AP2 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_114 GTHE2_CHANNEL_X0Y4 / GTHE2_COMMON_X0Y1
+#set_property -dict {LOC AP1 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_114 GTHE2_CHANNEL_X0Y4 / GTHE2_COMMON_X0Y1
+#set_property -dict {LOC AK6 } [get_ports pcie_mgt_refclk_p] ;# MGTREFCLK1P_115 via U28
+#set_property -dict {LOC AK5 } [get_ports pcie_mgt_refclk_n] ;# MGTREFCLK1N_115 via U28
+#set_property -dict {LOC AK32 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset]
+
+# 100 MHz MGT reference clock
+#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
+
+#set_false_path -from [get_ports {pcie_reset}]
+#set_input_delay 0 [get_ports {pcie_reset}]

src/eth/example/NT40E3/fpga/fpga/Makefile

@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xc7vx330tffg1157-2
+FPGA_TOP = fpga
+FPGA_ARCH = virtex7
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(RTL_DIR)/si5338_i2c_init.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/lss/rtl/taxi_i2c_master.sv
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+
+# XDC files
+XDC_FILES = ../fpga.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_phy_10g_7_gt.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+#IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
+
+# Configuration
+#CONFIG_TCL_FILES = config.tcl
+
+include ../common/vivado.mk
+
+program: $(PROJECT).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl

src/eth/example/NT40E3/fpga/lib/taxi

@@ -0,0 +1 @@
+../../../../../../

src/eth/example/NT40E3/fpga/rtl/fpga.sv

@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2014-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA top-level module
+ */
+module fpga #
+(
+    // simulation (set to avoid vendor primitives)
+    parameter logic SIM = 1'b0,
+    // vendor ("GENERIC", "XILINX", "ALTERA")
+    parameter string VENDOR = "XILINX",
+    // device family
+    parameter string FAMILY = "virtex7",
+    // 10G MAC configuration
+    parameter logic CFG_LOW_LATENCY = 1'b1,
+    parameter logic COMBINED_MAC_PCS = 1'b1
+)
+(
+    /*
+     * Clock: 80MHz
+     */
+    input  wire logic        clk_80mhz,
+
+    /*
+     * GPIO
+     */
+    output wire logic [3:0]  sfp_led,
+    output wire logic [3:0]  led,
+    output wire logic        led_red,
+    output wire logic        led_green,
+    output wire logic [1:0]  led_sync,
+
+    /*
+     * I2C
+     */
+    inout  wire logic        si5338_i2c_scl,
+    inout  wire logic        si5338_i2c_sda,
+    input  wire logic        si5338_intr,
+
+    /*
+     * Ethernet: SFP+
+     */
+    input  wire logic        sfp_rx_p[4],
+    input  wire logic        sfp_rx_n[4],
+    output wire logic        sfp_tx_p[4],
+    output wire logic        sfp_tx_n[4],
+    input  wire logic        sfp_mgt_refclk_p[2],
+    input  wire logic        sfp_mgt_refclk_n[2],
+
+    input  wire logic        sfp_mod_abs[4],
+    output wire logic [1:0]  sfp_rs[4],
+    output wire logic        sfp_tx_disable[4]
+);
+
+// Clock and reset
+
+wire clk_80mhz_ibufg;
+
+// Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
+wire clk_125mhz_int;
+wire rst_125mhz_int;
+
+// Internal 156.25 MHz clock
+wire clk_156mhz_int;
+wire rst_156mhz_int;
+
+wire mmcm_rst = 1'b0;
+wire mmcm_locked;
+wire mmcm_clkfb;
+
+IBUFG
+clk_80mhz_ibufg_inst (
+    .I(clk_80mhz),
+    .O(clk_80mhz_ibufg)
+);
+
+// MMCM instance
+// 80 MHz in, 125 MHz out
+// PFD range: 10 MHz to 500 MHz
+// VCO range: 600 MHz to 1440 MHz
+// M = 25, D = 2 sets Fvco = 1000 MHz
+// Divide by 8 to get output frequency of 125 MHz
+MMCME2_BASE #(
+    .BANDWIDTH("OPTIMIZED"),
+    .CLKOUT0_DIVIDE_F(8),
+    .CLKOUT0_DUTY_CYCLE(0.5),
+    .CLKOUT0_PHASE(0),
+    .CLKOUT1_DIVIDE(1),
+    .CLKOUT1_DUTY_CYCLE(0.5),
+    .CLKOUT1_PHASE(0),
+    .CLKOUT2_DIVIDE(1),
+    .CLKOUT2_DUTY_CYCLE(0.5),
+    .CLKOUT2_PHASE(0),
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.5),
+    .CLKOUT3_PHASE(0),
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.5),
+    .CLKOUT4_PHASE(0),
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.5),
+    .CLKOUT5_PHASE(0),
+    .CLKOUT6_DIVIDE(1),
+    .CLKOUT6_DUTY_CYCLE(0.5),
+    .CLKOUT6_PHASE(0),
+    .CLKFBOUT_MULT_F(25),
+    .CLKFBOUT_PHASE(0),
+    .DIVCLK_DIVIDE(2),
+    .REF_JITTER1(0.010),
+    .CLKIN1_PERIOD(12.5),
+    .STARTUP_WAIT("FALSE"),
+    .CLKOUT4_CASCADE("FALSE")
+)
+clk_mmcm_inst (
+    .CLKIN1(clk_80mhz_ibufg),
+    .CLKFBIN(mmcm_clkfb),
+    .RST(mmcm_rst),
+    .PWRDWN(1'b0),
+    .CLKOUT0(clk_125mhz_mmcm_out),
+    .CLKOUT0B(),
+    .CLKOUT1(),
+    .CLKOUT1B(),
+    .CLKOUT2(),
+    .CLKOUT2B(),
+    .CLKOUT3(),
+    .CLKOUT3B(),
+    .CLKOUT4(),
+    .CLKOUT5(),
+    .CLKOUT6(),
+    .CLKFBOUT(mmcm_clkfb),
+    .CLKFBOUTB(),
+    .LOCKED(mmcm_locked)
+);
+
+BUFG
+clk_bufg_inst (
+    .I(clk_125mhz_mmcm_out),
+    .O(clk_125mhz_int)
+);
+
+taxi_sync_reset #(
+    .N(4)
+)
+sync_reset_inst (
+    .clk(clk_125mhz_int),
+    .rst(~mmcm_locked),
+    .out(rst_125mhz_int)
+);
+
+// I2C
+wire si5338_i2c_scl_i;
+wire si5338_i2c_scl_o;
+wire si5338_i2c_sda_i;
+wire si5338_i2c_sda_o;
+
+assign si5338_i2c_scl_i = si5338_i2c_scl;
+assign si5338_i2c_scl = si5338_i2c_scl_o ? 1'bz : 1'b0;
+assign si5338_i2c_sda_i = si5338_i2c_sda;
+assign si5338_i2c_sda = si5338_i2c_sda_o ? 1'bz : 1'b0;
+
+// wire i2c_init_scl_i = i2c_scl_i;
+// wire i2c_init_scl_o;
+// wire i2c_init_sda_i = i2c_sda_i;
+// wire i2c_init_sda_o;
+
+// wire i2c_int_scl_i = i2c_scl_i;
+// wire i2c_int_scl_o;
+// wire i2c_int_sda_i = i2c_sda_i;
+// wire i2c_int_sda_o;
+
+// assign si5338_i2c_scl_o = si5338_i2c_init_scl_o & si5338_i2c_int_scl_o;
+// assign si5338_i2c_sda_o = si5338_i2c_init_sda_o & si5338_i2c_int_sda_o;
+
+// Si5338 init
+taxi_axis_if #(.DATA_W(12)) si5338_i2c_cmd();
+taxi_axis_if #(.DATA_W(8)) si5338_i2c_tx();
+taxi_axis_if #(.DATA_W(8)) si5338_i2c_rx();
+
+assign si5338_i2c_rx.tready = 1'b1;
+
+wire si5338_i2c_busy;
+
+// assign si5338_rst = ~rst_125mhz_int;
+
+taxi_i2c_master
+si5338_i2c_master_inst (
+    .clk(clk_125mhz_int),
+    .rst(rst_125mhz_int),
+
+    /*
+     * Host interface
+     */
+    .s_axis_cmd(si5338_i2c_cmd),
+    .s_axis_tx(si5338_i2c_tx),
+    .m_axis_rx(si5338_i2c_rx),
+
+    /*
+     * I2C interface
+     */
+    .scl_i(si5338_i2c_scl_i),
+    .scl_o(si5338_i2c_scl_o),
+    .sda_i(si5338_i2c_sda_i),
+    .sda_o(si5338_i2c_sda_o),
+
+    /*
+     * Status
+     */
+    .busy(),
+    .bus_control(),
+    .bus_active(),
+    .missed_ack(),
+
+    /*
+     * Configuration
+     */
+    .prescale(SIM ? 32 : 312),
+    .stop_on_idle(1)
+);
+
+si5338_i2c_init #(
+    .SIM_SPEEDUP(SIM)
+)
+si5338_i2c_init_inst (
+    .clk(clk_125mhz_int),
+    .rst(rst_125mhz_int),
+
+    /*
+     * I2C master interface
+     */
+    .m_axis_cmd(si5338_i2c_cmd),
+    .m_axis_tx(si5338_i2c_tx),
+
+    /*
+     * Status
+     */
+    .busy(si5338_i2c_busy),
+
+    /*
+     * Configuration
+     */
+    .start(1'b1)
+);
+
+fpga_core #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
+    .COMBINED_MAC_PCS(COMBINED_MAC_PCS)
+)
+core_inst (
+    /*
+     * Clock: 125MHz
+     * Synchronous reset
+     */
+    .clk_125mhz(clk_125mhz_int),
+    .rst_125mhz(rst_125mhz_int),
+
+    /*
+     * GPIO
+     */
+    .sfp_led(sfp_led),
+    .led(led),
+    .led_red(led_red),
+    .led_green(led_green),
+    .led_sync(led_sync),
+
+    /*
+     * Ethernet: SFP+
+     */
+    .sfp_rx_p(sfp_rx_p),
+    .sfp_rx_n(sfp_rx_n),
+    .sfp_tx_p(sfp_tx_p),
+    .sfp_tx_n(sfp_tx_n),
+    .sfp_mgt_refclk_p(sfp_mgt_refclk_p),
+    .sfp_mgt_refclk_n(sfp_mgt_refclk_n),
+    // .sma_mgt_refclk_p(sma_mgt_refclk_p),
+    // .sma_mgt_refclk_n(sma_mgt_refclk_n),
+    // .sfp_recclk_p(sfp_recclk_p),
+    // .sfp_recclk_n(sfp_recclk_n),
+
+    .sfp_mod_abs(sfp_mod_abs),
+    .sfp_rs(sfp_rs),
+    .sfp_tx_disable(sfp_tx_disable)
+);
+
+endmodule
+
+`resetall

src/eth/example/NT40E3/fpga/rtl/fpga_core.sv

@@ -0,0 +1,434 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2014-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA core logic
+ */
+module fpga_core #
+(
+    // simulation (set to avoid vendor primitives)
+    parameter logic SIM = 1'b0,
+    // vendor ("GENERIC", "XILINX", "ALTERA")
+    parameter string VENDOR = "XILINX",
+    // device family
+    parameter string FAMILY = "virtex7",
+    // 10G MAC configuration
+    parameter logic CFG_LOW_LATENCY = 1'b1,
+    parameter logic COMBINED_MAC_PCS = 1'b1,
+    parameter MAC_DATA_W = 32
+)
+(
+    /*
+     * Clock: 125 MHz
+     * Synchronous reset
+     */
+    input  wire logic        clk_125mhz,
+    input  wire logic        rst_125mhz,
+
+    /*
+     * GPIO
+     */
+    output wire logic [3:0]  sfp_led,
+    output wire logic [3:0]  led,
+    output wire logic        led_red,
+    output wire logic        led_green,
+    output wire logic [1:0]  led_sync,
+
+    /*
+     * Ethernet: SFP+
+     */
+    input  wire logic        sfp_rx_p[4],
+    input  wire logic        sfp_rx_n[4],
+    output wire logic        sfp_tx_p[4],
+    output wire logic        sfp_tx_n[4],
+    input  wire logic        sfp_mgt_refclk_p[2],
+    input  wire logic        sfp_mgt_refclk_n[2],
+
+    input  wire logic        sfp_mod_abs[4],
+    output wire logic [1:0]  sfp_rs[4],
+    input  wire logic        sfp_los[4],
+    output wire logic        sfp_tx_disable[4],
+    input  wire logic        sfp_tx_fault[4]
+);
+
+// SFP+
+assign sfp_tx_disable = '{4{1'b0}};
+
+wire sfp_tx_clk[4];
+wire sfp_tx_rst[4];
+wire sfp_rx_clk[4];
+wire sfp_rx_rst[4];
+
+wire sfp_rx_status[4];
+
+assign sfp_led[0] = sfp_rx_status[0];
+assign sfp_led[1] = sfp_rx_status[1];
+assign sfp_led[2] = sfp_rx_status[2];
+assign sfp_led[3] = sfp_rx_status[3];
+
+wire [1:0] sfp_gtpowergood;
+
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_tx[4]();
+taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[4]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_rx[4]();
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_sfp_stat[2]();
+
+wire sfp_mgt_refclk[2];
+wire sfp_mgt_refclk_bufg[2];
+
+wire sfp_rst[2];
+
+for (genvar n = 0; n < 2; n = n + 1) begin : gty_clk
+
+    wire sfp_mgt_refclk_int;
+
+    if (SIM) begin
+
+        assign sfp_mgt_refclk[n] = sfp_mgt_refclk_p[n];
+        assign sfp_mgt_refclk_int = sfp_mgt_refclk_p[n];
+        assign sfp_mgt_refclk_bufg[n] = sfp_mgt_refclk_int;
+
+    end else begin
+
+        IBUFDS_GTE2 ibufds_gte2_sfp_mgt_refclk_inst (
+            .I     (sfp_mgt_refclk_p[n]),
+            .IB    (sfp_mgt_refclk_n[n]),
+            .CEB   (1'b0),
+            .O     (sfp_mgt_refclk[n]),
+            .ODIV2 (sfp_mgt_refclk_int)
+        );
+
+        BUFG bufg_sfp_mgt_refclk_inst (
+            .I (sfp_mgt_refclk_int),
+            .O (sfp_mgt_refclk_bufg[n])
+        );
+
+    end
+
+    taxi_sync_reset #(
+        .N(4)
+    )
+    sfp_sync_reset_inst (
+        .clk(sfp_mgt_refclk_bufg[n]),
+        .rst(rst_125mhz),
+        .out(sfp_rst[n])
+    );
+
+end
+
+for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
+
+    localparam CLK = n;
+    localparam CNT = 2;
+
+    taxi_apb_if #(
+        .ADDR_W(18),
+        .DATA_W(16)
+    )
+    gt_apb_ctrl();
+
+    taxi_eth_mac_25g_us #(
+        .SIM(SIM),
+        .VENDOR(VENDOR),
+        .FAMILY(FAMILY),
+
+        .CNT(CNT),
+
+        // GT config
+        .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
+
+        // GT type
+        .GT_TYPE("GTH"),
+
+        // GT parameters
+        .GT_TX_POLARITY(n == 0 ? 2'b01 : 2'b00),
+        .GT_RX_POLARITY('0),
+
+        // MAC/PHY config
+        .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
+        .DATA_W(MAC_DATA_W),
+        .PADDING_EN(1'b1),
+        .DIC_EN(1'b1),
+        .MIN_FRAME_LEN(64),
+        .PTP_TS_EN(1'b0),
+        .PTP_TD_EN(1'b0),
+        .PTP_TS_FMT_TOD(1'b1),
+        .PTP_TS_W(96),
+        .PTP_TD_SDI_PIPELINE(2),
+        .PRBS31_EN(1'b0),
+        .TX_SERDES_PIPELINE(1),
+        .RX_SERDES_PIPELINE(1),
+        .COUNT_125US(125000/6.4),
+        .STAT_EN(1'b0)
+    )
+    mac_inst (
+        .xcvr_ctrl_clk(clk_125mhz),
+        .xcvr_ctrl_rst(sfp_rst[CLK]),
+
+        /*
+         * Transceiver control
+         */
+        .s_apb_ctrl(gt_apb_ctrl),
+
+        /*
+         * Common
+         */
+        .xcvr_gtpowergood_out(sfp_gtpowergood[n]),
+        .xcvr_gtrefclk00_in(sfp_mgt_refclk[CLK]),
+        .xcvr_qpll0pd_in(1'b0),
+        .xcvr_qpll0reset_in(1'b0),
+        .xcvr_qpll0pcierate_in(3'd0),
+        .xcvr_qpll0lock_out(),
+        .xcvr_qpll0clk_out(),
+        .xcvr_qpll0refclk_out(),
+        .xcvr_gtrefclk01_in(sfp_mgt_refclk[CLK]),
+        .xcvr_qpll1pd_in(1'b0),
+        .xcvr_qpll1reset_in(1'b0),
+        .xcvr_qpll1pcierate_in(3'd0),
+        .xcvr_qpll1lock_out(),
+        .xcvr_qpll1clk_out(),
+        .xcvr_qpll1refclk_out(),
+
+        /*
+         * Serial data
+         */
+        .xcvr_txp(sfp_tx_p[n*CNT +: CNT]),
+        .xcvr_txn(sfp_tx_n[n*CNT +: CNT]),
+        .xcvr_rxp(sfp_rx_p[n*CNT +: CNT]),
+        .xcvr_rxn(sfp_rx_n[n*CNT +: CNT]),
+
+        /*
+         * MAC clocks
+         */
+        .rx_clk(sfp_rx_clk[n*CNT +: CNT]),
+        .rx_rst_in('{CNT{1'b0}}),
+        .rx_rst_out(sfp_rx_rst[n*CNT +: CNT]),
+        .tx_clk(sfp_tx_clk[n*CNT +: CNT]),
+        .tx_rst_in('{CNT{1'b0}}),
+        .tx_rst_out(sfp_tx_rst[n*CNT +: CNT]),
+
+        /*
+         * Transmit interface (AXI stream)
+         */
+        .s_axis_tx(axis_sfp_tx[n*CNT +: CNT]),
+        .m_axis_tx_cpl(axis_sfp_tx_cpl[n*CNT +: CNT]),
+
+        /*
+         * Receive interface (AXI stream)
+         */
+        .m_axis_rx(axis_sfp_rx[n*CNT +: CNT]),
+
+        /*
+         * PTP clock
+         */
+        .ptp_clk(1'b0),
+        .ptp_rst(1'b0),
+        .ptp_sample_clk(1'b0),
+        .ptp_td_sdi(1'b0),
+        .tx_ptp_ts_in('{CNT{'0}}),
+        .tx_ptp_ts_out(),
+        .tx_ptp_ts_step_out(),
+        .tx_ptp_locked(),
+        .rx_ptp_ts_in('{CNT{'0}}),
+        .rx_ptp_ts_out(),
+        .rx_ptp_ts_step_out(),
+        .rx_ptp_locked(),
+
+        /*
+         * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
+         */
+        .tx_lfc_req('{CNT{1'b0}}),
+        .tx_lfc_resend('{CNT{1'b0}}),
+        .rx_lfc_en('{CNT{1'b0}}),
+        .rx_lfc_req(),
+        .rx_lfc_ack('{CNT{1'b0}}),
+
+        /*
+         * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
+         */
+        .tx_pfc_req('{CNT{'0}}),
+        .tx_pfc_resend('{CNT{1'b0}}),
+        .rx_pfc_en('{CNT{'0}}),
+        .rx_pfc_req(),
+        .rx_pfc_ack('{CNT{'0}}),
+
+        /*
+         * Pause interface
+         */
+        .tx_lfc_pause_en('{CNT{1'b0}}),
+        .tx_pause_req('{CNT{1'b0}}),
+        .tx_pause_ack(),
+
+        /*
+         * Statistics
+         */
+        .stat_clk(clk_125mhz),
+        .stat_rst(rst_125mhz),
+        .m_axis_stat(axis_sfp_stat[n]),
+
+        /*
+         * Status
+         */
+        .tx_start_packet(),
+        .stat_tx_byte(),
+        .stat_tx_pkt_len(),
+        .stat_tx_pkt_ucast(),
+        .stat_tx_pkt_mcast(),
+        .stat_tx_pkt_bcast(),
+        .stat_tx_pkt_vlan(),
+        .stat_tx_pkt_good(),
+        .stat_tx_pkt_bad(),
+        .stat_tx_err_oversize(),
+        .stat_tx_err_user(),
+        .stat_tx_err_underflow(),
+        .rx_start_packet(),
+        .rx_error_count(),
+        .rx_block_lock(),
+        .rx_high_ber(),
+        .rx_status(sfp_rx_status[n*CNT +: CNT]),
+        .stat_rx_byte(),
+        .stat_rx_pkt_len(),
+        .stat_rx_pkt_fragment(),
+        .stat_rx_pkt_jabber(),
+        .stat_rx_pkt_ucast(),
+        .stat_rx_pkt_mcast(),
+        .stat_rx_pkt_bcast(),
+        .stat_rx_pkt_vlan(),
+        .stat_rx_pkt_good(),
+        .stat_rx_pkt_bad(),
+        .stat_rx_err_oversize(),
+        .stat_rx_err_bad_fcs(),
+        .stat_rx_err_bad_block(),
+        .stat_rx_err_framing(),
+        .stat_rx_err_preamble(),
+        .stat_rx_fifo_drop('{CNT{1'b0}}),
+        .stat_tx_mcf(),
+        .stat_rx_mcf(),
+        .stat_tx_lfc_pkt(),
+        .stat_tx_lfc_xon(),
+        .stat_tx_lfc_xoff(),
+        .stat_tx_lfc_paused(),
+        .stat_tx_pfc_pkt(),
+        .stat_tx_pfc_xon(),
+        .stat_tx_pfc_xoff(),
+        .stat_tx_pfc_paused(),
+        .stat_rx_lfc_pkt(),
+        .stat_rx_lfc_xon(),
+        .stat_rx_lfc_xoff(),
+        .stat_rx_lfc_paused(),
+        .stat_rx_pfc_pkt(),
+        .stat_rx_pfc_xon(),
+        .stat_rx_pfc_xoff(),
+        .stat_rx_pfc_paused(),
+
+        /*
+         * Configuration
+         */
+        .cfg_tx_max_pkt_len('{CNT{16'd9218}}),
+        .cfg_tx_ifg('{CNT{8'd12}}),
+        .cfg_tx_enable('{CNT{1'b1}}),
+        .cfg_rx_max_pkt_len('{CNT{16'd9218}}),
+        .cfg_rx_enable('{CNT{1'b1}}),
+        .cfg_tx_prbs31_enable('{CNT{1'b0}}),
+        .cfg_rx_prbs31_enable('{CNT{1'b0}}),
+        .cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
+        .cfg_mcf_rx_check_eth_dst_mcast('{CNT{1'b1}}),
+        .cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
+        .cfg_mcf_rx_check_eth_dst_ucast('{CNT{1'b0}}),
+        .cfg_mcf_rx_eth_src('{CNT{48'd0}}),
+        .cfg_mcf_rx_check_eth_src('{CNT{1'b0}}),
+        .cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
+        .cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
+        .cfg_mcf_rx_check_opcode_lfc('{CNT{1'b1}}),
+        .cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
+        .cfg_mcf_rx_check_opcode_pfc('{CNT{1'b1}}),
+        .cfg_mcf_rx_forward('{CNT{1'b0}}),
+        .cfg_mcf_rx_enable('{CNT{1'b0}}),
+        .cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
+        .cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
+        .cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
+        .cfg_tx_lfc_opcode('{CNT{16'h0001}}),
+        .cfg_tx_lfc_en('{CNT{1'b0}}),
+        .cfg_tx_lfc_quanta('{CNT{16'hffff}}),
+        .cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
+        .cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
+        .cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
+        .cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
+        .cfg_tx_pfc_opcode('{CNT{16'h0101}}),
+        .cfg_tx_pfc_en('{CNT{1'b0}}),
+        .cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
+        .cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
+        .cfg_rx_lfc_opcode('{CNT{16'h0001}}),
+        .cfg_rx_lfc_en('{CNT{1'b0}}),
+        .cfg_rx_pfc_opcode('{CNT{16'h0101}}),
+        .cfg_rx_pfc_en('{CNT{1'b0}})
+    );
+
+end
+
+for (genvar n = 0; n < 4; n = n + 1) begin : sfp_ch
+
+    taxi_axis_async_fifo #(
+        .DEPTH(16384),
+        .RAM_PIPELINE(2),
+        .FRAME_FIFO(1),
+        .USER_BAD_FRAME_VALUE(1'b1),
+        .USER_BAD_FRAME_MASK(1'b1),
+        .DROP_OVERSIZE_FRAME(1),
+        .DROP_BAD_FRAME(1),
+        .DROP_WHEN_FULL(1)
+    )
+    ch_fifo (
+        /*
+         * AXI4-Stream input (sink)
+         */
+        .s_clk(sfp_rx_clk[n]),
+        .s_rst(sfp_rx_rst[n]),
+        .s_axis(axis_sfp_rx[n]),
+
+        /*
+         * AXI4-Stream output (source)
+         */
+        .m_clk(sfp_tx_clk[n]),
+        .m_rst(sfp_tx_rst[n]),
+        .m_axis(axis_sfp_tx[n]),
+
+        /*
+         * Pause
+         */
+        .s_pause_req(1'b0),
+        .s_pause_ack(),
+        .m_pause_req(1'b0),
+        .m_pause_ack(),
+
+        /*
+         * Status
+         */
+        .s_status_depth(),
+        .s_status_depth_commit(),
+        .s_status_overflow(),
+        .s_status_bad_frame(),
+        .s_status_good_frame(),
+        .m_status_depth(),
+        .m_status_depth_commit(),
+        .m_status_overflow(),
+        .m_status_bad_frame(),
+        .m_status_good_frame()
+    );
+
+end
+
+endmodule
+
+`resetall

src/eth/example/NT40E3/fpga/rtl/si5338_i2c_init.sv

@@ -0,0 +1,548 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2015-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * I2C init
+ */
+module si5338_i2c_init #
+(
+    parameter logic SIM_SPEEDUP = 1'b0
+)
+(
+    input  wire logic  clk,
+    input  wire logic  rst,
+
+    /*
+     * I2C master interface
+     */
+    taxi_axis_if.src   m_axis_cmd,
+    taxi_axis_if.src   m_axis_tx,
+
+    /*
+     * Status
+     */
+    output wire logic  busy,
+
+    /*
+     * Configuration
+     */
+    input  wire logic  start
+);
+
+/*
+
+Generic module for I2C bus initialization.  Good for use when multiple devices
+on an I2C bus must be initialized on system start without intervention of a
+general-purpose processor.
+
+Copy this file and change init_data and INIT_DATA_LEN as needed.
+
+This module can be used in two modes: simple device initialization, or multiple
+device initialization.  In multiple device mode, the same initialization sequence
+can be performed on multiple different device addresses.
+
+To use single device mode, only use the start write to address and write data commands.
+The module will generate the I2C commands in sequential order.  Terminate the list
+with a 0 entry.
+
+To use the multiple device mode, use the start data and start address block commands
+to set up lists of initialization data and device addresses.  The module enters
+multiple device mode upon seeing a start data block command.  The module stores the
+offset of the start of the data block and then skips ahead until it reaches a start
+address block command.  The module will store the offset to the address block and
+read the first address in the block.  Then it will jump back to the data block
+and execute it, substituting the stored address for each current address write
+command.  Upon reaching the start address block command, the module will read out the
+next address and start again at the top of the data block.  If the module encounters
+a start data block command while looking for an address, then it will store a new data
+offset and then look for a start address block command.  Terminate the list with a 0
+entry.  Normal address commands will operate normally inside a data block.
+
+Commands:
+
+00 0000000 : halt
+00 0000001 : exit multiple device mode
+00 0000011 : start write to current address
+00 0001000 : start address block
+00 0001001 : start data block
+00 001dddd : delay 2**(16+d) cycles
+00 1000001 : send I2C stop
+01 aaaaaaa : start write to address
+1 dddddddd : write 8-bit data
+
+Examples
+
+write 0x11223344 to register 0x0004 on device at 0x50
+
+01 1010000  start write to 0x50
+1 00000000  write address 0x0004
+1 00000100
+1 00010001  write data 0x11223344
+1 00100010
+1 00110011
+1 01000100
+0 00000000  halt
+
+write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53
+
+00 0001001  start data block
+00 0000011  start write to current address
+1 00000000  write address 0x0004
+1 00000100
+1 00010001  write data 0x11223344
+1 00100010
+1 00110011
+1 01000100
+00 0001000  start address block
+01 1010000  address 0x50
+01 1010001  address 0x51
+01 1010010  address 0x52
+01 1010011  address 0x53
+00 0000001  exit multi-dev mode
+00 0000000  halt
+
+*/
+
+// check configuration
+if (m_axis_cmd.DATA_W < 12)
+    $fatal(0, "Command interface width must be at least 12 bits (instance %m)");
+
+if (m_axis_tx.DATA_W != 8)
+    $fatal(0, "Data interface width must be 8 bits (instance %m)");
+
+function [8:0] cmd_start(input [6:0] addr);
+    cmd_start = {2'b01, addr};
+endfunction
+
+function [8:0] cmd_wr(input [7:0] data);
+    cmd_wr = {1'b1, data};
+endfunction
+
+function [8:0] cmd_stop();
+    cmd_stop = {2'b00, 7'b1000001};
+endfunction
+
+function [8:0] cmd_delay(input [3:0] d);
+    cmd_delay = {2'b00, 3'b001, d};
+endfunction
+
+function [8:0] cmd_halt();
+    cmd_halt = 9'd0;
+endfunction
+
+function [8:0] blk_start_data();
+    blk_start_data = {2'b00, 7'b0001001};
+endfunction
+
+function [8:0] blk_start_addr();
+    blk_start_addr = {2'b00, 7'b0001000};
+endfunction
+
+function [8:0] cmd_start_cur();
+    cmd_start_cur = {2'b00, 7'b0000011};
+endfunction
+
+function [8:0] cmd_exit();
+    cmd_exit = {2'b00, 7'b0000001};
+endfunction
+
+// init_data ROM
+localparam INIT_DATA_LEN = 20;
+
+logic [8:0] init_data [INIT_DATA_LEN-1:0];
+
+initial begin
+    // Initial delay
+    init_data[0]  = cmd_delay(6); // delay 30 ms
+    // init Si5338 registers
+    init_data[1]  = cmd_start(7'h70); // start write to 0x70 (Si5338)
+    init_data[2]  = cmd_wr(8'd255); // register 255
+    init_data[3]  = cmd_wr(8'd0);   // Reg 255: select page 0
+    init_data[4]  = cmd_start(7'h70); // start write to 0x70 (Si5338)
+    init_data[5]  = cmd_wr(8'd31);  // register 31
+    init_data[6]  = cmd_wr(8'hC0);  // Reg 31: power up CLK0
+    init_data[7]  = cmd_wr(8'hC1);  // Reg 32: power down CLK1
+    init_data[8]  = cmd_wr(8'hC1);  // Reg 33: power down CLK2
+    init_data[9]  = cmd_wr(8'hC0);  // Reg 34: power up CLK3
+    init_data[10] = cmd_wr(8'hAA);  // Reg 35: VDDO 0-3 = 1.8V
+    init_data[11] = cmd_wr(8'h06);  // Reg 36: CLK0 LVDS, no inversion
+    init_data[12] = cmd_wr(8'h06);  // Reg 37: CLK1 LVDS, no inversion
+    init_data[13] = cmd_wr(8'h06);  // Reg 38: CLK2 LVDS, no inversion
+    init_data[14] = cmd_wr(8'h06);  // Reg 39: CLK3 LVDS, no inversion
+    init_data[15] = cmd_start(7'h70); // start write to 0x70 (Si5338)
+    init_data[16] = cmd_wr(8'd230); // register 230
+    init_data[17] = cmd_wr(8'h06);  // Reg 230: enable CLK0 and CLK3
+    init_data[18] = cmd_delay(6); // delay 30 ms
+    init_data[19] = cmd_halt(); // stop
+end
+
+localparam [2:0]
+    STATE_IDLE = 3'd0,
+    STATE_RUN = 3'd1,
+    STATE_TABLE_1 = 3'd2,
+    STATE_TABLE_2 = 3'd3,
+    STATE_TABLE_3 = 3'd4;
+
+logic [2:0] state_reg = STATE_IDLE, state_next;
+
+localparam AW = $clog2(INIT_DATA_LEN);
+
+logic [8:0] init_data_reg = '0;
+
+logic [AW-1:0] address_reg = '0, address_next;
+logic [AW-1:0] address_ptr_reg = '0, address_ptr_next;
+logic [AW-1:0] data_ptr_reg = '0, data_ptr_next;
+
+logic [6:0] cur_address_reg = '0, cur_address_next;
+
+logic [31:0] delay_counter_reg = '0, delay_counter_next;
+
+logic [6:0] m_axis_cmd_address_reg = '0, m_axis_cmd_address_next;
+logic m_axis_cmd_start_reg = 1'b0, m_axis_cmd_start_next;
+logic m_axis_cmd_write_reg = 1'b0, m_axis_cmd_write_next;
+logic m_axis_cmd_stop_reg = 1'b0, m_axis_cmd_stop_next;
+logic m_axis_cmd_valid_reg = 1'b0, m_axis_cmd_valid_next;
+
+logic [7:0] m_axis_tx_tdata_reg = '0, m_axis_tx_tdata_next;
+logic m_axis_tx_tvalid_reg = 1'b0, m_axis_tx_tvalid_next;
+
+logic start_flag_reg = 1'b0, start_flag_next;
+
+logic busy_reg = 1'b0;
+
+assign m_axis_cmd.tdata[6:0] = m_axis_cmd_address_reg;
+assign m_axis_cmd.tdata[7]   = m_axis_cmd_start_reg;
+assign m_axis_cmd.tdata[8]   = 1'b0; // read
+assign m_axis_cmd.tdata[9]   = m_axis_cmd_write_reg;
+assign m_axis_cmd.tdata[10]  = 1'b0; // write multi
+assign m_axis_cmd.tdata[11]  = m_axis_cmd_stop_reg;
+assign m_axis_cmd.tvalid = m_axis_cmd_valid_reg;
+assign m_axis_cmd.tlast = 1'b1;
+assign m_axis_cmd.tid = '0;
+assign m_axis_cmd.tdest = '0;
+assign m_axis_cmd.tuser = '0;
+
+assign m_axis_tx.tdata = m_axis_tx_tdata_reg;
+assign m_axis_tx.tvalid = m_axis_tx_tvalid_reg;
+assign m_axis_tx.tlast = 1'b1;
+assign m_axis_tx.tid = '0;
+assign m_axis_tx.tdest = '0;
+assign m_axis_tx.tuser = '0;
+
+assign busy = busy_reg;
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    address_next = address_reg;
+    address_ptr_next = address_ptr_reg;
+    data_ptr_next = data_ptr_reg;
+
+    cur_address_next = cur_address_reg;
+
+    delay_counter_next = delay_counter_reg;
+
+    m_axis_cmd_address_next = m_axis_cmd_address_reg;
+    m_axis_cmd_start_next = m_axis_cmd_start_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
+    m_axis_cmd_write_next = m_axis_cmd_write_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
+    m_axis_cmd_stop_next = m_axis_cmd_stop_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
+    m_axis_cmd_valid_next = m_axis_cmd_valid_reg && !m_axis_cmd.tready;
+
+    m_axis_tx_tdata_next = m_axis_tx_tdata_reg;
+    m_axis_tx_tvalid_next = m_axis_tx_tvalid_reg && !m_axis_tx.tready;
+
+    start_flag_next = start_flag_reg;
+
+    if (m_axis_cmd.tvalid || m_axis_tx.tvalid) begin
+        // wait for output registers to clear
+        state_next = state_reg;
+    end else if (delay_counter_reg != 0) begin
+        // delay
+        delay_counter_next = delay_counter_reg - 1;
+        state_next = state_reg;
+    end else begin
+        case (state_reg)
+            STATE_IDLE: begin
+                // wait for start signal
+                if (!start_flag_reg && start) begin
+                    address_next = '0;
+                    start_flag_next = 1'b1;
+                    state_next = STATE_RUN;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_RUN: begin
+                // process commands
+                if (init_data_reg[8] == 1'b1) begin
+                    // write data
+                    m_axis_cmd_write_next = 1'b1;
+                    m_axis_cmd_stop_next = 1'b0;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    m_axis_tx_tdata_next = init_data_reg[7:0];
+                    m_axis_tx_tvalid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg[8:7] == 2'b01) begin
+                    // write address
+                    m_axis_cmd_address_next = init_data_reg[6:0];
+                    m_axis_cmd_start_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg[8:4] == 5'b00001) begin
+                    // delay
+                    if (SIM_SPEEDUP) begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]);
+                    end else begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]+16);
+                    end
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'b001000001) begin
+                    // send stop
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end
+            end
+            STATE_TABLE_1: begin
+                // find address table start
+                if (init_data_reg == 9'b000001000) begin
+                    // address table start
+                    address_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_2;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 1) begin
+                    // exit mode
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end
+            end
+            STATE_TABLE_2: begin
+                // find next address
+                if (init_data_reg[8:7] == 2'b01) begin
+                    // write address command
+                    // store address and move to data table
+                    cur_address_next = init_data_reg[6:0];
+                    address_ptr_next = address_reg + 1;
+                    address_next = data_ptr_reg;
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 9'd1) begin
+                    // exit mode
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_2;
+                end
+            end
+            STATE_TABLE_3: begin
+                // process data table with selected address
+                if (init_data_reg[8] == 1'b1) begin
+                    // write data
+                    m_axis_cmd_write_next = 1'b1;
+                    m_axis_cmd_stop_next = 1'b0;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    m_axis_tx_tdata_next = init_data_reg[7:0];
+                    m_axis_tx_tvalid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg[8:7] == 2'b01) begin
+                    // write address
+                    m_axis_cmd_address_next = init_data_reg[6:0];
+                    m_axis_cmd_start_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b000000011) begin
+                    // write current address
+                    m_axis_cmd_address_next = cur_address_reg;
+                    m_axis_cmd_start_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg[8:4] == 5'b00001) begin
+                    // delay
+                    if (SIM_SPEEDUP) begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]);
+                    end else begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]+16);
+                    end
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b001000001) begin
+                    // send stop
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 9'b000001000) begin
+                    // address table start
+                    address_next = address_ptr_reg;
+                    state_next = STATE_TABLE_2;
+                end else if (init_data_reg == 9'd1) begin
+                    // exit mode
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_3;
+                end
+            end
+            default: begin
+                // invalid state
+                state_next = STATE_IDLE;
+            end
+        endcase
+    end
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+
+    // read init_data ROM
+    init_data_reg <= init_data[address_next];
+
+    address_reg <= address_next;
+    address_ptr_reg <= address_ptr_next;
+    data_ptr_reg <= data_ptr_next;
+
+    cur_address_reg <= cur_address_next;
+
+    delay_counter_reg <= delay_counter_next;
+
+    m_axis_cmd_address_reg <= m_axis_cmd_address_next;
+    m_axis_cmd_start_reg <= m_axis_cmd_start_next;
+    m_axis_cmd_write_reg <= m_axis_cmd_write_next;
+    m_axis_cmd_stop_reg <= m_axis_cmd_stop_next;
+    m_axis_cmd_valid_reg <= m_axis_cmd_valid_next;
+
+    m_axis_tx_tdata_reg <= m_axis_tx_tdata_next;
+    m_axis_tx_tvalid_reg <= m_axis_tx_tvalid_next;
+
+    start_flag_reg <= start && start_flag_next;
+
+    busy_reg <= (state_reg != STATE_IDLE);
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+
+        init_data_reg <= '0;
+
+        address_reg <= '0;
+        address_ptr_reg <= '0;
+        data_ptr_reg <= '0;
+
+        cur_address_reg <= '0;
+
+        delay_counter_reg <= '0;
+
+        m_axis_cmd_valid_reg <= 1'b0;
+
+        m_axis_tx_tvalid_reg <= 1'b0;
+
+        start_flag_reg <= 1'b0;
+
+        busy_reg <= 1'b0;
+    end
+end
+
+endmodule
+
+`resetall

src/eth/example/NT40E3/fpga/tb/fpga_core/Makefile

@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = fpga_core
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = $(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/lss/rtl/taxi_i2c_master.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_SIM := "1'b1"
+export PARAM_VENDOR := "\"XILINX\""
+export PARAM_FAMILY := "\"virtex7\""
+export PARAM_CFG_LOW_LATENCY := "1'b1"
+export PARAM_COMBINED_MAC_PCS := "1'b1"
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/example/NT40E3/fpga/tb/fpga_core/baser.py

@@ -0,0 +1 @@
+../../lib/taxi/src/eth/tb/baser.py

src/eth/example/NT40E3/fpga/tb/fpga_core/test_fpga_core.py

@@ -0,0 +1,227 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: MIT
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import sys
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Combine
+
+from cocotbext.eth import XgmiiFrame
+
+try:
+    from baser import BaseRSerdesSource, BaseRSerdesSink
+except ImportError:
+    # attempt import from current directory
+    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
+    try:
+        from baser import BaseRSerdesSource, BaseRSerdesSink
+    finally:
+        del sys.path[0]
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
+
+        self.sfp_sources = []
+        self.sfp_sinks = []
+
+        cocotb.start_soon(Clock(dut.sfp_mgt_refclk_p[0], 6.4, units="ns").start())
+        cocotb.start_soon(Clock(dut.sfp_mgt_refclk_p[1], 6.4, units="ns").start())
+
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]):
+            gt_inst = ch.ch_inst.gt.gt_inst
+
+            if ch.ch_inst.CFG_LOW_LATENCY.value:
+                clk = 3.102
+                gbx_cfg = (66, [64, 65])
+            else:
+                clk = 3.2
+                gbx_cfg = None
+
+            cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())
+            cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start())
+
+            self.sfp_sources.append(BaseRSerdesSource(
+                data=gt_inst.serdes_rx_data,
+                data_valid=gt_inst.serdes_rx_data_valid,
+                hdr=gt_inst.serdes_rx_hdr,
+                hdr_valid=gt_inst.serdes_rx_hdr_valid,
+                clock=gt_inst.rx_clk,
+                slip=gt_inst.serdes_rx_bitslip,
+                reverse=True,
+                gbx_cfg=gbx_cfg
+            ))
+            self.sfp_sinks.append(BaseRSerdesSink(
+                data=gt_inst.serdes_tx_data,
+                data_valid=gt_inst.serdes_tx_data_valid,
+                hdr=gt_inst.serdes_tx_hdr,
+                hdr_valid=gt_inst.serdes_tx_hdr_valid,
+                gbx_sync=gt_inst.serdes_tx_gbx_sync,
+                clock=gt_inst.tx_clk,
+                reverse=True,
+                gbx_cfg=gbx_cfg
+            ))
+
+    async def init(self):
+
+        self.dut.rst_125mhz.setimmediatevalue(0)
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk_125mhz)
+
+        self.dut.rst_125mhz.value = 1
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk_125mhz)
+
+        self.dut.rst_125mhz.value = 0
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk_125mhz)
+
+
+async def mac_test_10g(tb, source, sink):
+    tb.log.info("Test MAC")
+
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk_125mhz)
+
+    tb.log.info("Multiple small packets")
+
+    count = 64
+
+    pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
+
+    for p in pkts:
+        await source.send(XgmiiFrame.from_payload(p))
+
+    for k in range(count):
+        rx_frame = await sink.recv()
+
+        tb.log.info("RX frame: %s", rx_frame)
+
+        assert rx_frame.get_payload() == pkts[k]
+        assert rx_frame.check_fcs()
+
+    tb.log.info("Multiple large packets")
+
+    count = 32
+
+    pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
+
+    for p in pkts:
+        await source.send(XgmiiFrame.from_payload(p))
+
+    for k in range(count):
+        rx_frame = await sink.recv()
+
+        tb.log.info("RX frame: %s", rx_frame)
+
+        assert rx_frame.get_payload() == pkts[k]
+        assert rx_frame.check_fcs()
+
+    tb.log.info("MAC test done")
+
+
+@cocotb.test()
+async def run_test(dut):
+
+    tb = TB(dut)
+
+    await tb.init()
+
+    tests = []
+
+    for k in range(len(tb.sfp_sources)):
+        tb.log.info("Start SFP %d 10G MAC loopback test", k)
+        tests.append(cocotb.start_soon(mac_test_10g(tb, tb.sfp_sources[k], tb.sfp_sinks[k])))
+
+    await Combine(*tests)
+
+    await RisingEdge(dut.clk_125mhz)
+    await RisingEdge(dut.clk_125mhz)
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("sfp_rate", [0, 1])
+def test_fpga_core(request, sfp_rate):
+    dut = "fpga_core"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_fifo.f"),
+        os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"),
+        os.path.join(taxi_src_dir, "lss", "rtl", "taxi_i2c_master.sv"),
+        os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
+        os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['SIM'] = "1'b1"
+    parameters['VENDOR'] = "\"XILINX\""
+    parameters['FAMILY'] = "\"virtex7\""
+    parameters['CFG_LOW_LATENCY'] = "1'b1"
+    parameters['COMBINED_MAC_PCS'] = "1'b1"
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv

@@ -161,7 +161,7 @@ assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n;
 assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p;
 assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n;
 
-for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
 
     localparam CNT = 4;
 

src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -46,8 +47,7 @@ class TB:
         self.qsfp_sources = []
         self.qsfp_sinks = []
 
-        for inst in dut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64:

src/eth/example/VCU118/fpga/rtl/fpga_core.sv

@@ -550,7 +550,7 @@ assign qsfp_rx_n[4*1 +: 4] = qsfp2_rx_n;
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3",  "QSFP1.4"};
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3",  "QSFP2.4"};
 
-for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
 
     localparam CNT = 4;
 

src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -57,8 +58,7 @@ class TB:
         self.qsfp_sources = []
         self.qsfp_sinks = []
 
-        for inst in dut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64:

src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv

@@ -215,7 +215,7 @@ wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
 
 wire eth_gty_rst[GTY_CLK_CNT];
 
-for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
+for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gt_clk
 
     wire eth_gty_mgt_refclk_int;
 
@@ -277,7 +277,7 @@ localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "Q
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3",  "QSFP2.4"};
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP3[4] = '{"QSFP3.1", "QSFP3.2", "QSFP3.3",  "QSFP3.4"};
 
-for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
 
     localparam CNT = 4;
 

src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -52,8 +53,7 @@ class TB:
         for clk in dut.eth_gty_mgt_refclk_p:
             cocotb.start_soon(Clock(clk, 3.102, units="ns").start())
 
-        for inst in dut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64:

src/eth/example/fb2CG/fpga/rtl/fpga_core.sv

@@ -135,7 +135,7 @@ wire qsfp_mgt_refclk_bufg[2];
 
 wire qsfp_rst[2];
 
-for (genvar n = 0; n < 2; n = n + 1) begin : gty_clk
+for (genvar n = 0; n < 2; n = n + 1) begin : gt_clk
 
     wire qsfp_mgt_refclk_int;
 
@@ -192,7 +192,7 @@ assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n;
 assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p;
 assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n;
 
-for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
 
     localparam CLK = n;
     localparam CNT = 4;

src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -47,8 +48,7 @@ class TB:
         self.qsfp_sources = []
         self.qsfp_sinks = []
 
-        for inst in dut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64: