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121 lines
2.6 KiB
Systemverilog
121 lines
2.6 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream FIFO testbench
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*/
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module test_taxi_axis_fifo #
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(
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/* verilator lint_off WIDTHTRUNC */
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parameter DEPTH = 4096,
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parameter DATA_W = 8,
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parameter logic KEEP_EN = (DATA_W>8),
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parameter KEEP_W = ((DATA_W+7)/8),
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parameter logic STRB_EN = 1'b0,
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parameter logic LAST_EN = 1'b1,
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parameter logic ID_EN = 1'b0,
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parameter ID_W = 8,
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parameter logic DEST_EN = 1'b0,
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parameter DEST_W = 8,
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parameter logic USER_EN = 1'b1,
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parameter USER_W = 1,
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parameter RAM_PIPELINE = 1,
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parameter logic OUTPUT_FIFO_EN = 1'b0,
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parameter logic FRAME_FIFO = 1'b0,
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parameter logic [USER_W-1:0] USER_BAD_FRAME_VALUE = 1'b1,
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parameter logic [USER_W-1:0] USER_BAD_FRAME_MASK = 1'b1,
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parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
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parameter logic DROP_BAD_FRAME = 1'b0,
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parameter logic DROP_WHEN_FULL = 1'b0,
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parameter logic MARK_WHEN_FULL = 1'b0,
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parameter logic PAUSE_EN = 1'b0,
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parameter logic FRAME_PAUSE = FRAME_FIFO
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/* verilator lint_on WIDTHTRUNC */
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)
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();
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logic clk;
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logic rst;
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taxi_axis_if #(
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.DATA_W(DATA_W),
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.KEEP_EN(KEEP_EN),
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.KEEP_W(KEEP_W),
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.STRB_EN(STRB_EN),
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.LAST_EN(LAST_EN),
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.ID_EN(ID_EN),
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.ID_W(ID_W),
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.DEST_EN(DEST_EN),
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.DEST_W(DEST_W),
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.USER_EN(USER_EN),
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.USER_W(USER_W)
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) s_axis(), m_axis();
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logic pause_req;
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logic pause_ack;
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logic [$clog2(DEPTH):0] status_depth;
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logic [$clog2(DEPTH):0] status_depth_commit;
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logic status_overflow;
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logic status_bad_frame;
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logic status_good_frame;
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taxi_axis_fifo #(
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.DEPTH(DEPTH),
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.RAM_PIPELINE(RAM_PIPELINE),
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.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
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.FRAME_FIFO(FRAME_FIFO),
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.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
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.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
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.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
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.DROP_BAD_FRAME(DROP_BAD_FRAME),
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.DROP_WHEN_FULL(DROP_WHEN_FULL),
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.MARK_WHEN_FULL(MARK_WHEN_FULL),
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.PAUSE_EN(PAUSE_EN),
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.FRAME_PAUSE(FRAME_PAUSE)
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)
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uut (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4-Stream input (sink)
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*/
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.s_axis(s_axis),
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/*
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* AXI4-Stream output (source)
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*/
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.m_axis(m_axis),
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/*
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* Pause
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*/
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.pause_req(pause_req),
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.pause_ack(pause_ack),
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/*
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* Status
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*/
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.status_depth(status_depth),
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.status_depth_commit(status_depth_commit),
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.status_overflow(status_overflow),
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.status_bad_frame(status_bad_frame),
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.status_good_frame(status_good_frame)
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);
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endmodule
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`resetall
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