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17 lines
428 B
Tcl
17 lines
428 B
Tcl
# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# Ethernet constraints
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# IDELAY from PHY chip (RGMII)
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set_property DELAY_VALUE 0 [get_cells {phy2_rx_ctl_idelay phy2_rxd_idelay_bit[*].idelay_inst}]
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set_property DELAY_VALUE 0 [get_cells {phy3_rx_ctl_idelay phy3_rxd_idelay_bit[*].idelay_inst}]
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# MMCM phase (RGMII)
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set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]
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