mirror of
https://github.com/fpganinja/taxi.git
synced 2025-12-09 08:58:40 -08:00
344 lines
11 KiB
Systemverilog
344 lines
11 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2015-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* PTP clock module
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*/
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module taxi_ptp_clock #
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(
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parameter PERIOD_NS_W = 4,
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parameter OFFSET_NS_W = 4,
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parameter FNS_W = 16,
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parameter PERIOD_NS_NUM = 32,
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parameter PERIOD_NS_DENOM = 5,
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parameter PIPELINE_OUTPUT = 0
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* Timestamp inputs for synchronization
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*/
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input wire logic [95:0] input_ts_tod,
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input wire logic input_ts_tod_valid,
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input wire logic [63:0] input_ts_rel,
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input wire logic input_ts_rel_valid,
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/*
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* Period adjustment
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*/
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input wire logic [PERIOD_NS_W-1:0] input_period_ns,
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input wire logic [FNS_W-1:0] input_period_fns,
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input wire logic input_period_valid,
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/*
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* Offset adjustment
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*/
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input wire logic [OFFSET_NS_W-1:0] input_adj_ns,
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input wire logic [FNS_W-1:0] input_adj_fns,
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input wire logic [15:0] input_adj_count,
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input wire logic input_adj_valid,
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output wire logic input_adj_active,
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/*
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* Drift adjustment
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*/
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input wire logic [FNS_W-1:0] input_drift_num,
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input wire logic [15:0] input_drift_denom,
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input wire logic input_drift_valid,
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/*
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* Timestamp outputs
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*/
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output wire logic [95:0] output_ts_tod,
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output wire logic output_ts_tod_step,
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output wire logic [63:0] output_ts_rel,
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output wire logic output_ts_rel_step,
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/*
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* PPS output
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*/
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output wire logic output_pps,
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output wire logic output_pps_str
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);
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localparam PERIOD_NS = PERIOD_NS_NUM / PERIOD_NS_DENOM;
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localparam PERIOD_NS_REM = PERIOD_NS_NUM - PERIOD_NS*PERIOD_NS_DENOM;
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localparam PERIOD_FNS = (PERIOD_NS_REM * {32'd1, {FNS_W{1'b0}}}) / (32+FNS_W)'(PERIOD_NS_DENOM);
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localparam PERIOD_FNS_REM = (PERIOD_NS_REM * {32'd1, {FNS_W{1'b0}}}) - PERIOD_FNS*PERIOD_NS_DENOM;
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localparam INC_NS_W = $clog2(2**PERIOD_NS_W + 2**OFFSET_NS_W);
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localparam [30:0] NS_PER_S = 31'd1_000_000_000;
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logic [PERIOD_NS_W-1:0] period_ns_reg = PERIOD_NS_W'(PERIOD_NS);
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logic [FNS_W-1:0] period_fns_reg = FNS_W'(PERIOD_FNS);
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logic [OFFSET_NS_W-1:0] adj_ns_reg = '0;
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logic [FNS_W-1:0] adj_fns_reg = '0;
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logic [15:0] adj_count_reg = '0;
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logic adj_active_reg = '0;
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logic [FNS_W-1:0] drift_num_reg = FNS_W'(PERIOD_FNS_REM);
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logic [15:0] drift_denom_reg = 16'(PERIOD_NS_DENOM);
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logic [15:0] drift_cnt_reg = '0;
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logic drift_apply_reg = 1'b0;
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logic [INC_NS_W-1:0] ts_inc_ns_reg = '0;
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logic [FNS_W-1:0] ts_inc_fns_reg = '0;
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logic [INC_NS_W-1:0] ts_inc_ns_delay_reg = '0;
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logic [FNS_W-1:0] ts_inc_fns_delay_reg = '0;
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logic [30:0] ts_inc_ns_ovf_reg = '0;
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logic [FNS_W-1:0] ts_inc_fns_ovf_reg = '0;
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logic [47:0] ts_tod_s_reg = '0;
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logic [29:0] ts_tod_ns_reg = '0;
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logic [FNS_W-1:0] ts_tod_fns_reg = '0;
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logic [29:0] ts_tod_ns_inc_reg = '0;
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logic [FNS_W-1:0] ts_tod_fns_inc_reg = '0;
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logic [30:0] ts_tod_ns_ovf_reg = '1;
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logic [FNS_W-1:0] ts_tod_fns_ovf_reg = '1;
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logic [47:0] ts_rel_ns_reg = '0;
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logic [FNS_W-1:0] ts_rel_fns_reg = '0;
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logic ts_tod_step_reg = 1'b0;
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logic ts_rel_step_reg = 1'b0;
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logic [47:0] temp;
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logic pps_reg = 0;
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logic pps_str_reg = 0;
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assign input_adj_active = adj_active_reg;
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if (PIPELINE_OUTPUT > 0) begin
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// pipeline
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(* shreg_extract = "no" *)
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logic [95:0] output_ts_tod_reg[0:PIPELINE_OUTPUT-1];
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(* shreg_extract = "no" *)
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logic output_ts_tod_step_reg[0:PIPELINE_OUTPUT-1];
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(* shreg_extract = "no" *)
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logic [63:0] output_ts_rel_reg[0:PIPELINE_OUTPUT-1];
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(* shreg_extract = "no" *)
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logic output_ts_rel_step_reg[0:PIPELINE_OUTPUT-1];
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(* shreg_extract = "no" *)
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logic output_pps_reg[0:PIPELINE_OUTPUT-1];
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(* shreg_extract = "no" *)
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logic output_pps_str_reg[0:PIPELINE_OUTPUT-1];
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assign output_ts_tod = output_ts_tod_reg[PIPELINE_OUTPUT-1];
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assign output_ts_tod_step = output_ts_tod_step_reg[PIPELINE_OUTPUT-1];
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assign output_ts_rel = output_ts_rel_reg[PIPELINE_OUTPUT-1];
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assign output_ts_rel_step = output_ts_rel_step_reg[PIPELINE_OUTPUT-1];
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assign output_pps = output_pps_reg[PIPELINE_OUTPUT-1];
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assign output_pps_str = output_pps_str_reg[PIPELINE_OUTPUT-1];
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initial begin
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for (integer i = 0; i < PIPELINE_OUTPUT; i = i + 1) begin
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output_ts_tod_reg[i] = '0;
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output_ts_tod_step_reg[i] = 1'b0;
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output_ts_rel_reg[i] = '0;
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output_ts_rel_step_reg[i] = 1'b0;
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output_pps_reg[i] = 1'b0;
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output_pps_str_reg[i] = 1'b0;
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end
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end
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always_ff @(posedge clk) begin
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output_ts_tod_reg[0][95:48] <= ts_tod_s_reg;
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output_ts_tod_reg[0][47:46] <= 2'b00;
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output_ts_tod_reg[0][45:16] <= ts_tod_ns_reg;
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output_ts_tod_reg[0][15:0] <= {ts_tod_fns_reg, 16'd0} >> FNS_W;
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output_ts_tod_step_reg[0] <= ts_tod_step_reg;
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output_ts_rel_reg[0][63:16] <= ts_rel_ns_reg;
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output_ts_rel_reg[0][15:0] <= {ts_rel_fns_reg, 16'd0} >> FNS_W;
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output_ts_rel_step_reg[0] <= ts_rel_step_reg;
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output_pps_reg[0] <= pps_reg;
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output_pps_str_reg[0] <= pps_str_reg;
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for (integer i = 0; i < PIPELINE_OUTPUT-1; i = i + 1) begin
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output_ts_tod_reg[i+1] <= output_ts_tod_reg[i];
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output_ts_tod_step_reg[i+1] <= output_ts_tod_step_reg[i];
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output_ts_rel_reg[i+1] <= output_ts_rel_reg[i];
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output_ts_rel_step_reg[i+1] <= output_ts_rel_step_reg[i];
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output_pps_reg[i+1] <= output_pps_reg[i];
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output_pps_str_reg[i+1] <= output_pps_str_reg[i];
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end
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if (rst) begin
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for (integer i = 0; i < PIPELINE_OUTPUT; i = i + 1) begin
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output_ts_tod_reg[i] <= '0;
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output_ts_tod_step_reg[i] <= 1'b0;
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output_ts_rel_reg[i] <= '0;
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output_ts_rel_step_reg[i] <= 1'b0;
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output_pps_reg[i] <= 1'b0;
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output_pps_str_reg[i] <= 1'b0;
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end
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end
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end
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end else begin
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assign output_ts_tod[95:48] = ts_tod_s_reg;
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assign output_ts_tod[47:46] = 2'b00;
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assign output_ts_tod[45:16] = ts_tod_ns_reg;
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assign output_ts_tod[15:0] = 16'({ts_tod_fns_reg, 16'd0} >> FNS_W);
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assign output_ts_tod_step = ts_tod_step_reg;
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assign output_ts_rel[63:16] = ts_rel_ns_reg;
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assign output_ts_rel[15:0] = 16'({ts_rel_fns_reg, 16'd0} >> FNS_W);
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assign output_ts_rel_step = ts_rel_step_reg;
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assign output_pps = pps_reg;
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assign output_pps_str = pps_str_reg;
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end
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always_ff @(posedge clk) begin
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ts_tod_step_reg <= 1'b0;
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ts_rel_step_reg <= 1'b0;
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drift_apply_reg <= 1'b0;
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pps_reg <= 1'b0;
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// latch parameters
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if (input_period_valid) begin
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period_ns_reg <= input_period_ns;
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period_fns_reg <= input_period_fns;
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end
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if (input_adj_valid) begin
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adj_ns_reg <= input_adj_ns;
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adj_fns_reg <= input_adj_fns;
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adj_count_reg <= input_adj_count;
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end
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if (input_drift_valid) begin
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drift_num_reg <= input_drift_num;
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drift_denom_reg <= input_drift_denom;
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end
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// timestamp increment calculation
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{ts_inc_ns_reg, ts_inc_fns_reg} <= $signed({1'b0, period_ns_reg, period_fns_reg}) +
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(adj_active_reg ? (INC_NS_W+FNS_W)'($signed({adj_ns_reg, adj_fns_reg})) : '0) +
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(drift_apply_reg ? (INC_NS_W+FNS_W)'($signed(drift_num_reg)) : '0);
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// offset adjust counter
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if (adj_count_reg != 0) begin
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adj_count_reg <= adj_count_reg - 1;
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adj_active_reg <= 1;
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ts_tod_step_reg <= 1;
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ts_rel_step_reg <= 1;
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end else begin
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adj_active_reg <= 0;
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end
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// drift counter
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if (drift_cnt_reg != 0) begin
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drift_cnt_reg <= drift_cnt_reg - 1;
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end else begin
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drift_cnt_reg <= drift_denom_reg-1;
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drift_apply_reg <= 1'b1;
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end
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// 96 bit timestamp
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{ts_inc_ns_delay_reg, ts_inc_fns_delay_reg} <= {ts_inc_ns_reg, ts_inc_fns_reg};
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{ts_inc_ns_ovf_reg, ts_inc_fns_ovf_reg} <= {NS_PER_S, {FNS_W{1'b0}}} - (31+FNS_W)'({ts_inc_ns_reg, ts_inc_fns_reg});
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{ts_tod_ns_inc_reg, ts_tod_fns_inc_reg} <= {ts_tod_ns_inc_reg, ts_tod_fns_inc_reg} + (30+FNS_W)'({ts_inc_ns_delay_reg, ts_inc_fns_delay_reg});
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{ts_tod_ns_ovf_reg, ts_tod_fns_ovf_reg} <= {ts_tod_ns_inc_reg, ts_tod_fns_inc_reg} - (31+FNS_W)'({ts_inc_ns_ovf_reg[29:0], ts_inc_fns_ovf_reg});
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{ts_tod_ns_reg, ts_tod_fns_reg} <= {ts_tod_ns_inc_reg, ts_tod_fns_inc_reg};
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if (ts_tod_ns_reg[29]) begin
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pps_str_reg <= 1'b0;
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end
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if (!ts_tod_ns_ovf_reg[30]) begin
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// if the overflow lookahead did not borrow, one second has elapsed
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// increment seconds field, pre-compute normal increment, force overflow lookahead borrow bit set
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{ts_tod_ns_inc_reg, ts_tod_fns_inc_reg} <= (30+FNS_W)'({ts_tod_ns_ovf_reg[29:0], ts_tod_fns_ovf_reg} + {ts_inc_ns_delay_reg, ts_inc_fns_delay_reg});
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ts_tod_ns_ovf_reg[30] <= 1'b1;
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{ts_tod_ns_reg, ts_tod_fns_reg} <= {ts_tod_ns_ovf_reg[29:0], ts_tod_fns_ovf_reg};
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ts_tod_s_reg <= ts_tod_s_reg + 1;
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pps_reg <= 1'b1;
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pps_str_reg <= 1'b1;
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end
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if (input_ts_tod_valid) begin
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// load timestamp
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ts_tod_s_reg <= input_ts_tod[95:48];
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ts_tod_ns_reg <= input_ts_tod[45:16];
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ts_tod_ns_inc_reg <= input_ts_tod[45:16];
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ts_tod_ns_ovf_reg[30] <= 1'b1;
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ts_tod_fns_reg <= FNS_W > 16 ? input_ts_tod[15:0] << (FNS_W-16) : input_ts_tod[15:0] >> (16-FNS_W);
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ts_tod_fns_inc_reg <= FNS_W > 16 ? input_ts_tod[15:0] << (FNS_W-16) : input_ts_tod[15:0] >> (16-FNS_W);
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ts_tod_step_reg <= 1;
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end
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// 64 bit timestamp
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{ts_rel_ns_reg, ts_rel_fns_reg} <= {ts_rel_ns_reg, ts_rel_fns_reg} + (48+FNS_W)'({ts_inc_ns_reg, ts_inc_fns_reg});
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if (input_ts_rel_valid) begin
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// load timestamp
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{ts_rel_ns_reg, ts_rel_fns_reg} <= input_ts_rel;
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ts_rel_step_reg <= 1;
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end
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if (rst) begin
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period_ns_reg <= PERIOD_NS_W'(PERIOD_NS);
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period_fns_reg <= FNS_W'(PERIOD_FNS);
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adj_ns_reg <= '0;
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adj_fns_reg <= '0;
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adj_count_reg <= '0;
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adj_active_reg <= '0;
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drift_num_reg <= FNS_W'(PERIOD_FNS_REM);
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drift_denom_reg <= 16'(PERIOD_NS_DENOM);
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drift_cnt_reg <= '0;
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drift_apply_reg <= 1'b0;
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ts_tod_s_reg <= '0;
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ts_tod_ns_reg <= '0;
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ts_tod_fns_reg <= '0;
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ts_tod_ns_inc_reg <= '0;
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ts_tod_fns_inc_reg <= '0;
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ts_tod_ns_ovf_reg[30] <= 1'b1;
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ts_tod_step_reg <= '0;
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ts_rel_ns_reg <= '0;
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ts_rel_fns_reg <= '0;
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ts_rel_step_reg <= '0;
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pps_reg <= '0;
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pps_str_reg <= '0;
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end
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end
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endmodule
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`resetall
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