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67 lines
3.2 KiB
Tcl
67 lines
3.2 KiB
Tcl
# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2014-2026 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# XDC constraints for the Digilent Arty board
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# part: xc7a35t-csg324-1
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# LEDs
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set_property -dict {LOC G6 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led0_r]
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set_property -dict {LOC F6 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led0_g]
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set_property -dict {LOC E1 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led0_b]
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set_property -dict {LOC G3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led1_r]
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set_property -dict {LOC J4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led1_g]
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set_property -dict {LOC G4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led1_b]
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set_property -dict {LOC J3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led2_r]
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set_property -dict {LOC J2 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led2_g]
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set_property -dict {LOC H4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led2_b]
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set_property -dict {LOC K1 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led3_r]
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set_property -dict {LOC H6 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led3_g]
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set_property -dict {LOC K2 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led3_b]
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set_property -dict {LOC H5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led4]
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set_property -dict {LOC J5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led5]
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set_property -dict {LOC T9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led6]
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set_property -dict {LOC T10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led7]
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set_false_path -to [get_ports {led0_r led0_g led0_b led1_r led1_g led1_b led2_r led2_g led2_b led3_r led3_g led3_b led4 led5 led6 led7}]
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set_output_delay 0 [get_ports {led0_r led0_g led0_b led1_r led1_g led1_b led2_r led2_g led2_b led3_r led3_g led3_b led4 led5 led6 led7}]
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# Reset button
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# Note: IC8.43 BDBUS4 DTR drives FPGA pin C2 (reset_n) via JP2
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set_property -dict {LOC C2 IOSTANDARD LVCMOS33} [get_ports reset_n]
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set_false_path -from [get_ports {reset_n}]
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set_input_delay 0 [get_ports {reset_n}]
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# Push buttons
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set_property -dict {LOC D9 IOSTANDARD LVCMOS33} [get_ports {btn[0]}]
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set_property -dict {LOC C9 IOSTANDARD LVCMOS33} [get_ports {btn[1]}]
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set_property -dict {LOC B9 IOSTANDARD LVCMOS33} [get_ports {btn[2]}]
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set_property -dict {LOC B8 IOSTANDARD LVCMOS33} [get_ports {btn[3]}]
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set_false_path -from [get_ports {btn[*]}]
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set_input_delay 0 [get_ports {btn[*]}]
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# Toggle switches
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set_property -dict {LOC A8 IOSTANDARD LVCMOS33} [get_ports {sw[0]}]
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set_property -dict {LOC C11 IOSTANDARD LVCMOS33} [get_ports {sw[1]}]
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set_property -dict {LOC C10 IOSTANDARD LVCMOS33} [get_ports {sw[2]}]
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set_property -dict {LOC A10 IOSTANDARD LVCMOS33} [get_ports {sw[3]}]
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set_false_path -from [get_ports {sw[*]}]
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set_input_delay 0 [get_ports {sw[*]}]
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# UART (IC8 FT2232H BDBUS)
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# Note: IC8.43 BDBUS4 DTR drives FPGA pin C2 (reset_n) via JP2
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set_property -dict {LOC D10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports uart_txd] ;# IC8.39 BDBUS1 RXD
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set_property -dict {LOC A9 IOSTANDARD LVCMOS33} [get_ports uart_rxd] ;# IC8.38 BDBUS0 TXD
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set_false_path -to [get_ports {uart_txd}]
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set_output_delay 0 [get_ports {uart_txd}]
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set_false_path -from [get_ports {uart_rxd}]
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set_input_delay 0 [get_ports {uart_rxd}]
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