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https://github.com/fpganinja/taxi.git
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548 lines
15 KiB
Systemverilog
548 lines
15 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Corundum-micro core logic
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*/
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module cndm_micro_core #(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter string VENDOR = "XILINX",
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// device family
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parameter string FAMILY = "virtexuplus",
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// FW ID
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parameter FPGA_ID = 32'hDEADBEEF,
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parameter FW_ID = 32'h0000C001,
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parameter FW_VER = 32'h000_01_000,
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parameter BOARD_ID = 32'h1234_0000,
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parameter BOARD_VER = 32'h001_00_000,
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parameter BUILD_DATE = 32'd602976000,
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parameter GIT_HASH = 32'h5f87c2e8,
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parameter RELEASE_INFO = 32'h00000000,
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// Structural configuration
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parameter PORTS = 2,
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// PTP configuration
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parameter logic PTP_TS_EN = 1'b1,
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parameter logic PTP_TS_FMT_TOD = 1'b0,
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parameter PTP_CLK_PER_NS_NUM = 512,
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parameter PTP_CLK_PER_NS_DENOM = 165
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* Control register interface
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*/
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taxi_axil_if.wr_slv s_axil_ctrl_wr,
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taxi_axil_if.rd_slv s_axil_ctrl_rd,
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/*
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* DMA
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*/
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taxi_dma_desc_if.req_src dma_rd_desc_req,
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taxi_dma_desc_if.sts_snk dma_rd_desc_sts,
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taxi_dma_desc_if.req_src dma_wr_desc_req,
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taxi_dma_desc_if.sts_snk dma_wr_desc_sts,
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taxi_dma_ram_if.wr_slv dma_ram_wr,
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taxi_dma_ram_if.rd_slv dma_ram_rd,
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output wire logic [PORTS-1:0] irq,
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/*
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* PTP
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*/
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input wire logic ptp_clk = 1'b0,
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input wire logic ptp_rst = 1'b0,
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input wire logic ptp_sample_clk = 1'b0,
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input wire logic ptp_td_sdi = 1'b0,
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output wire logic ptp_td_sdo,
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output wire logic ptp_pps,
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output wire logic ptp_pps_str,
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output wire logic ptp_sync_locked,
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output wire logic [63:0] ptp_sync_ts_rel,
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output wire logic ptp_sync_ts_rel_step,
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output wire logic [95:0] ptp_sync_ts_tod,
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output wire logic ptp_sync_ts_tod_step,
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output wire logic ptp_sync_pps,
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output wire logic ptp_sync_pps_str,
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/*
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* Ethernet
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*/
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input wire logic mac_tx_clk[PORTS],
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input wire logic mac_tx_rst[PORTS],
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taxi_axis_if.src mac_axis_tx[PORTS],
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taxi_axis_if.snk mac_axis_tx_cpl[PORTS],
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input wire logic mac_rx_clk[PORTS],
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input wire logic mac_rx_rst[PORTS],
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taxi_axis_if.snk mac_axis_rx[PORTS]
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);
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localparam CL_PORTS = $clog2(PORTS);
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localparam AXIL_ADDR_W = s_axil_ctrl_wr.ADDR_W;
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localparam AXIL_DATA_W = s_axil_ctrl_wr.DATA_W;
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localparam RAM_SEGS = dma_ram_wr.SEGS;
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localparam RAM_SEG_ADDR_W = dma_ram_wr.SEG_ADDR_W;
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localparam RAM_SEG_DATA_W = dma_ram_wr.SEG_DATA_W;
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localparam RAM_SEG_BE_W = dma_ram_wr.SEG_BE_W;
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localparam RAM_SEL_W = dma_ram_wr.SEL_W;
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localparam PORT_OFFSET_DP = PTP_TS_EN ? 1 : 0;
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localparam PORT_OFFSET_HOST = 2;
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localparam PORT_BASE_ADDR_DP = PTP_TS_EN ? 32'h00010000 : 32'h00000000;
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localparam PORT_BASE_ADDR_HOST = 32'h00020000;
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taxi_axil_if #(
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.DATA_W(s_axil_ctrl_wr.DATA_W),
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.ADDR_W(16),
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.STRB_W(s_axil_ctrl_wr.STRB_W),
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.AWUSER_EN(s_axil_ctrl_wr.AWUSER_EN),
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.AWUSER_W(s_axil_ctrl_wr.AWUSER_W),
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.WUSER_EN(s_axil_ctrl_wr.WUSER_EN),
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.WUSER_W(s_axil_ctrl_wr.WUSER_W),
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.BUSER_EN(s_axil_ctrl_wr.BUSER_EN),
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.BUSER_W(s_axil_ctrl_wr.BUSER_W),
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.ARUSER_EN(s_axil_ctrl_wr.ARUSER_EN),
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.ARUSER_W(s_axil_ctrl_wr.ARUSER_W),
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.RUSER_EN(s_axil_ctrl_wr.RUSER_EN),
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.RUSER_W(s_axil_ctrl_wr.RUSER_W)
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)
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axil_ctrl[PORTS+PORT_OFFSET_HOST]();
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taxi_axil_interconnect_1s #(
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.M_COUNT($size(axil_ctrl)),
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.ADDR_W(s_axil_ctrl_wr.ADDR_W),
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.M_REGIONS(1),
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.M_BASE_ADDR('0),
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.M_ADDR_W({$size(axil_ctrl){{1{32'd16}}}}),
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.M_SECURE({$size(axil_ctrl){1'b0}})
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)
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port_intercon_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4-lite slave interface
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*/
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.s_axil_wr(s_axil_ctrl_wr),
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.s_axil_rd(s_axil_ctrl_rd),
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/*
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* AXI4-lite master interfaces
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*/
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.m_axil_wr(axil_ctrl),
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.m_axil_rd(axil_ctrl)
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);
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logic s_axil_awready_reg = 1'b0;
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logic s_axil_wready_reg = 1'b0;
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logic s_axil_bvalid_reg = 1'b0;
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logic s_axil_arready_reg = 1'b0;
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logic [AXIL_DATA_W-1:0] s_axil_rdata_reg = '0;
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logic s_axil_rvalid_reg = 1'b0;
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assign axil_ctrl[0].awready = s_axil_awready_reg;
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assign axil_ctrl[0].wready = s_axil_wready_reg;
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assign axil_ctrl[0].bresp = '0;
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assign axil_ctrl[0].buser = '0;
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assign axil_ctrl[0].bvalid = s_axil_bvalid_reg;
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assign axil_ctrl[0].arready = s_axil_arready_reg;
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assign axil_ctrl[0].rdata = s_axil_rdata_reg;
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assign axil_ctrl[0].rresp = '0;
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assign axil_ctrl[0].ruser = '0;
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assign axil_ctrl[0].rvalid = s_axil_rvalid_reg;
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logic cmd_mbox_start_reg = 1'b0;
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wire cmd_mbox_busy;
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logic [95:0] get_ptp_ts_tod_reg = '0;
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logic [63:0] get_ptp_ts_rel_reg = '0;
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always_ff @(posedge clk) begin
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s_axil_awready_reg <= 1'b0;
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s_axil_wready_reg <= 1'b0;
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s_axil_bvalid_reg <= s_axil_bvalid_reg && !axil_ctrl[0].bready;
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s_axil_arready_reg <= 1'b0;
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s_axil_rvalid_reg <= s_axil_rvalid_reg && !axil_ctrl[0].rready;
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cmd_mbox_start_reg <= 1'b0;
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if (axil_ctrl[0].awvalid && axil_ctrl[0].wvalid && !s_axil_bvalid_reg) begin
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s_axil_awready_reg <= 1'b1;
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s_axil_wready_reg <= 1'b1;
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s_axil_bvalid_reg <= 1'b1;
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case ({axil_ctrl[0].awaddr[15:2], 2'b00})
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// 16'h0100: begin
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// txq_en_reg <= axil_ctrl[0].wdata[0];
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// txq_size_reg <= axil_ctrl[0].wdata[19:16];
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// end
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// 16'h0104: txq_prod_reg <= axil_ctrl[0].wdata[15:0];
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// 16'h0108: txq_base_addr_reg[31:0] <= axil_ctrl[0].wdata;
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// 16'h010c: txq_base_addr_reg[63:32] <= axil_ctrl[0].wdata;
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16'h0200: begin
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cmd_mbox_start_reg <= axil_ctrl[0].wdata[0];
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end
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default: begin end
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endcase
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end
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if (axil_ctrl[0].arvalid && !s_axil_rvalid_reg) begin
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s_axil_rdata_reg <= '0;
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s_axil_arready_reg <= 1'b1;
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s_axil_rvalid_reg <= 1'b1;
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case ({axil_ctrl[0].araddr[15:2], 2'b00})
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16'h0100: s_axil_rdata_reg <= PORTS; // port count
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16'h0200: begin
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s_axil_rdata_reg[0] <= cmd_mbox_busy;
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end
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16'h0300: s_axil_rdata_reg <= {ptp_sync_ts_tod[15:0], 16'd0}; // PTP cur fns
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16'h0304: s_axil_rdata_reg <= ptp_sync_ts_tod[47:16]; // PTP cur ToD ns
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16'h0308: s_axil_rdata_reg <= ptp_sync_ts_tod[79:48]; // PTP cur ToD sec l
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16'h030C: s_axil_rdata_reg <= 32'(ptp_sync_ts_tod[95:80]); // PTP cur ToD sec h
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16'h0310: s_axil_rdata_reg <= ptp_sync_ts_rel[47:16]; // PTP cur rel ns l
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16'h0314: s_axil_rdata_reg <= 32'(ptp_sync_ts_rel[63:48]); // PTP cur rel ns h
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16'h0318: s_axil_rdata_reg <= '0; // PTP cur PTM l
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16'h031C: s_axil_rdata_reg <= '0; // PTP cur PTM h
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16'h0320: begin
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// PTP snapshot fns
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get_ptp_ts_tod_reg <= ptp_sync_ts_tod;
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get_ptp_ts_rel_reg <= ptp_sync_ts_rel;
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s_axil_rdata_reg <= {ptp_sync_ts_tod[15:0], 16'd0};
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end
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16'h0324: s_axil_rdata_reg <= 32'(get_ptp_ts_tod_reg[45:16]); // PTP snapshot ToD ns
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16'h0328: s_axil_rdata_reg <= get_ptp_ts_tod_reg[79:48]; // PTP snapshot ToD sec l
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16'h032C: s_axil_rdata_reg <= 32'(get_ptp_ts_tod_reg[95:80]); // PTP snapshot ToD sec h
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16'h0330: s_axil_rdata_reg <= get_ptp_ts_rel_reg[47:16]; // PTP snapshot rel ns l
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16'h0334: s_axil_rdata_reg <= 32'(get_ptp_ts_rel_reg[63:48]); // PTP snapshot rel ns h
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16'h0338: s_axil_rdata_reg <= '0; // PTP snapshot PTM l
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16'h033C: s_axil_rdata_reg <= '0; // PTP snapshot PTM h
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default: begin end
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endcase
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end
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if (rst) begin
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s_axil_awready_reg <= 1'b0;
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s_axil_wready_reg <= 1'b0;
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s_axil_bvalid_reg <= 1'b0;
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s_axil_arready_reg <= 1'b0;
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s_axil_rvalid_reg <= 1'b0;
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end
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end
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// command mailbox
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taxi_axis_if #(
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.DATA_W(32),
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.KEEP_EN(1),
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.LAST_EN(1),
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.ID_EN(0),
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.DEST_EN(0),
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.USER_EN(0)
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) axis_cmd();
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taxi_axis_if #(
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.DATA_W(32),
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.KEEP_EN(1),
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.LAST_EN(1),
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.ID_EN(0),
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.DEST_EN(0),
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.USER_EN(0)
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) axis_rsp();
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cndm_micro_cmd_mbox
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cmd_mbox_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI lite interface
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*/
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.s_axil_wr(axil_ctrl[1]),
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.s_axil_rd(axil_ctrl[1]),
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/*
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* Control
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*/
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.start(cmd_mbox_start_reg),
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.busy(cmd_mbox_busy),
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/*
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* Command interface
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*/
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.m_axis_cmd(axis_cmd),
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.s_axis_rsp(axis_rsp)
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);
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// datapath manager
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taxi_apb_if #(
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.DATA_W(32),
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.ADDR_W(16+$clog2(PORTS+PORT_OFFSET_DP))
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)
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apb_dp_ctrl();
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cndm_micro_dp_mgr #(
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.PORTS(PORTS),
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.PTP_EN(PTP_TS_EN),
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.PTP_BASE_ADDR_DP(0),
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.PORT_BASE_ADDR_DP(PORT_BASE_ADDR_DP),
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.PORT_BASE_ADDR_HOST(PORT_BASE_ADDR_HOST)
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)
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dp_mgr_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Command interface
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*/
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.s_axis_cmd(axis_cmd),
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.m_axis_rsp(axis_rsp),
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/*
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* APB master interface (datapath control)
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*/
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.m_apb_dp_ctrl(apb_dp_ctrl)
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);
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taxi_apb_if #(
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.DATA_W(32),
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.ADDR_W(16)
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)
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apb_port_dp_ctrl[PORT_OFFSET_DP+PORTS]();
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taxi_apb_interconnect #(
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.M_CNT($size(apb_port_dp_ctrl)),
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.ADDR_W(apb_dp_ctrl.ADDR_W),
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.M_REGIONS(1),
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.M_BASE_ADDR('0),
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.M_ADDR_W({$size(apb_port_dp_ctrl){{1{32'd16}}}}),
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.M_SECURE({$size(apb_port_dp_ctrl){1'b0}})
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)
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port_dp_intercon_inst (
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.clk(clk),
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.rst(rst),
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/*
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* APB slave interface
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*/
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.s_apb(apb_dp_ctrl),
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/*
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* APB master interfaces
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*/
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.m_apb(apb_port_dp_ctrl)
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);
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if (PTP_TS_EN) begin : ptp
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taxi_ptp_td_phc_apb #(
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.PTP_CLK_PER_NS_NUM(PTP_CLK_PER_NS_NUM),
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.PTP_CLK_PER_NS_DENOM(PTP_CLK_PER_NS_DENOM)
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)
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ptp_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Control register interface
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*/
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.s_apb(apb_port_dp_ctrl[0]),
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/*
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* PTP
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*/
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.ptp_clk(ptp_clk),
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.ptp_rst(ptp_rst),
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.ptp_sample_clk(ptp_sample_clk),
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.ptp_td_sdo(ptp_td_sdo),
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.ptp_pps(ptp_pps),
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.ptp_pps_str(ptp_pps_str),
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.ptp_sync_locked(ptp_sync_locked),
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.ptp_sync_ts_rel(ptp_sync_ts_rel),
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.ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
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.ptp_sync_ts_tod(ptp_sync_ts_tod),
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.ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
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.ptp_sync_pps(ptp_sync_pps),
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.ptp_sync_pps_str(ptp_sync_pps_str)
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);
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end else begin : ptp
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assign ptp_td_sdo = 1'b0;
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assign ptp_pps = 1'b0;
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assign ptp_pps_str = 1'b0;
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assign ptp_sync_locked = 1'b0;
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assign ptp_sync_ts_rel = '0;
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assign ptp_sync_ts_rel_step = 1'b0;
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assign ptp_sync_ts_tod = '0;
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assign ptp_sync_ts_tod_step = 1'b0;
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assign ptp_sync_pps = 1'b0;
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assign ptp_sync_pps_str = 1'b0;
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end
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taxi_dma_desc_if #(
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.SRC_ADDR_W(dma_rd_desc_req.SRC_ADDR_W),
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.SRC_SEL_EN(dma_rd_desc_req.SRC_SEL_EN),
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.SRC_SEL_W(dma_rd_desc_req.SRC_SEL_W),
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.SRC_ASID_EN(dma_rd_desc_req.SRC_ASID_EN),
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.DST_ADDR_W(dma_rd_desc_req.DST_ADDR_W),
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.DST_SEL_EN(dma_rd_desc_req.DST_SEL_EN),
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.DST_SEL_W(dma_rd_desc_req.DST_SEL_W-CL_PORTS),
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.DST_ASID_EN(dma_rd_desc_req.DST_ASID_EN),
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.IMM_EN(dma_rd_desc_req.IMM_EN),
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.LEN_W(dma_rd_desc_req.LEN_W),
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.TAG_W(dma_rd_desc_req.TAG_W-CL_PORTS),
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.ID_EN(dma_rd_desc_req.ID_EN),
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.DEST_EN(dma_rd_desc_req.DEST_EN),
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.USER_EN(dma_rd_desc_req.USER_EN)
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) dma_rd_desc_int[PORTS]();
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taxi_dma_desc_if #(
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.SRC_ADDR_W(dma_wr_desc_req.SRC_ADDR_W),
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.SRC_SEL_EN(dma_wr_desc_req.SRC_SEL_EN),
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.SRC_SEL_W(dma_wr_desc_req.SRC_SEL_W-CL_PORTS),
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.SRC_ASID_EN(dma_wr_desc_req.SRC_ASID_EN),
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.DST_ADDR_W(dma_wr_desc_req.DST_ADDR_W),
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.DST_SEL_EN(dma_wr_desc_req.DST_SEL_EN),
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.DST_SEL_W(dma_wr_desc_req.DST_SEL_W),
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.DST_ASID_EN(dma_wr_desc_req.DST_ASID_EN),
|
|
.IMM_EN(dma_wr_desc_req.IMM_EN),
|
|
.IMM_W(dma_wr_desc_req.IMM_W),
|
|
.LEN_W(dma_wr_desc_req.LEN_W),
|
|
.TAG_W(dma_wr_desc_req.TAG_W-CL_PORTS),
|
|
.ID_EN(dma_wr_desc_req.ID_EN),
|
|
.DEST_EN(dma_wr_desc_req.DEST_EN),
|
|
.USER_EN(dma_wr_desc_req.USER_EN)
|
|
) dma_wr_desc_int[PORTS]();
|
|
|
|
taxi_dma_ram_if #(
|
|
.SEGS(RAM_SEGS),
|
|
.SEG_ADDR_W(RAM_SEG_ADDR_W),
|
|
.SEG_DATA_W(RAM_SEG_DATA_W),
|
|
.SEG_BE_W(RAM_SEG_BE_W),
|
|
.SEL_W(RAM_SEL_W-CL_PORTS)
|
|
) dma_ram_int[PORTS]();
|
|
|
|
taxi_dma_if_mux #(
|
|
.PORTS(PORTS),
|
|
.ARB_ROUND_ROBIN(1),
|
|
.ARB_LSB_HIGH_PRIO(1)
|
|
)
|
|
dma_mux_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* DMA descriptors from clients
|
|
*/
|
|
.client_rd_req(dma_rd_desc_int),
|
|
.client_rd_sts(dma_rd_desc_int),
|
|
.client_wr_req(dma_wr_desc_int),
|
|
.client_wr_sts(dma_wr_desc_int),
|
|
|
|
/*
|
|
* DMA descriptors to DMA engines
|
|
*/
|
|
.dma_rd_req(dma_rd_desc_req),
|
|
.dma_rd_sts(dma_rd_desc_sts),
|
|
.dma_wr_req(dma_wr_desc_req),
|
|
.dma_wr_sts(dma_wr_desc_sts),
|
|
|
|
/*
|
|
* RAM interface (from DMA interface)
|
|
*/
|
|
.dma_ram_wr(dma_ram_wr),
|
|
.dma_ram_rd(dma_ram_rd),
|
|
|
|
/*
|
|
* RAM interface (towards RAM)
|
|
*/
|
|
.client_ram_wr(dma_ram_int),
|
|
.client_ram_rd(dma_ram_int)
|
|
);
|
|
|
|
for (genvar p = 0; p < PORTS; p = p + 1) begin : port
|
|
|
|
cndm_micro_port #(
|
|
.PTP_TS_EN(PTP_TS_EN),
|
|
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD)
|
|
)
|
|
port_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* Control register interface
|
|
*/
|
|
.s_axil_ctrl_wr(axil_ctrl[PORT_OFFSET_HOST+p]),
|
|
.s_axil_ctrl_rd(axil_ctrl[PORT_OFFSET_HOST+p]),
|
|
|
|
/*
|
|
* Datapath control register interface
|
|
*/
|
|
.s_apb_dp_ctrl(apb_port_dp_ctrl[PORT_OFFSET_DP+p]),
|
|
|
|
/*
|
|
* DMA
|
|
*/
|
|
.dma_rd_desc_req(dma_rd_desc_int[p]),
|
|
.dma_rd_desc_sts(dma_rd_desc_int[p]),
|
|
.dma_wr_desc_req(dma_wr_desc_int[p]),
|
|
.dma_wr_desc_sts(dma_wr_desc_int[p]),
|
|
.dma_ram_wr(dma_ram_int[p]),
|
|
.dma_ram_rd(dma_ram_int[p]),
|
|
|
|
.irq(irq[p]),
|
|
|
|
/*
|
|
* PTP
|
|
*/
|
|
.ptp_clk(ptp_clk),
|
|
.ptp_rst(ptp_rst),
|
|
.ptp_td_sdi(ptp_td_sdo),
|
|
|
|
/*
|
|
* Ethernet
|
|
*/
|
|
.mac_tx_clk(mac_tx_clk[p]),
|
|
.mac_tx_rst(mac_tx_rst[p]),
|
|
.mac_axis_tx(mac_axis_tx[p]),
|
|
.mac_axis_tx_cpl(mac_axis_tx_cpl[p]),
|
|
|
|
.mac_rx_clk(mac_rx_clk[p]),
|
|
.mac_rx_rst(mac_rx_rst[p]),
|
|
.mac_axis_rx(mac_axis_rx[p])
|
|
);
|
|
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|