mirror of
https://github.com/fpganinja/taxi.git
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306 lines
6.9 KiB
Systemverilog
306 lines
6.9 KiB
Systemverilog
// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga #
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(
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parameter logic SIM = 1'b0,
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parameter string VENDOR = "XILINX",
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parameter string FAMILY = "virtexuplus"
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)
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(
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/*
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* Reset: Push button, active low
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*/
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input wire logic reset,
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/*
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* GPIO
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*/
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input wire logic [3:0] sw,
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output wire logic [2:0] led,
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/*
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* I2C for board management
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*/
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inout wire logic i2c_scl,
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inout wire logic i2c_sda,
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/*
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* UART
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*/
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output wire logic uart_txd,
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input wire logic uart_rxd,
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/*
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* Ethernet: QSFP28
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*/
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output wire logic qsfp0_tx_p[4],
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output wire logic qsfp0_tx_n[4],
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input wire logic qsfp0_rx_p[4],
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input wire logic qsfp0_rx_n[4],
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input wire logic qsfp0_mgt_refclk_0_p,
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input wire logic qsfp0_mgt_refclk_0_n,
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// input wire logic qsfp0_mgt_refclk_1_p,
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// input wire logic qsfp0_mgt_refclk_1_n,
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output wire logic qsfp0_modsell,
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output wire logic qsfp0_resetl,
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input wire logic qsfp0_modprsl,
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input wire logic qsfp0_intl,
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output wire logic qsfp0_lpmode,
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// output wire logic qsfp0_refclk_reset,
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// output wire logic [1:0] qsfp0_fs,
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output wire logic qsfp1_tx_p[4],
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output wire logic qsfp1_tx_n[4],
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input wire logic qsfp1_rx_p[4],
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input wire logic qsfp1_rx_n[4],
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input wire logic qsfp1_mgt_refclk_0_p,
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input wire logic qsfp1_mgt_refclk_0_n,
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// input wire logic qsfp1_mgt_refclk_1_p,
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// input wire logic qsfp1_mgt_refclk_1_n,
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output wire logic qsfp1_modsell,
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output wire logic qsfp1_resetl,
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input wire logic qsfp1_modprsl,
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input wire logic qsfp1_intl,
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output wire logic qsfp1_lpmode
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// output wire logic qsfp1_refclk_reset,
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// output wire logic [1:0] qsfp1_fs
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);
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// Clock and reset
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wire clk_156mhz_ref_int;
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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wire mmcm_rst = 1'b0;
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wire mmcm_locked;
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wire mmcm_clkfb;
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// MMCM instance
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MMCME4_BASE #(
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// 156.25 MHz input
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.CLKIN1_PERIOD(6.4),
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.REF_JITTER1(0.010),
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// 156.25 MHz input / 1 = 156.25 MHz PFD (range 10 MHz to 500 MHz)
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.DIVCLK_DIVIDE(1),
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// 156.25 MHz PFD * 8 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
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.CLKFBOUT_MULT_F(8),
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.CLKFBOUT_PHASE(0),
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// 1250 MHz / 10 = 125 MHz, 0 degrees
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.CLKOUT0_DIVIDE_F(10),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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// Not used
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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// Not used
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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// Not used
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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// Not used
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT4_CASCADE("FALSE"),
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// Not used
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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// Not used
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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// optimized bandwidth
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.BANDWIDTH("OPTIMIZED"),
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// don't wait for lock during startup
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.STARTUP_WAIT("FALSE")
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)
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clk_mmcm_inst (
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// 156.25 MHz input
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.CLKIN1(clk_156mhz_ref_int),
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// direct clkfb feeback
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.CLKFBIN(mmcm_clkfb),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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// 125 MHz, 0 degrees
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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// Not used
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.CLKOUT1(),
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.CLKOUT1B(),
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// Not used
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.CLKOUT2(),
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.CLKOUT2B(),
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// Not used
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.CLKOUT3(),
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.CLKOUT3B(),
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// Not used
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.CLKOUT4(),
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// Not used
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.CLKOUT5(),
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// Not used
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.CLKOUT6(),
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// reset input
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.RST(mmcm_rst),
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// don't power down
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.PWRDWN(1'b0),
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// locked output
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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// GPIO
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wire [3:0] sw_int;
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taxi_debounce_switch #(
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.WIDTH(4),
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.N(4),
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.RATE(156000)
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)
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debounce_switch_inst (
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.clk(clk_125mhz_int),
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.rst(rst_125mhz_int),
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.in({sw}),
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.out({sw_int})
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);
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// SI570 I2C
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wire i2c_scl_i;
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wire i2c_scl_o = 1'b1;
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wire i2c_scl_t = 1'b1;
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wire i2c_sda_i;
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wire i2c_sda_o = 1'b1;
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wire i2c_sda_t = 1'b1;
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assign i2c_scl_i = i2c_scl;
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assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
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assign i2c_sda_i = i2c_sda;
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assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
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localparam PORT_CNT = 2;
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localparam GTY_QUAD_CNT = PORT_CNT;
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localparam GTY_CNT = GTY_QUAD_CNT*4;
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localparam GTY_CLK_CNT = GTY_QUAD_CNT;
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wire eth_gty_tx_p[GTY_CNT];
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wire eth_gty_tx_n[GTY_CNT];
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wire eth_gty_rx_p[GTY_CNT];
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wire eth_gty_rx_n[GTY_CNT];
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wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
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wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
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wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
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assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4];
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assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4];
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assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p;
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assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n;
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assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4];
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assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4];
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assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p;
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assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n;
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assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_0_p;
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assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_0_n;
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assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_0_p;
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assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_0_n;
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assign clk_156mhz_ref_int = eth_gty_mgt_refclk_out[0];
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fpga_core #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.SW_CNT(4),
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.LED_CNT(3),
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.UART_CNT(1),
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.PORT_CNT(PORT_CNT),
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.GTY_QUAD_CNT(GTY_QUAD_CNT),
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.GTY_CNT(GTY_CNT),
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.GTY_CLK_CNT(GTY_CLK_CNT)
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)
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core_inst (
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/*
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* Clock: 125MHz
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* Synchronous reset
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*/
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.clk_125mhz(clk_125mhz_int),
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.rst_125mhz(rst_125mhz_int),
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/*
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* GPIO
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*/
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.sw(sw_int),
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.led(led),
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.port_led_act(),
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.port_led_stat_r(),
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.port_led_stat_g(),
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.port_led_stat_b(),
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.port_led_stat_y(),
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/*
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* UART
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*/
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.uart_txd(uart_txd),
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.uart_rxd(uart_rxd),
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/*
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* Ethernet
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*/
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.eth_gty_tx_p(eth_gty_tx_p),
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.eth_gty_tx_n(eth_gty_tx_n),
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.eth_gty_rx_p(eth_gty_rx_p),
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.eth_gty_rx_n(eth_gty_rx_n),
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.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
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.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
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.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
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.eth_port_modsell({qsfp1_modsell, qsfp0_modsell}),
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.eth_port_resetl({qsfp1_resetl, qsfp0_resetl}),
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.eth_port_modprsl({qsfp1_modprsl, qsfp0_modprsl}),
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.eth_port_intl({qsfp1_intl, qsfp0_intl}),
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.eth_port_lpmode({qsfp1_lpmode, qsfp0_lpmode})
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);
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endmodule
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`resetall
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