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https://github.com/fpganinja/taxi.git
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924 lines
21 KiB
Systemverilog
924 lines
21 KiB
Systemverilog
// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2021-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module for HTG-ZRF8-R2
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*/
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module fpga #
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(
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parameter logic SIM = 1'b0,
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parameter string VENDOR = "XILINX",
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parameter string FAMILY = "zynquplusRFSOC"
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)
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(
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/*
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* Clock: 200 MHz LVDS
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*/
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input wire logic clk_pl_user1_p,
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input wire logic clk_pl_user1_n,
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input wire logic fpga_refclk_p,
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input wire logic fpga_refclk_n,
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input wire logic fpga_sysref_p,
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input wire logic fpga_sysref_n,
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/*
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* GPIO
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*/
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input wire logic btn,
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input wire logic [3:0] sw,
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output wire logic [3:0] led,
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/*
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* I2C for board management
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*/
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inout wire logic i2c_scl,
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inout wire logic i2c_sda,
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output wire logic i2c_rst_n,
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/*
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* PLL
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*/
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output wire logic clk_fdec,
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output wire logic clk_finc,
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input wire logic clk_intr_n,
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input wire logic clk_lol_n,
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output wire logic clk_sync_n,
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output wire logic clk_rst_n,
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output wire logic lmk_rst,
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output wire logic [1:0] lmk_clkin_s,
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/*
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* UART: 921600 bps, 8N1
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*/
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output wire logic uart_rxd,
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input wire logic uart_txd,
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input wire logic uart_rts,
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output wire logic uart_cts,
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output wire logic uart_rst_n,
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input wire logic uart_suspend_n,
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/*
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* FMC+
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*/
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// output wire logic [33:0] fmc_la_p,
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// output wire logic [33:0] fmc_la_n,
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output wire logic fmc_qsfp_modsell,
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output wire logic fmc_qsfp_resetl,
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output wire logic fmc_qsfp_lpmode,
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output wire logic fmc_dp_c2m_p[8],
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output wire logic fmc_dp_c2m_n[8],
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input wire logic fmc_dp_m2c_p[8],
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input wire logic fmc_dp_m2c_n[8],
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input wire logic fmc_mgt_refclk_0_0_p,
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input wire logic fmc_mgt_refclk_0_0_n,
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input wire logic fmc_mgt_refclk_1_0_p,
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input wire logic fmc_mgt_refclk_1_0_n,
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/*
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* RFDC
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*/
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input wire logic [7:0] adc_vin_p,
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input wire logic [7:0] adc_vin_n,
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input wire logic adc_refclk_0_p,
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input wire logic adc_refclk_0_n,
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input wire logic adc_refclk_1_p,
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input wire logic adc_refclk_1_n,
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input wire logic adc_refclk_2_p,
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input wire logic adc_refclk_2_n,
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input wire logic adc_refclk_3_p,
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input wire logic adc_refclk_3_n,
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output wire logic [7:0] dac_vout_p,
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output wire logic [7:0] dac_vout_n,
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// input wire logic dac_refclk_0_p,
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// input wire logic dac_refclk_0_n,
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input wire logic dac_refclk_1_p,
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input wire logic dac_refclk_1_n,
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input wire logic rfdc_sysref_p,
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input wire logic rfdc_sysref_n
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);
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// PLL
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assign clk_fdec = 1'b0;
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assign clk_finc = 1'b0;
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assign clk_sync_n = 1'b1;
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assign clk_rst_n = 1'b1;
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assign lmk_rst = 1'b0;
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assign lmk_clkin_s = 2'b00;
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wire pll_i2c_busy;
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// Clock and reset
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wire clk_pl_user1_ibufg;
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wire clk_pl_user1_bufg;
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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wire mmcm_rst = pll_i2c_busy || !clk_lol_n;
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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clk_pl_user1_ibufg_inst (
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.I (clk_pl_user1_p),
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.IB(clk_pl_user1_n),
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.O (clk_pl_user1_ibufg)
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);
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BUFG
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clk_pl_user1_bufg_inst (
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.I(clk_pl_user1_ibufg),
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.O(clk_pl_user1_bufg)
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);
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// MMCM instance
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MMCME4_BASE #(
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// 200 MHz input
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.CLKIN1_PERIOD(5.0),
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.REF_JITTER1(0.010),
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// 200 MHz input / 1 = 200 MHz PFD (range 10 MHz to 500 MHz)
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.DIVCLK_DIVIDE(1),
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// 200 MHz PFD * 5 = 1000 MHz VCO (range 800 MHz to 1600 MHz)
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.CLKFBOUT_MULT_F(5),
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.CLKFBOUT_PHASE(0),
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// 1000 MHz / 8 = 125 MHz, 0 degrees
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.CLKOUT0_DIVIDE_F(8),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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// Not used
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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// Not used
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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// Not used
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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// Not used
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT4_CASCADE("FALSE"),
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// Not used
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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// Not used
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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// optimized bandwidth
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.BANDWIDTH("OPTIMIZED"),
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// don't wait for lock during startup
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.STARTUP_WAIT("FALSE")
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)
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clk_mmcm_inst (
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// 200 MHz input
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.CLKIN1(clk_pl_user1_bufg),
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// direct clkfb feeback
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.CLKFBIN(mmcm_clkfb),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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// 125 MHz, 0 degrees
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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// Not used
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.CLKOUT1(),
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.CLKOUT1B(),
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// Not used
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.CLKOUT2(),
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.CLKOUT2B(),
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// Not used
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.CLKOUT3(),
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.CLKOUT3B(),
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// Not used
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.CLKOUT4(),
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// Not used
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.CLKOUT5(),
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// Not used
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.CLKOUT6(),
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// reset input
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.RST(mmcm_rst),
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// don't power down
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.PWRDWN(1'b0),
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// locked output
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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wire fpga_refclk_ibufg;
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wire fpga_refclk_int;
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wire fpga_sysref_ibufg;
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wire fpga_sysref_int;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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fpga_refclk_ibufg_inst (
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.O (fpga_refclk_ibufg),
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.I (fpga_refclk_p),
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.IB (fpga_refclk_n)
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);
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BUFG
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fpga_refclk_bufg_inst (
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.I(fpga_refclk_ibufg),
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.O(fpga_refclk_int)
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);
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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fpga_sysref_ibufg_inst (
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.O (fpga_sysref_ibufg),
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.I (fpga_sysref_p),
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.IB (fpga_sysref_n)
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);
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BUFG
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fpga_sysref_bufg_inst (
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.I(fpga_sysref_ibufg),
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.O(fpga_sysref_int)
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);
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// STARTUP instance for cfgmclk
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wire cfgmclk;
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STARTUPE3
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startupe3_inst (
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.CFGCLK(),
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.CFGMCLK(cfgmclk),
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.DI(),
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.DO(4'd0),
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.DTS(1'b1),
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.EOS(),
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.FCSBO(1'b1),
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.FCSBTS(1'b1),
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.GSR(1'b0),
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.GTS(1'b0),
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.KEYCLEARB(1'b1),
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.PACK(1'b0),
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.PREQ(),
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.USRCCLKO(1'b0),
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.USRCCLKTS(1'b1),
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.USRDONEO(1'b0),
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.USRDONETS(1'b1)
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);
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wire cfgmclk_int;
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BUFG
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cfgmclk_bufg_inst (
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.I(cfgmclk),
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.O(cfgmclk_int)
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);
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wire cfgmclk_rst_int;
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_cfgmclk_inst (
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.clk(cfgmclk_int),
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.rst(~btn),
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.out(cfgmclk_rst_int)
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);
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// GPIO
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wire [3:0] sw_int;
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taxi_debounce_switch #(
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.WIDTH(4),
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.N(4),
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.RATE(125000)
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)
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debounce_switch_inst (
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.clk(clk_125mhz_int),
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.rst(rst_125mhz_int),
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.in({sw}),
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.out({sw_int})
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);
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wire uart_txd_int;
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wire uart_rts_int;
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taxi_sync_signal #(
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.WIDTH(2),
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.N(2)
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)
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sync_signal_inst (
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.clk(clk_125mhz_int),
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.in({uart_txd, uart_rts}),
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.out({uart_txd_int, uart_rts_int})
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);
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wire i2c_scl_i;
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wire i2c_scl_o;
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wire i2c_sda_i;
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wire i2c_sda_o;
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assign i2c_scl_i = i2c_scl;
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assign i2c_scl = i2c_scl_o ? 1'bz : 1'b0;
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assign i2c_sda_i = i2c_sda;
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assign i2c_sda = i2c_sda_o ? 1'bz : 1'b0;
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assign i2c_rst_n = 1'b1;
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wire i2c_init_scl_i = i2c_scl_i;
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wire i2c_init_scl_o;
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wire i2c_init_sda_i = i2c_sda_i;
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wire i2c_init_sda_o;
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wire i2c_int_scl_i = i2c_scl_i;
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wire i2c_int_scl_o;
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wire i2c_int_sda_i = i2c_sda_i;
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wire i2c_int_sda_o;
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assign i2c_scl_o = i2c_init_scl_o & i2c_int_scl_o;
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assign i2c_sda_o = i2c_init_sda_o & i2c_int_sda_o;
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// PLL init
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taxi_axis_if #(.DATA_W(12)) pll_i2c_cmd();
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taxi_axis_if #(.DATA_W(8)) pll_i2c_tx();
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taxi_axis_if #(.DATA_W(8)) pll_i2c_rx();
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assign pll_i2c_rx.tready = 1'b1;
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taxi_i2c_master
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pll_i2c_master_inst (
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.clk(cfgmclk_int),
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.rst(cfgmclk_rst_int),
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/*
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* Host interface
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*/
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.s_axis_cmd(pll_i2c_cmd),
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.s_axis_tx(pll_i2c_tx),
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.m_axis_rx(pll_i2c_rx),
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/*
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* I2C interface
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*/
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.scl_i(i2c_init_scl_i),
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.scl_o(i2c_init_scl_o),
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.sda_i(i2c_init_sda_i),
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.sda_o(i2c_init_sda_o),
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/*
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* Status
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*/
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.busy(),
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.bus_control(),
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.bus_active(),
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.missed_ack(),
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/*
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* Configuration
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*/
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.prescale(SIM ? 15 : 150),
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.stop_on_idle(1)
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);
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pll_i2c_init_r2 #(
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.SIM_SPEEDUP(SIM)
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)
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pll_i2c_init_inst (
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.clk(cfgmclk_int),
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.rst(cfgmclk_rst_int),
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/*
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* I2C master interface
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*/
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.m_axis_cmd(pll_i2c_cmd),
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.m_axis_tx(pll_i2c_tx),
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/*
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* Status
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*/
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.busy(pll_i2c_busy),
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/*
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* Configuration
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*/
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.start(1'b1)
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);
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localparam PORT_CNT = 2;
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localparam GTY_QUAD_CNT = PORT_CNT;
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localparam GTY_CNT = GTY_QUAD_CNT*4;
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localparam GTY_CLK_CNT = GTY_QUAD_CNT;
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assign fmc_qsfp_modsell = 1'b0;
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assign fmc_qsfp_resetl = 1'b1;
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assign fmc_qsfp_lpmode = 1'b0;
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// RF data converters
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localparam ADC_CNT = 8;
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localparam ADC_SAMPLE_W = 16;
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localparam ADC_SAMPLE_CNT = 4;
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localparam ADC_DATA_W = ADC_SAMPLE_W*ADC_SAMPLE_CNT;
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localparam DAC_CNT = ADC_CNT;
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localparam DAC_SAMPLE_W = ADC_SAMPLE_W;
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localparam DAC_SAMPLE_CNT = ADC_SAMPLE_CNT;
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localparam DAC_DATA_W = DAC_SAMPLE_W*DAC_SAMPLE_CNT;
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wire axil_rfdc_clk = clk_125mhz_int;
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wire axil_rfdc_rst = rst_125mhz_int;
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taxi_axil_if #(
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.DATA_W(32),
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.ADDR_W(18)
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) axil_rfdc();
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wire axis_rfdc_clk;
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wire axis_rfdc_rst;
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wire [3:0] adc_clk_out;
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wire [3:0] dac_clk_out;
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taxi_axis_if #(
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.DATA_W(ADC_DATA_W),
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.KEEP_EN(1),
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.KEEP_W(ADC_SAMPLE_CNT),
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.LAST_EN(0),
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.USER_EN(0),
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.ID_EN(0),
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.DEST_EN(0)
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) axis_adc[ADC_CNT]();
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(* MARK_DEBUG = "TRUE" *)
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wire [ADC_DATA_W-1:0] adc_data_0 = axis_adc[0].tdata;
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(* MARK_DEBUG = "TRUE" *)
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wire [ADC_DATA_W-1:0] adc_data_1 = axis_adc[1].tdata;
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(* MARK_DEBUG = "TRUE" *)
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wire [ADC_DATA_W-1:0] adc_data_2 = axis_adc[2].tdata;
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(* MARK_DEBUG = "TRUE" *)
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wire [ADC_DATA_W-1:0] adc_data_3 = axis_adc[3].tdata;
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(* MARK_DEBUG = "TRUE" *)
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wire [ADC_DATA_W-1:0] adc_data_4 = axis_adc[4].tdata;
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(* MARK_DEBUG = "TRUE" *)
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wire [ADC_DATA_W-1:0] adc_data_5 = axis_adc[5].tdata;
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(* MARK_DEBUG = "TRUE" *)
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wire [ADC_DATA_W-1:0] adc_data_6 = axis_adc[6].tdata;
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(* MARK_DEBUG = "TRUE" *)
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wire [ADC_DATA_W-1:0] adc_data_7 = axis_adc[7].tdata;
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taxi_axis_if #(
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.DATA_W(DAC_DATA_W),
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.KEEP_EN(1),
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.KEEP_W(DAC_SAMPLE_CNT),
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.LAST_EN(0),
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.USER_EN(0),
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.ID_EN(0),
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|
.DEST_EN(0)
|
|
) axis_dac[DAC_CNT]();
|
|
|
|
(* MARK_DEBUG = "TRUE" *)
|
|
wire [DAC_DATA_W-1:0] dac_data_0 = axis_dac[0].tdata;
|
|
(* MARK_DEBUG = "TRUE" *)
|
|
wire [DAC_DATA_W-1:0] dac_data_1 = axis_dac[1].tdata;
|
|
(* MARK_DEBUG = "TRUE" *)
|
|
wire [DAC_DATA_W-1:0] dac_data_2 = axis_dac[2].tdata;
|
|
(* MARK_DEBUG = "TRUE" *)
|
|
wire [DAC_DATA_W-1:0] dac_data_3 = axis_dac[3].tdata;
|
|
(* MARK_DEBUG = "TRUE" *)
|
|
wire [DAC_DATA_W-1:0] dac_data_4 = axis_dac[4].tdata;
|
|
(* MARK_DEBUG = "TRUE" *)
|
|
wire [DAC_DATA_W-1:0] dac_data_5 = axis_dac[5].tdata;
|
|
(* MARK_DEBUG = "TRUE" *)
|
|
wire [DAC_DATA_W-1:0] dac_data_6 = axis_dac[6].tdata;
|
|
(* MARK_DEBUG = "TRUE" *)
|
|
wire [DAC_DATA_W-1:0] dac_data_7 = axis_dac[7].tdata;
|
|
|
|
wire rfdc_mmcm_in = dac_clk_out[0];
|
|
wire rfdc_mmcm_rst = rst_125mhz_int;
|
|
wire rfdc_mmcm_clkfb;
|
|
wire rfdc_mmcm_locked;
|
|
wire rfdc_mmcm_out;
|
|
|
|
// MMCM instance
|
|
MMCME4_BASE #(
|
|
// 62.5 MHz input
|
|
.CLKIN1_PERIOD(16.0),
|
|
.REF_JITTER1(0.010),
|
|
// 62.5 MHz input / 1 = 62.5 MHz PFD (range 10 MHz to 500 MHz)
|
|
.DIVCLK_DIVIDE(1),
|
|
// 62.5 MHz PFD * 20 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
|
|
.CLKFBOUT_MULT_F(20),
|
|
.CLKFBOUT_PHASE(0),
|
|
// 1250 MHz / 5 = 250 MHz, 0 degrees
|
|
.CLKOUT0_DIVIDE_F(5),
|
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
|
.CLKOUT0_PHASE(0),
|
|
// Not used
|
|
.CLKOUT1_DIVIDE(1),
|
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
|
.CLKOUT1_PHASE(0),
|
|
// Not used
|
|
.CLKOUT2_DIVIDE(1),
|
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
|
.CLKOUT2_PHASE(0),
|
|
// Not used
|
|
.CLKOUT3_DIVIDE(1),
|
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
|
.CLKOUT3_PHASE(0),
|
|
// Not used
|
|
.CLKOUT4_DIVIDE(1),
|
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
|
.CLKOUT4_PHASE(0),
|
|
.CLKOUT4_CASCADE("FALSE"),
|
|
// Not used
|
|
.CLKOUT5_DIVIDE(1),
|
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
|
.CLKOUT5_PHASE(0),
|
|
// Not used
|
|
.CLKOUT6_DIVIDE(1),
|
|
.CLKOUT6_DUTY_CYCLE(0.5),
|
|
.CLKOUT6_PHASE(0),
|
|
|
|
// optimized bandwidth
|
|
.BANDWIDTH("OPTIMIZED"),
|
|
// don't wait for lock during startup
|
|
.STARTUP_WAIT("FALSE")
|
|
)
|
|
rfdc_mmcm_inst (
|
|
// 62.5 MHz input
|
|
.CLKIN1(rfdc_mmcm_in),
|
|
// direct clkfb feeback
|
|
.CLKFBIN(rfdc_mmcm_clkfb),
|
|
.CLKFBOUT(rfdc_mmcm_clkfb),
|
|
.CLKFBOUTB(),
|
|
// 250 MHz, 0 degrees
|
|
.CLKOUT0(rfdc_mmcm_out),
|
|
.CLKOUT0B(),
|
|
// Not used
|
|
.CLKOUT1(),
|
|
.CLKOUT1B(),
|
|
// Not used
|
|
.CLKOUT2(),
|
|
.CLKOUT2B(),
|
|
// Not used
|
|
.CLKOUT3(),
|
|
.CLKOUT3B(),
|
|
// Not used
|
|
.CLKOUT4(),
|
|
// Not used
|
|
.CLKOUT5(),
|
|
// Not used
|
|
.CLKOUT6(),
|
|
// reset input
|
|
.RST(rfdc_mmcm_rst),
|
|
// don't power down
|
|
.PWRDWN(1'b0),
|
|
// locked output
|
|
.LOCKED(rfdc_mmcm_locked)
|
|
);
|
|
|
|
BUFG
|
|
axis_rfdc_bufg_inst (
|
|
.I(rfdc_mmcm_out),
|
|
.O(axis_rfdc_clk)
|
|
);
|
|
|
|
taxi_sync_reset #(
|
|
.N(4)
|
|
)
|
|
axis_rfdc_sync_reset_inst (
|
|
.clk(axis_rfdc_clk),
|
|
.rst(!rfdc_mmcm_locked || rfdc_mmcm_rst),
|
|
.out(axis_rfdc_rst)
|
|
);
|
|
|
|
usp_rfdc_0 rfdc_inst (
|
|
// Common
|
|
.sysref_in_p(rfdc_sysref_p),
|
|
.sysref_in_n(rfdc_sysref_n),
|
|
|
|
.s_axi_aclk(axil_rfdc_clk),
|
|
.s_axi_aresetn(!axil_rfdc_rst),
|
|
.s_axi_awaddr(axil_rfdc.awaddr),
|
|
.s_axi_awvalid(axil_rfdc.awvalid),
|
|
.s_axi_awready(axil_rfdc.awready),
|
|
.s_axi_wdata(axil_rfdc.wdata),
|
|
.s_axi_wstrb(axil_rfdc.wstrb),
|
|
.s_axi_wvalid(axil_rfdc.wvalid),
|
|
.s_axi_wready(axil_rfdc.wready),
|
|
.s_axi_bresp(axil_rfdc.bresp),
|
|
.s_axi_bvalid(axil_rfdc.bvalid),
|
|
.s_axi_bready(axil_rfdc.bready),
|
|
.s_axi_araddr(axil_rfdc.araddr),
|
|
.s_axi_arvalid(axil_rfdc.arvalid),
|
|
.s_axi_arready(axil_rfdc.arready),
|
|
.s_axi_rdata(axil_rfdc.rdata),
|
|
.s_axi_rresp(axil_rfdc.rresp),
|
|
.s_axi_rvalid(axil_rfdc.rvalid),
|
|
.s_axi_rready(axil_rfdc.rready),
|
|
|
|
.irq(),
|
|
|
|
// ADC
|
|
.adc0_clk_p(adc_refclk_0_p),
|
|
.adc0_clk_n(adc_refclk_0_n),
|
|
.clk_adc0(adc_clk_out[0]),
|
|
|
|
.adc1_clk_p(adc_refclk_1_p),
|
|
.adc1_clk_n(adc_refclk_1_n),
|
|
.clk_adc1(adc_clk_out[1]),
|
|
|
|
.adc2_clk_p(adc_refclk_2_p),
|
|
.adc2_clk_n(adc_refclk_2_n),
|
|
.clk_adc2(adc_clk_out[2]),
|
|
|
|
.adc3_clk_p(adc_refclk_3_p),
|
|
.adc3_clk_n(adc_refclk_3_n),
|
|
.clk_adc3(adc_clk_out[3]),
|
|
|
|
.vin0_01_p(adc_vin_p[7]),
|
|
.vin0_01_n(adc_vin_n[7]),
|
|
.vin0_23_p(adc_vin_p[6]),
|
|
.vin0_23_n(adc_vin_n[6]),
|
|
|
|
.vin1_01_p(adc_vin_p[5]),
|
|
.vin1_01_n(adc_vin_n[5]),
|
|
.vin1_23_p(adc_vin_p[4]),
|
|
.vin1_23_n(adc_vin_n[4]),
|
|
|
|
.vin2_01_p(adc_vin_p[3]),
|
|
.vin2_01_n(adc_vin_n[3]),
|
|
.vin2_23_p(adc_vin_p[2]),
|
|
.vin2_23_n(adc_vin_n[2]),
|
|
|
|
.vin3_01_p(adc_vin_p[1]),
|
|
.vin3_01_n(adc_vin_n[1]),
|
|
.vin3_23_p(adc_vin_p[0]),
|
|
.vin3_23_n(adc_vin_n[0]),
|
|
|
|
.m0_axis_aresetn(!axis_rfdc_rst),
|
|
.m0_axis_aclk(axis_rfdc_clk),
|
|
.m00_axis_tdata(axis_adc[7].tdata),
|
|
.m00_axis_tvalid(axis_adc[7].tvalid),
|
|
.m00_axis_tready(axis_adc[7].tready),
|
|
.m02_axis_tdata(axis_adc[6].tdata),
|
|
.m02_axis_tvalid(axis_adc[6].tvalid),
|
|
.m02_axis_tready(axis_adc[6].tready),
|
|
|
|
.m1_axis_aresetn(!axis_rfdc_rst),
|
|
.m1_axis_aclk(axis_rfdc_clk),
|
|
.m10_axis_tdata(axis_adc[5].tdata),
|
|
.m10_axis_tvalid(axis_adc[5].tvalid),
|
|
.m10_axis_tready(axis_adc[5].tready),
|
|
.m12_axis_tdata(axis_adc[4].tdata),
|
|
.m12_axis_tvalid(axis_adc[4].tvalid),
|
|
.m12_axis_tready(axis_adc[4].tready),
|
|
|
|
.m2_axis_aresetn(!axis_rfdc_rst),
|
|
.m2_axis_aclk(axis_rfdc_clk),
|
|
.m20_axis_tdata(axis_adc[3].tdata),
|
|
.m20_axis_tvalid(axis_adc[3].tvalid),
|
|
.m20_axis_tready(axis_adc[3].tready),
|
|
.m22_axis_tdata(axis_adc[2].tdata),
|
|
.m22_axis_tvalid(axis_adc[2].tvalid),
|
|
.m22_axis_tready(axis_adc[2].tready),
|
|
|
|
.m3_axis_aresetn(!axis_rfdc_rst),
|
|
.m3_axis_aclk(axis_rfdc_clk),
|
|
.m30_axis_tdata(axis_adc[1].tdata),
|
|
.m30_axis_tvalid(axis_adc[1].tvalid),
|
|
.m30_axis_tready(axis_adc[1].tready),
|
|
.m32_axis_tdata(axis_adc[0].tdata),
|
|
.m32_axis_tvalid(axis_adc[0].tvalid),
|
|
.m32_axis_tready(axis_adc[0].tready),
|
|
|
|
.adc0_01_dsa_code(5'd27),
|
|
.adc0_23_dsa_code(5'd27),
|
|
.adc0_dsa_update(1'b0),
|
|
.adc1_01_dsa_code(5'd27),
|
|
.adc1_23_dsa_code(5'd27),
|
|
.adc1_dsa_update(1'b0),
|
|
.adc2_01_dsa_code(5'd27),
|
|
.adc2_23_dsa_code(5'd27),
|
|
.adc2_dsa_update(1'b0),
|
|
.adc3_01_dsa_code(5'd27),
|
|
.adc3_23_dsa_code(5'd27),
|
|
.adc3_dsa_update(1'b0),
|
|
|
|
// DAC
|
|
.dac2_clk_p(dac_refclk_1_p),
|
|
.dac2_clk_n(dac_refclk_1_n),
|
|
|
|
.clk_dac0(dac_clk_out[0]),
|
|
.clk_dac1(dac_clk_out[1]),
|
|
.clk_dac2(dac_clk_out[2]),
|
|
.clk_dac3(dac_clk_out[3]),
|
|
|
|
.vout00_p(dac_vout_p[7]),
|
|
.vout00_n(dac_vout_n[7]),
|
|
.vout02_p(dac_vout_p[6]),
|
|
.vout02_n(dac_vout_n[6]),
|
|
|
|
.vout10_p(dac_vout_p[5]),
|
|
.vout10_n(dac_vout_n[5]),
|
|
.vout12_p(dac_vout_p[4]),
|
|
.vout12_n(dac_vout_n[4]),
|
|
|
|
.vout20_p(dac_vout_p[3]),
|
|
.vout20_n(dac_vout_n[3]),
|
|
.vout22_p(dac_vout_p[2]),
|
|
.vout22_n(dac_vout_n[2]),
|
|
|
|
.vout30_p(dac_vout_p[1]),
|
|
.vout30_n(dac_vout_n[1]),
|
|
.vout32_p(dac_vout_p[0]),
|
|
.vout32_n(dac_vout_n[0]),
|
|
|
|
.s0_axis_aresetn(!axis_rfdc_rst),
|
|
.s0_axis_aclk(axis_rfdc_clk),
|
|
.s00_axis_tdata(axis_dac[7].tdata),
|
|
.s00_axis_tvalid(axis_dac[7].tvalid),
|
|
.s00_axis_tready(axis_dac[7].tready),
|
|
.s02_axis_tdata(axis_dac[6].tdata),
|
|
.s02_axis_tvalid(axis_dac[6].tvalid),
|
|
.s02_axis_tready(axis_dac[6].tready),
|
|
|
|
.s1_axis_aresetn(!axis_rfdc_rst),
|
|
.s1_axis_aclk(axis_rfdc_clk),
|
|
.s10_axis_tdata(axis_dac[5].tdata),
|
|
.s10_axis_tvalid(axis_dac[5].tvalid),
|
|
.s10_axis_tready(axis_dac[5].tready),
|
|
.s12_axis_tdata(axis_dac[4].tdata),
|
|
.s12_axis_tvalid(axis_dac[4].tvalid),
|
|
.s12_axis_tready(axis_dac[4].tready),
|
|
|
|
.s2_axis_aresetn(!axis_rfdc_rst),
|
|
.s2_axis_aclk(axis_rfdc_clk),
|
|
.s20_axis_tdata(axis_dac[3].tdata),
|
|
.s20_axis_tvalid(axis_dac[3].tvalid),
|
|
.s20_axis_tready(axis_dac[3].tready),
|
|
.s22_axis_tdata(axis_dac[2].tdata),
|
|
.s22_axis_tvalid(axis_dac[2].tvalid),
|
|
.s22_axis_tready(axis_dac[2].tready),
|
|
|
|
.s3_axis_aresetn(!axis_rfdc_rst),
|
|
.s3_axis_aclk(axis_rfdc_clk),
|
|
.s30_axis_tdata(axis_dac[1].tdata),
|
|
.s30_axis_tvalid(axis_dac[1].tvalid),
|
|
.s30_axis_tready(axis_dac[1].tready),
|
|
.s32_axis_tdata(axis_dac[0].tdata),
|
|
.s32_axis_tvalid(axis_dac[0].tvalid),
|
|
.s32_axis_tready(axis_dac[0].tready),
|
|
|
|
.dac00_vop_code(10'd895),
|
|
.dac02_vop_code(10'd895),
|
|
.dac00_update_vop(1'b0),
|
|
.dac02_update_vop(1'b0),
|
|
.dac00_vop_done(),
|
|
.dac02_vop_done(),
|
|
.dac0_vop_busy(),
|
|
|
|
.dac10_vop_code(10'd895),
|
|
.dac12_vop_code(10'd895),
|
|
.dac10_update_vop(1'b0),
|
|
.dac12_update_vop(1'b0),
|
|
.dac10_vop_done(),
|
|
.dac12_vop_done(),
|
|
.dac1_vop_busy(),
|
|
|
|
.dac20_vop_code(10'd895),
|
|
.dac22_vop_code(10'd895),
|
|
.dac20_update_vop(1'b0),
|
|
.dac22_update_vop(1'b0),
|
|
.dac20_vop_done(),
|
|
.dac22_vop_done(),
|
|
.dac2_vop_busy(),
|
|
|
|
.dac30_vop_code(10'd895),
|
|
.dac32_vop_code(10'd895),
|
|
.dac30_update_vop(1'b0),
|
|
.dac32_update_vop(1'b0),
|
|
.dac30_vop_done(),
|
|
.dac32_vop_done(),
|
|
.dac3_vop_busy()
|
|
);
|
|
|
|
fpga_core #(
|
|
.SIM(SIM),
|
|
.VENDOR(VENDOR),
|
|
.FAMILY(FAMILY),
|
|
.PORT_CNT(PORT_CNT),
|
|
.GTY_QUAD_CNT(GTY_QUAD_CNT),
|
|
.GTY_CNT(GTY_CNT),
|
|
.GTY_CLK_CNT(GTY_CLK_CNT),
|
|
.ADC_CNT(ADC_CNT),
|
|
.DAC_CNT(DAC_CNT)
|
|
)
|
|
core_inst (
|
|
/*
|
|
* Clock: 125MHz
|
|
* Synchronous reset
|
|
*/
|
|
.clk_125mhz(clk_125mhz_int),
|
|
.rst_125mhz(rst_125mhz_int),
|
|
.fpga_refclk(fpga_refclk_int),
|
|
.fpga_sysref(fpga_sysref_int),
|
|
|
|
/*
|
|
* GPIO
|
|
*/
|
|
.sw(sw_int),
|
|
.led(led),
|
|
.gpio(),
|
|
|
|
/*
|
|
* I2C for board management
|
|
*/
|
|
.i2c_scl_i(i2c_int_scl_i),
|
|
.i2c_scl_o(i2c_int_scl_o),
|
|
.i2c_sda_i(i2c_int_sda_i),
|
|
.i2c_sda_o(i2c_int_sda_o),
|
|
|
|
/*
|
|
* UART: 921600 bps, 8N1
|
|
*/
|
|
.uart_rxd(uart_rxd),
|
|
.uart_txd(uart_txd_int),
|
|
.uart_rts(uart_rts_int),
|
|
.uart_cts(uart_cts),
|
|
.uart_rst_n(uart_rst_n),
|
|
.uart_suspend_n(uart_suspend_n),
|
|
|
|
/*
|
|
* Ethernet: QSFP28
|
|
*/
|
|
.eth_gty_tx_p(fmc_dp_c2m_p),
|
|
.eth_gty_tx_n(fmc_dp_c2m_n),
|
|
.eth_gty_rx_p(fmc_dp_m2c_p),
|
|
.eth_gty_rx_n(fmc_dp_m2c_n),
|
|
.eth_gty_mgt_refclk_p({fmc_mgt_refclk_1_0_p, fmc_mgt_refclk_0_0_p}),
|
|
.eth_gty_mgt_refclk_n({fmc_mgt_refclk_1_0_n, fmc_mgt_refclk_0_0_n}),
|
|
.eth_gty_mgt_refclk_out(),
|
|
|
|
.eth_port_resetl(),
|
|
.eth_port_modprsl('0),
|
|
.eth_port_intl('1),
|
|
|
|
/*
|
|
* RFDC
|
|
*/
|
|
.axil_rfdc_clk(axil_rfdc_clk),
|
|
.axil_rfdc_rst(axil_rfdc_rst),
|
|
.m_axil_rfdc_wr(axil_rfdc),
|
|
.m_axil_rfdc_rd(axil_rfdc),
|
|
|
|
.axis_rfdc_clk(axis_rfdc_clk),
|
|
.axis_rfdc_rst(axis_rfdc_rst),
|
|
.s_axis_adc(axis_adc),
|
|
.m_axis_dac(axis_dac)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|