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47 lines
772 B
Systemverilog
47 lines
772 B
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Synchronizes an active-high asynchronous reset signal to a given clock by
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* using a pipeline of N registers.
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*/
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module taxi_sync_reset #
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(
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// depth of synchronizer
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parameter N = 2
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)
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(
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input wire logic clk,
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input wire logic rst,
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output wire logic out
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);
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(* async_reg="true", srl_style="register", shreg_extract="no" *)
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logic [N-1:0] sync_reg = '1;
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assign out = sync_reg[N-1];
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always_ff @(posedge clk or posedge rst) begin
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if (rst) begin
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sync_reg <= '1;
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end else begin
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sync_reg <= {sync_reg[N-2:0], 1'b0};
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end
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end
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endmodule
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`resetall
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