mirror of
https://github.com/fpganinja/taxi.git
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1089 lines
31 KiB
Systemverilog
1089 lines
31 KiB
Systemverilog
// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2014-2026 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter string VENDOR = "XILINX",
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// device family
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parameter string FAMILY = "virtexu",
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// FW ID
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parameter FPGA_ID = 32'h3842093,
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parameter FW_ID = 32'h0000C001,
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parameter FW_VER = 32'h000_01_000,
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parameter BOARD_ID = 32'h10ee_806c,
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parameter BOARD_VER = 32'h001_00_000,
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parameter BUILD_DATE = 32'd602976000,
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parameter GIT_HASH = 32'h5f87c2e8,
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parameter RELEASE_INFO = 32'h00000000,
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// PTP configuration
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parameter logic PTP_TS_EN = 1'b1,
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// AXI lite interface configuration (control)
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parameter AXIL_CTRL_DATA_W = 32,
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parameter AXIL_CTRL_ADDR_W = 24,
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// MAC configuration
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parameter logic CFG_LOW_LATENCY = 1'b1,
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parameter logic COMBINED_MAC_PCS = 1'b1,
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parameter MAC_DATA_W = 64
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)
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(
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/*
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* Clock: 125MHz LVDS
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* Reset: Push button, active low
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*/
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input wire logic clk_125mhz_p,
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input wire logic clk_125mhz_n,
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input wire logic reset,
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/*
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* GPIO
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*/
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input wire logic btnu,
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input wire logic btnl,
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input wire logic btnd,
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input wire logic btnr,
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input wire logic btnc,
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input wire logic [3:0] sw,
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output wire logic [7:0] led,
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/*
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* UART: 500000 bps, 8N1
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*/
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input wire logic uart_rxd,
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output wire logic uart_txd,
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input wire logic uart_rts,
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output wire logic uart_cts,
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/*
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* Ethernet: 1000BASE-T SGMII
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*/
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input wire logic phy_sgmii_rx_p,
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input wire logic phy_sgmii_rx_n,
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output wire logic phy_sgmii_tx_p,
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output wire logic phy_sgmii_tx_n,
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input wire logic phy_sgmii_clk_p,
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input wire logic phy_sgmii_clk_n,
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output wire logic phy_reset_n,
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input wire logic phy_int_n,
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/*
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* Ethernet: QSFP28
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*/
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input wire logic qsfp_rx_p[4],
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input wire logic qsfp_rx_n[4],
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output wire logic qsfp_tx_p[4],
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output wire logic qsfp_tx_n[4],
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input wire logic qsfp_mgt_refclk_0_p,
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input wire logic qsfp_mgt_refclk_0_n,
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// input wire logic qsfp_mgt_refclk_1_p,
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// input wire logic qsfp_mgt_refclk_1_n,
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// output wire logic qsfp_recclk_p,
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// output wire logic qsfp_recclk_n,
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output wire logic qsfp_modsell,
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output wire logic qsfp_resetl,
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input wire logic qsfp_modprsl,
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input wire logic qsfp_intl,
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output wire logic qsfp_lpmode,
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/*
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* PCIe
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*/
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input wire logic [7:0] pcie_rx_p,
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input wire logic [7:0] pcie_rx_n,
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output wire logic [7:0] pcie_tx_p,
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output wire logic [7:0] pcie_tx_n,
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input wire logic pcie_refclk_p,
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input wire logic pcie_refclk_n,
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input wire logic pcie_reset_n,
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/*
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* BPI Flash
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*/
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inout wire logic [15:4] flash_dq,
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output wire logic [23:0] flash_addr,
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output wire logic [1:0] flash_region,
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output wire logic flash_oe_n,
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output wire logic flash_we_n,
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output wire logic flash_adv_n,
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input wire logic flash_wait
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);
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// Clock and reset
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wire pcie_user_clk;
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wire pcie_user_rst;
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wire clk_125mhz_ibufg;
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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wire mmcm_rst = reset;
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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clk_125mhz_ibufg_inst (
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.O (clk_125mhz_ibufg),
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.I (clk_125mhz_p),
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.IB (clk_125mhz_n)
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);
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// MMCM instance
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MMCME3_BASE #(
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// 125 MHz input
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.CLKIN1_PERIOD(8.0),
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.REF_JITTER1(0.010),
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// 125 MHz input / 1 = 125 MHz PFD (range 10 MHz to 500 MHz)
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.DIVCLK_DIVIDE(1),
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// 125 MHz PFD * 10 = 1250 MHz VCO (range 600 MHz to 1440 MHz)
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.CLKFBOUT_MULT_F(10),
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.CLKFBOUT_PHASE(0),
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// 1250 MHz / 10 = 125 MHz, 0 degrees
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.CLKOUT0_DIVIDE_F(10),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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// Not used
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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// Not used
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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// Not used
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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// Not used
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT4_CASCADE("FALSE"),
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// Not used
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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// Not used
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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// optimized bandwidth
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.BANDWIDTH("OPTIMIZED"),
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// don't wait for lock during startup
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.STARTUP_WAIT("FALSE")
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)
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clk_mmcm_inst (
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// 125 MHz input
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.CLKIN1(clk_125mhz_ibufg),
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// direct clkfb feeback
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.CLKFBIN(mmcm_clkfb),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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// 125 MHz, 0 degrees
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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// Not used
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.CLKOUT1(),
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.CLKOUT1B(),
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// Not used
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.CLKOUT2(),
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.CLKOUT2B(),
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// Not used
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.CLKOUT3(),
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.CLKOUT3B(),
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// Not used
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.CLKOUT4(),
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// Not used
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.CLKOUT5(),
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// Not used
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.CLKOUT6(),
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// reset input
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.RST(mmcm_rst),
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// don't power down
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.PWRDWN(1'b0),
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// locked output
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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// GPIO
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wire btnu_int;
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wire btnl_int;
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wire btnd_int;
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wire btnr_int;
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wire btnc_int;
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wire [3:0] sw_int;
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taxi_debounce_switch #(
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.WIDTH(9),
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.N(4),
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.RATE(125000)
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)
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debounce_switch_inst (
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.clk(clk_125mhz_int),
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.rst(rst_125mhz_int),
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.in({btnu,
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btnl,
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btnd,
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btnr,
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btnc,
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sw}),
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.out({btnu_int,
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btnl_int,
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btnd_int,
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btnr_int,
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btnc_int,
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sw_int})
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);
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wire uart_rxd_int;
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wire uart_rts_int;
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taxi_sync_signal #(
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.WIDTH(2),
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.N(2)
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)
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sync_signal_inst (
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.clk(clk_125mhz_int),
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.in({uart_rxd, uart_rts}),
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.out({uart_rxd_int, uart_rts_int})
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);
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// SGMII interface to PHY
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wire phy_gmii_clk_int;
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wire phy_gmii_rst_int;
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wire phy_gmii_clk_en_int;
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wire [7:0] phy_gmii_txd_int;
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wire phy_gmii_tx_en_int;
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wire phy_gmii_tx_er_int;
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wire [7:0] phy_gmii_rxd_int;
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wire phy_gmii_rx_dv_int;
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wire phy_gmii_rx_er_int;
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wire [15:0] pcspma_status_vector;
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wire pcspma_status_link_status = pcspma_status_vector[0];
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wire pcspma_status_link_synchronization = pcspma_status_vector[1];
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wire pcspma_status_rudi_c = pcspma_status_vector[2];
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wire pcspma_status_rudi_i = pcspma_status_vector[3];
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wire pcspma_status_rudi_invalid = pcspma_status_vector[4];
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wire pcspma_status_rxdisperr = pcspma_status_vector[5];
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wire pcspma_status_rxnotintable = pcspma_status_vector[6];
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wire pcspma_status_phy_link_status = pcspma_status_vector[7];
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wire [1:0] pcspma_status_remote_fault_encdg = pcspma_status_vector[9:8];
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wire [1:0] pcspma_status_speed = pcspma_status_vector[11:10];
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wire pcspma_status_duplex = pcspma_status_vector[12];
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wire pcspma_status_remote_fault = pcspma_status_vector[13];
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wire [1:0] pcspma_status_pause = pcspma_status_vector[15:14];
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wire [4:0] pcspma_config_vector;
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assign pcspma_config_vector[4] = 1'b1; // autonegotiation enable
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assign pcspma_config_vector[3] = 1'b0; // isolate
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assign pcspma_config_vector[2] = 1'b0; // power down
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assign pcspma_config_vector[1] = 1'b0; // loopback enable
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assign pcspma_config_vector[0] = 1'b0; // unidirectional enable
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wire [15:0] pcspma_an_config_vector;
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assign pcspma_an_config_vector[15] = 1'b1; // SGMII link status
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assign pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge
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assign pcspma_an_config_vector[13:12] = 2'b01; // full duplex
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assign pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed
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assign pcspma_an_config_vector[9] = 1'b0; // reserved
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assign pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved
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assign pcspma_an_config_vector[6] = 1'b0; // reserved
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assign pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved
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assign pcspma_an_config_vector[4:1] = 4'b0000; // reserved
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assign pcspma_an_config_vector[0] = 1'b1; // SGMII
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sgmii_pcs_pma_0
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eth_pcspma (
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// SGMII
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.txp (phy_sgmii_tx_p),
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.txn (phy_sgmii_tx_n),
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.rxp (phy_sgmii_rx_p),
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.rxn (phy_sgmii_rx_n),
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// Ref clock from PHY
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.refclk625_p (phy_sgmii_clk_p),
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.refclk625_n (phy_sgmii_clk_n),
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// async reset
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.reset (rst_125mhz_int),
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// clock and reset outputs
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.clk125_out (phy_gmii_clk_int),
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.clk625_out (),
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.clk312_out (),
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.rst_125_out (phy_gmii_rst_int),
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.idelay_rdy_out (),
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.mmcm_locked_out (),
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// MAC clocking
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.sgmii_clk_r (),
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.sgmii_clk_f (),
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.sgmii_clk_en (phy_gmii_clk_en_int),
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// Speed control
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.speed_is_10_100 (pcspma_status_speed != 2'b10),
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.speed_is_100 (pcspma_status_speed == 2'b01),
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// Internal GMII
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.gmii_txd (phy_gmii_txd_int),
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.gmii_tx_en (phy_gmii_tx_en_int),
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.gmii_tx_er (phy_gmii_tx_er_int),
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.gmii_rxd (phy_gmii_rxd_int),
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.gmii_rx_dv (phy_gmii_rx_dv_int),
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.gmii_rx_er (phy_gmii_rx_er_int),
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.gmii_isolate (),
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// Configuration
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.configuration_vector (pcspma_config_vector),
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.an_interrupt (),
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.an_adv_config_vector (pcspma_an_config_vector),
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.an_restart_config (1'b0),
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// Status
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.status_vector (pcspma_status_vector),
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.signal_detect (1'b1)
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);
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wire [7:0] led_int;
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// SGMII interface debug:
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// SW12:1 (sw[3]) off for payload byte, on for status vector
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// SW12:4 (sw[0]) off for LSB of status vector, on for MSB
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assign led = sw[3] ? (sw[0] ? pcspma_status_vector[15:8] : pcspma_status_vector[7:0]) : led_int;
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// Flash
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wire [3:0] flash_dq_int;
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wire [15:0] flash_dq_i_int;
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wire [15:0] flash_dq_o_int;
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wire flash_dq_oe_int;
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wire [23:0] flash_addr_int;
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wire [1:0] flash_region_int;
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wire flash_region_oe_int;
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wire flash_ce_n_int;
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wire flash_oe_n_int;
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wire flash_we_n_int;
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wire flash_adv_n_int;
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logic [15:0] flash_dq_o_reg;
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logic flash_dq_oe_reg;
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logic [23:0] flash_addr_reg;
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logic [1:0] flash_region_reg;
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logic flash_region_oe_reg;
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logic flash_ce_n_reg;
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logic flash_oe_n_reg;
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logic flash_we_n_reg;
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logic flash_adv_n_reg;
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always_ff @(posedge pcie_user_clk) begin
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flash_dq_o_reg <= flash_dq_o_int;
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flash_dq_oe_reg <= flash_dq_oe_int;
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flash_addr_reg <= flash_addr_int;
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flash_region_reg <= flash_region_int;
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flash_region_oe_reg <= flash_region_oe_int;
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flash_ce_n_reg <= flash_ce_n_int;
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flash_oe_n_reg <= flash_oe_n_int;
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flash_we_n_reg <= flash_we_n_int;
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flash_adv_n_reg <= flash_adv_n_int;
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end
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assign flash_dq[15:4] = flash_dq_oe_reg ? flash_dq_o_reg[15:4] : 12'hzzz;
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assign flash_addr = flash_addr_reg;
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assign flash_region = flash_region_oe_reg ? flash_region_reg : 2'bz;
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assign flash_oe_n = flash_oe_n_reg;
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assign flash_we_n = flash_we_n_reg;
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assign flash_adv_n = flash_adv_n_reg;
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taxi_sync_signal #(
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.WIDTH(16),
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.N(2)
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)
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flash_sync_signal_inst (
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.clk(pcie_user_clk),
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.in({flash_dq, flash_dq_int}),
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.out(flash_dq_i_int)
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);
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STARTUPE3
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startupe3_inst (
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.CFGCLK(),
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.CFGMCLK(),
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.DI(flash_dq_int),
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.DO(flash_dq_o_reg[3:0]),
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.DTS({4{~flash_dq_oe_reg}}),
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.EOS(),
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.FCSBO(flash_ce_n_reg),
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.FCSBTS(1'b0),
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.GSR(1'b0),
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.GTS(1'b0),
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.KEYCLEARB(1'b1),
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.PACK(1'b0),
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.PREQ(),
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.USRCCLKO(1'b0),
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.USRCCLKTS(1'b1),
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.USRDONEO(1'b0),
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.USRDONETS(1'b1)
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);
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// FPGA boot
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wire fpga_boot;
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wire fpga_boot_sync;
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taxi_sync_signal #(
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.WIDTH(1),
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.N(2)
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)
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fpga_boot_sync_inst (
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.clk(clk_125mhz_int),
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.in({fpga_boot}),
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.out({fpga_boot_sync})
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);
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wire icap_avail;
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logic [2:0] icap_state_reg = 0;
|
|
logic icap_csib_reg = 1'b1;
|
|
logic icap_rdwrb_reg = 1'b0;
|
|
logic [31:0] icap_di_reg = 32'hffffffff;
|
|
|
|
wire [31:0] icap_di_rev;
|
|
|
|
assign icap_di_rev[ 7] = icap_di_reg[ 0];
|
|
assign icap_di_rev[ 6] = icap_di_reg[ 1];
|
|
assign icap_di_rev[ 5] = icap_di_reg[ 2];
|
|
assign icap_di_rev[ 4] = icap_di_reg[ 3];
|
|
assign icap_di_rev[ 3] = icap_di_reg[ 4];
|
|
assign icap_di_rev[ 2] = icap_di_reg[ 5];
|
|
assign icap_di_rev[ 1] = icap_di_reg[ 6];
|
|
assign icap_di_rev[ 0] = icap_di_reg[ 7];
|
|
|
|
assign icap_di_rev[15] = icap_di_reg[ 8];
|
|
assign icap_di_rev[14] = icap_di_reg[ 9];
|
|
assign icap_di_rev[13] = icap_di_reg[10];
|
|
assign icap_di_rev[12] = icap_di_reg[11];
|
|
assign icap_di_rev[11] = icap_di_reg[12];
|
|
assign icap_di_rev[10] = icap_di_reg[13];
|
|
assign icap_di_rev[ 9] = icap_di_reg[14];
|
|
assign icap_di_rev[ 8] = icap_di_reg[15];
|
|
|
|
assign icap_di_rev[23] = icap_di_reg[16];
|
|
assign icap_di_rev[22] = icap_di_reg[17];
|
|
assign icap_di_rev[21] = icap_di_reg[18];
|
|
assign icap_di_rev[20] = icap_di_reg[19];
|
|
assign icap_di_rev[19] = icap_di_reg[20];
|
|
assign icap_di_rev[18] = icap_di_reg[21];
|
|
assign icap_di_rev[17] = icap_di_reg[22];
|
|
assign icap_di_rev[16] = icap_di_reg[23];
|
|
|
|
assign icap_di_rev[31] = icap_di_reg[24];
|
|
assign icap_di_rev[30] = icap_di_reg[25];
|
|
assign icap_di_rev[29] = icap_di_reg[26];
|
|
assign icap_di_rev[28] = icap_di_reg[27];
|
|
assign icap_di_rev[27] = icap_di_reg[28];
|
|
assign icap_di_rev[26] = icap_di_reg[29];
|
|
assign icap_di_rev[25] = icap_di_reg[30];
|
|
assign icap_di_rev[24] = icap_di_reg[31];
|
|
|
|
always_ff @(posedge clk_125mhz_int) begin
|
|
case (icap_state_reg)
|
|
0: begin
|
|
icap_state_reg <= 0;
|
|
icap_csib_reg <= 1'b1;
|
|
icap_rdwrb_reg <= 1'b0;
|
|
icap_di_reg <= 32'hffffffff; // dummy word
|
|
|
|
if (fpga_boot_sync && icap_avail) begin
|
|
icap_state_reg <= 1;
|
|
icap_csib_reg <= 1'b0;
|
|
icap_rdwrb_reg <= 1'b0;
|
|
icap_di_reg <= 32'hffffffff; // dummy word
|
|
end
|
|
end
|
|
1: begin
|
|
icap_state_reg <= 2;
|
|
icap_csib_reg <= 1'b0;
|
|
icap_rdwrb_reg <= 1'b0;
|
|
icap_di_reg <= 32'hAA995566; // sync word
|
|
end
|
|
2: begin
|
|
icap_state_reg <= 3;
|
|
icap_csib_reg <= 1'b0;
|
|
icap_rdwrb_reg <= 1'b0;
|
|
icap_di_reg <= 32'h20000000; // type 1 noop
|
|
end
|
|
3: begin
|
|
icap_state_reg <= 4;
|
|
icap_csib_reg <= 1'b0;
|
|
icap_rdwrb_reg <= 1'b0;
|
|
icap_di_reg <= 32'h30008001; // write 1 word to CMD
|
|
end
|
|
4: begin
|
|
icap_state_reg <= 5;
|
|
icap_csib_reg <= 1'b0;
|
|
icap_rdwrb_reg <= 1'b0;
|
|
icap_di_reg <= 32'h0000000F; // IPROG
|
|
end
|
|
5: begin
|
|
icap_state_reg <= 0;
|
|
icap_csib_reg <= 1'b0;
|
|
icap_rdwrb_reg <= 1'b0;
|
|
icap_di_reg <= 32'h20000000; // type 1 noop
|
|
end
|
|
endcase
|
|
end
|
|
|
|
ICAPE3
|
|
icape3_inst (
|
|
.AVAIL(icap_avail),
|
|
.CLK(clk_125mhz_int),
|
|
.CSIB(icap_csib_reg),
|
|
.I(icap_di_rev),
|
|
.O(),
|
|
.PRDONE(),
|
|
.PRERROR(),
|
|
.RDWRB(icap_rdwrb_reg)
|
|
);
|
|
|
|
// PCIe
|
|
localparam AXIS_PCIE_DATA_W = 256;
|
|
localparam AXIS_PCIE_KEEP_W = (AXIS_PCIE_DATA_W/32);
|
|
localparam AXIS_PCIE_RC_USER_W = 75;
|
|
localparam AXIS_PCIE_RQ_USER_W = 60;
|
|
localparam AXIS_PCIE_CQ_USER_W = 85;
|
|
localparam AXIS_PCIE_CC_USER_W = 33;
|
|
localparam RC_STRADDLE = 1'b0; // AXIS_PCIE_DATA_W >= 256;
|
|
|
|
localparam RQ_SEQ_NUM_W = AXIS_PCIE_RQ_USER_W == 60 ? 4 : 6;
|
|
localparam RQ_SEQ_NUM_EN = 1;
|
|
|
|
localparam PCIE_TAG_CNT = AXIS_PCIE_RQ_USER_W == 60 ? 64 : 256;
|
|
localparam BAR0_APERTURE = 24;
|
|
|
|
taxi_axis_if #(
|
|
.DATA_W(AXIS_PCIE_DATA_W),
|
|
.KEEP_EN(1),
|
|
.KEEP_W(AXIS_PCIE_KEEP_W),
|
|
.USER_EN(1),
|
|
.USER_W(AXIS_PCIE_CQ_USER_W)
|
|
) axis_pcie_cq();
|
|
|
|
taxi_axis_if #(
|
|
.DATA_W(AXIS_PCIE_DATA_W),
|
|
.KEEP_EN(1),
|
|
.KEEP_W(AXIS_PCIE_KEEP_W),
|
|
.USER_EN(1),
|
|
.USER_W(AXIS_PCIE_CC_USER_W)
|
|
) axis_pcie_cc();
|
|
|
|
taxi_axis_if #(
|
|
.DATA_W(AXIS_PCIE_DATA_W),
|
|
.KEEP_EN(1),
|
|
.KEEP_W(AXIS_PCIE_KEEP_W),
|
|
.USER_EN(1),
|
|
.USER_W(AXIS_PCIE_RQ_USER_W)
|
|
) axis_pcie_rq();
|
|
|
|
taxi_axis_if #(
|
|
.DATA_W(AXIS_PCIE_DATA_W),
|
|
.KEEP_EN(1),
|
|
.KEEP_W(AXIS_PCIE_KEEP_W),
|
|
.USER_EN(1),
|
|
.USER_W(AXIS_PCIE_RC_USER_W)
|
|
) axis_pcie_rc();
|
|
|
|
wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num;
|
|
wire pcie_rq_seq_num_vld;
|
|
|
|
wire [2:0] cfg_max_payload;
|
|
wire [2:0] cfg_max_read_req;
|
|
wire [3:0] cfg_rcb_status;
|
|
|
|
wire [18:0] cfg_mgmt_addr;
|
|
wire cfg_mgmt_write;
|
|
wire [31:0] cfg_mgmt_write_data;
|
|
wire [3:0] cfg_mgmt_byte_enable;
|
|
wire cfg_mgmt_read;
|
|
wire [31:0] cfg_mgmt_read_data;
|
|
wire cfg_mgmt_read_write_done;
|
|
|
|
wire [7:0] cfg_fc_ph;
|
|
wire [11:0] cfg_fc_pd;
|
|
wire [7:0] cfg_fc_nph;
|
|
wire [11:0] cfg_fc_npd;
|
|
wire [7:0] cfg_fc_cplh;
|
|
wire [11:0] cfg_fc_cpld;
|
|
wire [2:0] cfg_fc_sel;
|
|
|
|
wire cfg_ext_read_received;
|
|
wire cfg_ext_write_received;
|
|
wire [9:0] cfg_ext_register_number;
|
|
wire [7:0] cfg_ext_function_number;
|
|
wire [31:0] cfg_ext_write_data;
|
|
wire [3:0] cfg_ext_write_byte_enable;
|
|
wire [31:0] cfg_ext_read_data;
|
|
wire cfg_ext_read_data_valid;
|
|
|
|
// wire [3:0] cfg_interrupt_msix_enable;
|
|
// wire [3:0] cfg_interrupt_msix_mask;
|
|
// wire [251:0] cfg_interrupt_msix_vf_enable;
|
|
// wire [251:0] cfg_interrupt_msix_vf_mask;
|
|
// wire [63:0] cfg_interrupt_msix_address;
|
|
// wire [31:0] cfg_interrupt_msix_data;
|
|
// wire cfg_interrupt_msix_int;
|
|
// wire [1:0] cfg_interrupt_msix_vec_pending;
|
|
// wire cfg_interrupt_msix_vec_pending_status;
|
|
// wire cfg_interrupt_msix_sent;
|
|
// wire cfg_interrupt_msix_fail;
|
|
// wire [7:0] cfg_interrupt_msi_function_number;
|
|
|
|
wire [3:0] cfg_interrupt_msi_enable;
|
|
wire [11:0] cfg_interrupt_msi_mmenable;
|
|
wire cfg_interrupt_msi_mask_update;
|
|
wire [31:0] cfg_interrupt_msi_data;
|
|
wire [3:0] cfg_interrupt_msi_select;
|
|
wire [31:0] cfg_interrupt_msi_int;
|
|
wire [31:0] cfg_interrupt_msi_pending_status;
|
|
wire cfg_interrupt_msi_pending_status_data_enable;
|
|
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
|
wire cfg_interrupt_msi_sent;
|
|
wire cfg_interrupt_msi_fail;
|
|
wire [2:0] cfg_interrupt_msi_attr;
|
|
wire cfg_interrupt_msi_tph_present;
|
|
wire [1:0] cfg_interrupt_msi_tph_type;
|
|
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
|
wire [3:0] cfg_interrupt_msi_function_number;
|
|
|
|
wire stat_err_cor;
|
|
wire stat_err_uncor;
|
|
|
|
wire pcie_sys_clk;
|
|
wire pcie_sys_clk_gt;
|
|
|
|
IBUFDS_GTE3 #(
|
|
.REFCLK_HROW_CK_SEL(2'b00)
|
|
)
|
|
ibufds_gte3_pcie_refclk_inst (
|
|
.I (pcie_refclk_p),
|
|
.IB (pcie_refclk_n),
|
|
.CEB (1'b0),
|
|
.O (pcie_sys_clk_gt),
|
|
.ODIV2 (pcie_sys_clk)
|
|
);
|
|
|
|
pcie3_ultrascale_0
|
|
pcie3_ultrascale_inst (
|
|
.pci_exp_txn(pcie_tx_n),
|
|
.pci_exp_txp(pcie_tx_p),
|
|
.pci_exp_rxn(pcie_rx_n),
|
|
.pci_exp_rxp(pcie_rx_p),
|
|
.user_clk(pcie_user_clk),
|
|
.user_reset(pcie_user_rst),
|
|
.user_lnk_up(),
|
|
|
|
.s_axis_rq_tdata(axis_pcie_rq.tdata),
|
|
.s_axis_rq_tkeep(axis_pcie_rq.tkeep),
|
|
.s_axis_rq_tlast(axis_pcie_rq.tlast),
|
|
.s_axis_rq_tready(axis_pcie_rq.tready),
|
|
.s_axis_rq_tuser(axis_pcie_rq.tuser),
|
|
.s_axis_rq_tvalid(axis_pcie_rq.tvalid),
|
|
|
|
.m_axis_rc_tdata(axis_pcie_rc.tdata),
|
|
.m_axis_rc_tkeep(axis_pcie_rc.tkeep),
|
|
.m_axis_rc_tlast(axis_pcie_rc.tlast),
|
|
.m_axis_rc_tready(axis_pcie_rc.tready),
|
|
.m_axis_rc_tuser(axis_pcie_rc.tuser),
|
|
.m_axis_rc_tvalid(axis_pcie_rc.tvalid),
|
|
|
|
.m_axis_cq_tdata(axis_pcie_cq.tdata),
|
|
.m_axis_cq_tkeep(axis_pcie_cq.tkeep),
|
|
.m_axis_cq_tlast(axis_pcie_cq.tlast),
|
|
.m_axis_cq_tready(axis_pcie_cq.tready),
|
|
.m_axis_cq_tuser(axis_pcie_cq.tuser),
|
|
.m_axis_cq_tvalid(axis_pcie_cq.tvalid),
|
|
|
|
.s_axis_cc_tdata(axis_pcie_cc.tdata),
|
|
.s_axis_cc_tkeep(axis_pcie_cc.tkeep),
|
|
.s_axis_cc_tlast(axis_pcie_cc.tlast),
|
|
.s_axis_cc_tready(axis_pcie_cc.tready),
|
|
.s_axis_cc_tuser(axis_pcie_cc.tuser),
|
|
.s_axis_cc_tvalid(axis_pcie_cc.tvalid),
|
|
|
|
.pcie_rq_seq_num(pcie_rq_seq_num),
|
|
.pcie_rq_seq_num_vld(pcie_rq_seq_num_vld),
|
|
.pcie_rq_tag(),
|
|
.pcie_rq_tag_av(),
|
|
.pcie_rq_tag_vld(),
|
|
|
|
.pcie_tfc_nph_av(),
|
|
.pcie_tfc_npd_av(),
|
|
|
|
.pcie_cq_np_req(1'b1),
|
|
.pcie_cq_np_req_count(),
|
|
|
|
.cfg_phy_link_down(),
|
|
.cfg_phy_link_status(),
|
|
.cfg_negotiated_width(),
|
|
.cfg_current_speed(),
|
|
.cfg_max_payload(cfg_max_payload),
|
|
.cfg_max_read_req(cfg_max_read_req),
|
|
.cfg_function_status(),
|
|
.cfg_function_power_state(),
|
|
.cfg_vf_status(),
|
|
.cfg_vf_power_state(),
|
|
.cfg_link_power_state(),
|
|
|
|
.cfg_mgmt_addr(cfg_mgmt_addr),
|
|
.cfg_mgmt_write(cfg_mgmt_write),
|
|
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
|
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
|
.cfg_mgmt_read(cfg_mgmt_read),
|
|
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
|
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
|
.cfg_mgmt_type1_cfg_reg_access(1'b0),
|
|
|
|
.cfg_err_cor_out(),
|
|
.cfg_err_nonfatal_out(),
|
|
.cfg_err_fatal_out(),
|
|
.cfg_local_error(),
|
|
.cfg_ltr_enable(),
|
|
.cfg_ltssm_state(),
|
|
.cfg_rcb_status(cfg_rcb_status),
|
|
.cfg_dpa_substate_change(),
|
|
.cfg_obff_enable(),
|
|
.cfg_pl_status_change(),
|
|
.cfg_tph_requester_enable(),
|
|
.cfg_tph_st_mode(),
|
|
.cfg_vf_tph_requester_enable(),
|
|
.cfg_vf_tph_st_mode(),
|
|
|
|
.cfg_msg_received(),
|
|
.cfg_msg_received_data(),
|
|
.cfg_msg_received_type(),
|
|
.cfg_msg_transmit(1'b0),
|
|
.cfg_msg_transmit_type(3'd0),
|
|
.cfg_msg_transmit_data(32'd0),
|
|
.cfg_msg_transmit_done(),
|
|
|
|
.cfg_fc_ph(cfg_fc_ph),
|
|
.cfg_fc_pd(cfg_fc_pd),
|
|
.cfg_fc_nph(cfg_fc_nph),
|
|
.cfg_fc_npd(cfg_fc_npd),
|
|
.cfg_fc_cplh(cfg_fc_cplh),
|
|
.cfg_fc_cpld(cfg_fc_cpld),
|
|
.cfg_fc_sel(cfg_fc_sel),
|
|
|
|
.cfg_per_func_status_control(3'd0),
|
|
.cfg_per_func_status_data(),
|
|
.cfg_per_function_number(4'd0),
|
|
.cfg_per_function_output_request(1'b0),
|
|
.cfg_per_function_update_done(),
|
|
|
|
.cfg_dsn(64'd0),
|
|
|
|
.cfg_power_state_change_ack(1'b1),
|
|
.cfg_power_state_change_interrupt(),
|
|
|
|
.cfg_err_cor_in(stat_err_cor),
|
|
.cfg_err_uncor_in(stat_err_uncor),
|
|
.cfg_flr_in_process(),
|
|
.cfg_flr_done(4'd0),
|
|
.cfg_vf_flr_in_process(),
|
|
.cfg_vf_flr_done(8'd0),
|
|
|
|
.cfg_link_training_enable(1'b1),
|
|
|
|
.cfg_ext_read_received(cfg_ext_read_received),
|
|
.cfg_ext_write_received(cfg_ext_write_received),
|
|
.cfg_ext_register_number(cfg_ext_register_number),
|
|
.cfg_ext_function_number(cfg_ext_function_number),
|
|
.cfg_ext_write_data(cfg_ext_write_data),
|
|
.cfg_ext_write_byte_enable(cfg_ext_write_byte_enable),
|
|
.cfg_ext_read_data(cfg_ext_read_data),
|
|
.cfg_ext_read_data_valid(cfg_ext_read_data_valid),
|
|
|
|
.cfg_interrupt_int(4'd0),
|
|
.cfg_interrupt_pending(4'd0),
|
|
.cfg_interrupt_sent(),
|
|
// .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
|
// .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
|
// .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
|
// .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
|
// .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
|
// .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
|
// .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
|
// .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
|
// .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
|
// .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
|
|
// .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
|
|
// .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
|
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
|
.cfg_interrupt_msi_vf_enable(),
|
|
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
|
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
|
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
|
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
|
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
|
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
|
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
|
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
|
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
|
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
|
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
|
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
|
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
|
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
|
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
|
|
|
.cfg_hot_reset_out(),
|
|
|
|
.cfg_config_space_enable(1'b1),
|
|
.cfg_req_pm_transition_l23_ready(1'b0),
|
|
.cfg_hot_reset_in(1'b0),
|
|
|
|
.cfg_ds_port_number(8'd0),
|
|
.cfg_ds_bus_number(8'd0),
|
|
.cfg_ds_device_number(5'd0),
|
|
.cfg_ds_function_number(3'd0),
|
|
|
|
.cfg_subsys_vend_id(BOARD_ID >> 16),
|
|
|
|
.sys_clk(pcie_sys_clk),
|
|
.sys_clk_gt(pcie_sys_clk_gt),
|
|
.sys_reset(pcie_reset_n),
|
|
.pcie_perstn1_in(1'b0),
|
|
.pcie_perstn0_out(),
|
|
.pcie_perstn1_out(),
|
|
|
|
.int_qpll1lock_out(),
|
|
.int_qpll1outrefclk_out(),
|
|
.int_qpll1outclk_out(),
|
|
.phy_rdy_out()
|
|
);
|
|
|
|
fpga_core #(
|
|
.SIM(SIM),
|
|
.VENDOR(VENDOR),
|
|
.FAMILY(FAMILY),
|
|
|
|
// FW ID
|
|
.FPGA_ID(FPGA_ID),
|
|
.FW_ID(FW_ID),
|
|
.FW_VER(FW_VER),
|
|
.BOARD_ID(BOARD_ID),
|
|
.BOARD_VER(BOARD_VER),
|
|
.BUILD_DATE(BUILD_DATE),
|
|
.GIT_HASH(GIT_HASH),
|
|
.RELEASE_INFO(RELEASE_INFO),
|
|
|
|
// PTP configuration
|
|
.PTP_TS_EN(PTP_TS_EN),
|
|
|
|
// PCIe interface configuration
|
|
.RQ_SEQ_NUM_W(RQ_SEQ_NUM_W),
|
|
|
|
// AXI lite interface configuration (control)
|
|
.AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W),
|
|
.AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W),
|
|
|
|
// MAC configuration
|
|
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
|
|
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
|
|
.MAC_DATA_W(MAC_DATA_W)
|
|
)
|
|
core_inst (
|
|
/*
|
|
* Clock: 125MHz
|
|
* Synchronous reset
|
|
*/
|
|
.clk_125mhz(clk_125mhz_int),
|
|
.rst_125mhz(rst_125mhz_int),
|
|
|
|
/*
|
|
* GPIO
|
|
*/
|
|
.btnu(btnu_int),
|
|
.btnl(btnl_int),
|
|
.btnd(btnd_int),
|
|
.btnr(btnr_int),
|
|
.btnc(btnc_int),
|
|
.sw(sw_int),
|
|
.led(led_int),
|
|
|
|
/*
|
|
* UART: 115200 bps, 8N1
|
|
*/
|
|
.uart_rxd(uart_rxd_int),
|
|
.uart_txd(uart_txd),
|
|
.uart_rts(uart_rts_int),
|
|
.uart_cts(uart_cts),
|
|
|
|
/*
|
|
* Ethernet: 1000BASE-T SGMII
|
|
*/
|
|
.phy_gmii_clk(phy_gmii_clk_int),
|
|
.phy_gmii_rst(phy_gmii_rst_int),
|
|
.phy_gmii_clk_en(phy_gmii_clk_en_int),
|
|
.phy_gmii_rxd(phy_gmii_rxd_int),
|
|
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
|
|
.phy_gmii_rx_er(phy_gmii_rx_er_int),
|
|
.phy_gmii_txd(phy_gmii_txd_int),
|
|
.phy_gmii_tx_en(phy_gmii_tx_en_int),
|
|
.phy_gmii_tx_er(phy_gmii_tx_er_int),
|
|
.phy_reset_n(phy_reset_n),
|
|
.phy_int_n(phy_int_n),
|
|
|
|
/*
|
|
* Ethernet: QSFP28
|
|
*/
|
|
.qsfp_rx_p(qsfp_rx_p),
|
|
.qsfp_rx_n(qsfp_rx_n),
|
|
.qsfp_tx_p(qsfp_tx_p),
|
|
.qsfp_tx_n(qsfp_tx_n),
|
|
.qsfp_mgt_refclk_0_p(qsfp_mgt_refclk_0_p),
|
|
.qsfp_mgt_refclk_0_n(qsfp_mgt_refclk_0_n),
|
|
// .qsfp_mgt_refclk_1_p(qsfp_mgt_refclk_1_p),
|
|
// .qsfp_mgt_refclk_1_n(qsfp_mgt_refclk_1_n),
|
|
// .qsfp_recclk_p(qsfp_recclk_p),
|
|
// .qsfp_recclk_n(qsfp_recclk_n),
|
|
.qsfp_modsell(qsfp_modsell),
|
|
.qsfp_resetl(qsfp_resetl),
|
|
.qsfp_modprsl(qsfp_modprsl),
|
|
.qsfp_intl(qsfp_intl),
|
|
.qsfp_lpmode(qsfp_lpmode),
|
|
|
|
/*
|
|
* PCIe
|
|
*/
|
|
.pcie_clk(pcie_user_clk),
|
|
.pcie_rst(pcie_user_rst),
|
|
.s_axis_pcie_cq(axis_pcie_cq),
|
|
.m_axis_pcie_cc(axis_pcie_cc),
|
|
.m_axis_pcie_rq(axis_pcie_rq),
|
|
.s_axis_pcie_rc(axis_pcie_rc),
|
|
|
|
.pcie_rq_seq_num(pcie_rq_seq_num),
|
|
.pcie_rq_seq_num_vld(pcie_rq_seq_num_vld),
|
|
|
|
.cfg_max_payload(cfg_max_payload),
|
|
.cfg_max_read_req(cfg_max_read_req),
|
|
.cfg_rcb_status(cfg_rcb_status),
|
|
|
|
.cfg_mgmt_addr(cfg_mgmt_addr),
|
|
.cfg_mgmt_write(cfg_mgmt_write),
|
|
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
|
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
|
.cfg_mgmt_read(cfg_mgmt_read),
|
|
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
|
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
|
|
|
.cfg_fc_ph(cfg_fc_ph),
|
|
.cfg_fc_pd(cfg_fc_pd),
|
|
.cfg_fc_nph(cfg_fc_nph),
|
|
.cfg_fc_npd(cfg_fc_npd),
|
|
.cfg_fc_cplh(cfg_fc_cplh),
|
|
.cfg_fc_cpld(cfg_fc_cpld),
|
|
.cfg_fc_sel(cfg_fc_sel),
|
|
|
|
.cfg_ext_read_received(cfg_ext_read_received),
|
|
.cfg_ext_write_received(cfg_ext_write_received),
|
|
.cfg_ext_register_number(cfg_ext_register_number),
|
|
.cfg_ext_function_number(cfg_ext_function_number),
|
|
.cfg_ext_write_data(cfg_ext_write_data),
|
|
.cfg_ext_write_byte_enable(cfg_ext_write_byte_enable),
|
|
.cfg_ext_read_data(cfg_ext_read_data),
|
|
.cfg_ext_read_data_valid(cfg_ext_read_data_valid),
|
|
|
|
// .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
|
// .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
|
// .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
|
// .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
|
// .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
|
// .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
|
// .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
|
// .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
|
// .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
|
// .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
|
// .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
|
// .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
|
|
|
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
|
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
|
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
|
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
|
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
|
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
|
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
|
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
|
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
|
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
|
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
|
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
|
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
|
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
|
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
|
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
|
|
|
/*
|
|
* BPI flash
|
|
*/
|
|
.fpga_boot(fpga_boot),
|
|
.flash_dq_i(flash_dq_i_int),
|
|
.flash_dq_o(flash_dq_o_int),
|
|
.flash_dq_oe(flash_dq_oe_int),
|
|
.flash_addr(flash_addr_int),
|
|
.flash_region(flash_region_int),
|
|
.flash_region_oe(flash_region_oe_int),
|
|
.flash_ce_n(flash_ce_n_int),
|
|
.flash_oe_n(flash_oe_n_int),
|
|
.flash_we_n(flash_we_n_int),
|
|
.flash_adv_n(flash_adv_n_int)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|