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45 lines
1.5 KiB
Tcl
45 lines
1.5 KiB
Tcl
# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2025-2026 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# XDC constraints for the Xilinx Alveo AU200/AU250/VCU1525
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# AU200 part: xcu200-fsgd2104-2-e
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# AU250 part: xcu250-figd2104-2-e
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# VCU1525 part: xcvu9p-fsgd2104-2L-e
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# LEDs
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set_property -dict {LOC BC21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
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set_property -dict {LOC BB21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}]
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set_property -dict {LOC BA20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}]
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set_false_path -to [get_ports {led[*]}]
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set_output_delay 0 [get_ports {led[*]}]
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# Reset button
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set_property -dict {LOC AL20 IOSTANDARD LVCMOS12} [get_ports reset]
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set_false_path -from [get_ports {reset}]
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set_input_delay 0 [get_ports {reset}]
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# DIP switches
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set_property -dict {LOC AN22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}]
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set_property -dict {LOC AM19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}]
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set_property -dict {LOC AL19 IOSTANDARD LVCMOS12} [get_ports {sw[2]}]
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set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports {sw[3]}]
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set_false_path -from [get_ports {sw[*]}]
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set_input_delay 0 [get_ports {sw[*]}]
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# UART (U27 FT4232H channel CDBUS)
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set_property -dict {LOC BB20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] ;# U27.39 CDBUS1 RXD
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set_property -dict {LOC BF18 IOSTANDARD LVCMOS12} [get_ports uart_rxd] ;# U27.38 CDBUS0 TXD
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set_false_path -to [get_ports {uart_txd}]
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set_output_delay 0 [get_ports {uart_txd}]
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set_false_path -from [get_ports {uart_rxd}]
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set_input_delay 0 [get_ports {uart_rxd}]
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