mirror of
https://github.com/fpganinja/taxi.git
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166 lines
4.1 KiB
Python
166 lines
4.1 KiB
Python
#!/usr/bin/env python
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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"""
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Copyright (c) 2020-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import logging
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import os
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import cocotb_test.simulator
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge, Timer
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from cocotbext.eth import PtpClock
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class TB:
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start())
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self.ptp_clock = PtpClock(
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ts_tod=dut.input_ts_tod,
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ts_step=dut.input_ts_tod_step,
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clock=dut.clk,
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reset=dut.rst,
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period_ns=6.4
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)
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dut.enable.setimmediatevalue(0)
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dut.input_start.setimmediatevalue(0)
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dut.input_start_valid.setimmediatevalue(0)
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dut.input_period.setimmediatevalue(0)
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dut.input_period_valid.setimmediatevalue(0)
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dut.input_width.setimmediatevalue(0)
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dut.input_width_valid.setimmediatevalue(0)
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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@cocotb.test()
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async def run_test(dut):
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tb = TB(dut)
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await tb.reset()
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dut.enable.value = 1
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await RisingEdge(dut.clk)
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dut.input_start.value = 100 << 16
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dut.input_start_valid.value = 1
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dut.input_period.value = 100 << 16
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dut.input_period_valid.value = 1
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dut.input_width.value = 50 << 16
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dut.input_width_valid.value = 1
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await RisingEdge(dut.clk)
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dut.input_start_valid.value = 0
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dut.input_period_valid.value = 0
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dut.input_width_valid.value = 0
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await Timer(10000, 'ns')
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await RisingEdge(dut.clk)
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dut.input_start.value = 0 << 16
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dut.input_start_valid.value = 1
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dut.input_period.value = 100 << 16
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dut.input_period_valid.value = 1
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dut.input_width.value = 50 << 16
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dut.input_width_valid.value = 1
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await RisingEdge(dut.clk)
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dut.input_start_valid.value = 0
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dut.input_period_valid.value = 0
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dut.input_width_valid.value = 0
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await Timer(10000, 'ns')
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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# cocotb-test
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tests_dir = os.path.abspath(os.path.dirname(__file__))
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
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def process_f_files(files):
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lst = {}
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for f in files:
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if f[-2:].lower() == '.f':
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with open(f, 'r') as fp:
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l = fp.read().split()
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for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
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lst[os.path.basename(f)] = f
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else:
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lst[os.path.basename(f)] = f
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return list(lst.values())
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def test_taxi_ptp_perout(request):
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dut = "taxi_ptp_perout"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = dut
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verilog_sources = [
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os.path.join(rtl_dir, "ptp", f"{dut}.sv"),
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]
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verilog_sources = process_f_files(verilog_sources)
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parameters = {}
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parameters['FNS_EN'] = "1'b1"
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parameters['OUT_START_S'] = 0
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parameters['OUT_START_NS'] = 0
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parameters['OUT_START_FNS'] = 0x0000
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parameters['OUT_PERIOD_S'] = 1
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parameters['OUT_PERIOD_NS'] = 0
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parameters['OUT_PERIOD_FNS'] = 0x0000
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parameters['OUT_WIDTH_S'] = 0
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parameters['OUT_WIDTH_NS'] = 1000
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parameters['OUT_WIDTH_FNS'] = 0x0000
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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simulator="verilator",
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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