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https://github.com/fpganinja/taxi.git
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123 lines
2.8 KiB
Systemverilog
123 lines
2.8 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* XFCP AXI module
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*/
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module taxi_xfcp_mod_axi #
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(
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parameter logic [15:0] XFCP_ID_TYPE = 16'h8001,
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parameter XFCP_ID_STR = "AXI Master",
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parameter logic [8*16-1:0] XFCP_EXT_ID = 0,
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parameter XFCP_EXT_ID_STR = "",
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parameter COUNT_SIZE = 16
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* XFCP upstream port
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*/
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taxi_axis_if.snk xfcp_usp_ds,
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taxi_axis_if.src xfcp_usp_us,
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/*
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* AXI master interface
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*/
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taxi_axi_if.wr_mst m_axi_wr,
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taxi_axi_if.rd_mst m_axi_rd
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);
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taxi_axil_if #(
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.DATA_W(m_axi_wr.DATA_W),
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.ADDR_W(m_axi_wr.ADDR_W),
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.STRB_W(m_axi_wr.STRB_W)
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) axil_if();
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// AW
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assign m_axi_wr.awid = '0;
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assign m_axi_wr.awaddr = axil_if.awaddr;
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assign m_axi_wr.awlen = '0;
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assign m_axi_wr.awsize = 3'($clog2(m_axi_wr.STRB_W));
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assign m_axi_wr.awburst = 2'b01;
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assign m_axi_wr.awlock = 1'b0;
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assign m_axi_wr.awcache = 4'b0011;
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assign m_axi_wr.awprot = axil_if.awprot;
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assign m_axi_wr.awqos = 4'd0;
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assign m_axi_wr.awregion = 4'd0;
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assign m_axi_wr.awuser = axil_if.awuser;
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assign m_axi_wr.awvalid = axil_if.awvalid;
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assign axil_if.awready = m_axi_wr.awready;
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// W
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assign m_axi_wr.wdata = axil_if.wdata;
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assign m_axi_wr.wstrb = axil_if.wstrb;
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assign m_axi_wr.wlast = 1'b1;
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assign m_axi_wr.wuser = axil_if.wuser;
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assign m_axi_wr.wvalid = axil_if.wvalid;
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assign axil_if.wready = m_axi_wr.wready;
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// B
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assign axil_if.bresp = m_axi_wr.bresp;
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assign axil_if.buser = m_axi_wr.buser;
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assign axil_if.bvalid = m_axi_wr.bvalid;
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assign m_axi_wr.bready = axil_if.bready;
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// AR
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assign m_axi_rd.arid = '0;
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assign m_axi_rd.araddr = axil_if.araddr;
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assign m_axi_rd.arlen = '0;
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assign m_axi_rd.arsize = 3'($clog2(m_axi_wr.STRB_W));
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assign m_axi_rd.arburst = 2'b01;
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assign m_axi_rd.arlock = 1'b0;
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assign m_axi_rd.arcache = 4'b0011;
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assign m_axi_rd.arprot = axil_if.arprot;
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assign m_axi_rd.arqos = 4'd0;
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assign m_axi_rd.arregion = 4'd0;
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assign m_axi_rd.aruser = axil_if.aruser;
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assign m_axi_rd.arvalid = axil_if.arvalid;
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assign axil_if.arready = m_axi_rd.arready;
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// R
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assign axil_if.rdata = m_axi_rd.rdata;
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assign axil_if.rresp = m_axi_rd.rresp;
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assign axil_if.ruser = m_axi_rd.ruser;
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assign axil_if.rvalid = m_axi_rd.rvalid;
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assign m_axi_rd.rready = axil_if.rready;
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taxi_xfcp_mod_axil #(
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.XFCP_ID_TYPE(XFCP_ID_TYPE),
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.XFCP_ID_STR(XFCP_ID_STR),
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.XFCP_EXT_ID(XFCP_EXT_ID),
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.XFCP_EXT_ID_STR(XFCP_EXT_ID_STR),
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.COUNT_SIZE(COUNT_SIZE)
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)
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xfcp_mod_axil_inst (
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.clk(clk),
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.rst(rst),
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/*
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* XFCP upstream port
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*/
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.xfcp_usp_ds(xfcp_usp_ds),
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.xfcp_usp_us(xfcp_usp_us),
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/*
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* AXI lite master interface
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*/
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.m_axil_wr(axil_if),
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.m_axil_rd(axil_if)
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);
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endmodule
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`resetall
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