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897 lines
29 KiB
Systemverilog
897 lines
29 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2015-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* I2C master
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*/
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module taxi_i2c_master (
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input wire logic clk,
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input wire logic rst,
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/*
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* Host interface
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*/
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taxi_axis_if.snk s_axis_cmd,
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taxi_axis_if.snk s_axis_data,
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taxi_axis_if.src m_axis_data,
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/*
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* I2C interface
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*/
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input wire logic scl_i,
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output wire logic scl_o,
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output wire logic scl_t,
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input wire logic sda_i,
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output wire logic sda_o,
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output wire logic sda_t,
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/*
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* Status
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*/
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output wire logic busy,
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output wire logic bus_control,
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output wire logic bus_active,
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output wire logic missed_ack,
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/*
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* Configuration
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*/
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input wire logic [15:0] prescale,
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input wire logic stop_on_idle
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);
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/*
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I2C
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Read
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__ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
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sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_\_R___A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A____/
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____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
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scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP
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Write
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__ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
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sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_/ W \_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_/ N \__/
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____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
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scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP
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Command encoding:
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cmd[6:0] address
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cmd[7] start
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cmd[8] read
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cmd[9] write
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cmd[10] write_multiple
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cmd[11] stop
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Commands:
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read
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read data byte
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set start to force generation of a start condition
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start is implied when bus is inactive or active with write or different address
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set stop to issue a stop condition after reading current byte
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if stop is set with read command, then m_axis_data_tlast will be set
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write
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write data byte
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set start to force generation of a start condition
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start is implied when bus is inactive or active with read or different address
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set stop to issue a stop condition after writing current byte
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write multiple
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write multiple data bytes (until s_axis_data_tlast)
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set start to force generation of a start condition
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start is implied when bus is inactive or active with read or different address
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set stop to issue a stop condition after writing block
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stop
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issue stop condition if bus is active
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Status:
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busy
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module is communicating over the bus
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bus_control
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module has control of bus in active state
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bus_active
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bus is active, not necessarily controlled by this module
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missed_ack
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strobed when a slave ack is missed
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Parameters:
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prescale
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set prescale to 1/4 of the minimum clock period in units
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of input clk cycles (prescale = Fclk / (FI2Cclk * 4))
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stop_on_idle
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automatically issue stop when command input is not valid
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Example of interfacing with tristate pins:
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(this will work for any tristate bus)
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assign scl_i = scl_pin;
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assign scl_pin = scl_t ? 1'bz : scl_o;
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assign sda_i = sda_pin;
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assign sda_pin = sda_t ? 1'bz : sda_o;
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Equivalent code that does not use *_t connections:
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(we can get away with this because I2C is open-drain)
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assign scl_i = scl_pin;
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assign scl_pin = scl_o ? 1'bz : 1'b0;
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assign sda_i = sda_pin;
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assign sda_pin = sda_o ? 1'bz : 1'b0;
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Example of two interconnected I2C devices:
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assign scl_1_i = scl_1_o & scl_2_o;
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assign scl_2_i = scl_1_o & scl_2_o;
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assign sda_1_i = sda_1_o & sda_2_o;
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assign sda_2_i = sda_1_o & sda_2_o;
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Example of two I2C devices sharing the same pins:
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assign scl_1_i = scl_pin;
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assign scl_2_i = scl_pin;
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assign scl_pin = (scl_1_o & scl_2_o) ? 1'bz : 1'b0;
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assign sda_1_i = sda_pin;
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assign sda_2_i = sda_pin;
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assign sda_pin = (sda_1_o & sda_2_o) ? 1'bz : 1'b0;
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Notes:
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scl_o should not be connected directly to scl_i, only via AND logic or a tristate
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I/O pin. This would prevent devices from stretching the clock period.
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*/
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localparam [3:0]
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STATE_IDLE = 4'd0,
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STATE_ACTIVE_WRITE = 4'd1,
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STATE_ACTIVE_READ = 4'd2,
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STATE_START_WAIT = 4'd3,
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STATE_START = 4'd4,
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STATE_ADDRESS_1 = 4'd5,
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STATE_ADDRESS_2 = 4'd6,
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STATE_WRITE_1 = 4'd7,
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STATE_WRITE_2 = 4'd8,
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STATE_WRITE_3 = 4'd9,
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STATE_READ = 4'd10,
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STATE_STOP = 4'd11;
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logic [3:0] state_reg = STATE_IDLE, state_next;
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localparam [3:0]
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PHY_STATE_IDLE = 4'd0,
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PHY_STATE_ACTIVE = 4'd1,
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PHY_STATE_REPEATED_START_1 = 4'd2,
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PHY_STATE_REPEATED_START_2 = 4'd3,
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PHY_STATE_START_1 = 4'd4,
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PHY_STATE_START_2 = 4'd5,
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PHY_STATE_WRITE_BIT_1 = 4'd6,
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PHY_STATE_WRITE_BIT_2 = 4'd7,
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PHY_STATE_WRITE_BIT_3 = 4'd8,
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PHY_STATE_READ_BIT_1 = 4'd9,
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PHY_STATE_READ_BIT_2 = 4'd10,
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PHY_STATE_READ_BIT_3 = 4'd11,
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PHY_STATE_READ_BIT_4 = 4'd12,
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PHY_STATE_STOP_1 = 4'd13,
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PHY_STATE_STOP_2 = 4'd14,
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PHY_STATE_STOP_3 = 4'd15;
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logic [3:0] phy_state_reg = STATE_IDLE, phy_state_next;
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logic phy_start_bit;
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logic phy_stop_bit;
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logic phy_write_bit;
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logic phy_read_bit;
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logic phy_release_bus;
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logic phy_tx_data;
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logic phy_rx_data_reg = 1'b0, phy_rx_data_next;
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logic [6:0] addr_reg = '0, addr_next;
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logic [7:0] data_reg = '0, data_next;
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logic last_reg = 1'b0, last_next;
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logic mode_read_reg = 1'b0, mode_read_next;
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logic mode_write_multiple_reg = 1'b0, mode_write_multiple_next;
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logic mode_stop_reg = 1'b0, mode_stop_next;
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logic [16:0] delay_reg = '0, delay_next;
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logic delay_scl_reg = 1'b0, delay_scl_next;
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logic delay_sda_reg = 1'b0, delay_sda_next;
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logic [3:0] bit_count_reg = '0, bit_count_next;
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logic s_axis_cmd_ready_reg = 1'b0, s_axis_cmd_ready_next;
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logic s_axis_data_tready_reg = 1'b0, s_axis_data_tready_next;
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logic [7:0] m_axis_data_tdata_reg = '0, m_axis_data_tdata_next;
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logic m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next;
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logic m_axis_data_tlast_reg = 1'b0, m_axis_data_tlast_next;
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logic scl_i_reg = 1'b1;
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logic sda_i_reg = 1'b1;
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logic scl_o_reg = 1'b1, scl_o_next;
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logic sda_o_reg = 1'b1, sda_o_next;
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logic last_scl_i_reg = 1'b1;
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logic last_sda_i_reg = 1'b1;
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logic busy_reg = 1'b0;
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logic bus_active_reg = 1'b0;
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logic bus_control_reg = 1'b0, bus_control_next;
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logic missed_ack_reg = 1'b0, missed_ack_next;
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wire [6:0] s_axis_cmd_address = s_axis_cmd.tdata[6:0];
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wire s_axis_cmd_start = s_axis_cmd.tdata[7];
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wire s_axis_cmd_read = s_axis_cmd.tdata[8];
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wire s_axis_cmd_write = s_axis_cmd.tdata[9];
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wire s_axis_cmd_write_multi = s_axis_cmd.tdata[10];
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wire s_axis_cmd_stop = s_axis_cmd.tdata[11];
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assign s_axis_cmd.tready = s_axis_cmd_ready_reg;
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assign s_axis_data.tready = s_axis_data_tready_reg;
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assign m_axis_data.tdata = m_axis_data_tdata_reg;
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assign m_axis_data.tkeep = '1;
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assign m_axis_data.tstrb = m_axis_data.tkeep;
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assign m_axis_data.tvalid = m_axis_data_tvalid_reg;
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assign m_axis_data.tlast = m_axis_data_tlast_reg;
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assign m_axis_data.tid = '0;
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assign m_axis_data.tdest = '0;
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assign m_axis_data.tuser = '0;
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assign scl_o = scl_o_reg;
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assign scl_t = scl_o_reg;
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assign sda_o = sda_o_reg;
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assign sda_t = sda_o_reg;
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assign busy = busy_reg;
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assign bus_active = bus_active_reg;
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assign bus_control = bus_control_reg;
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assign missed_ack = missed_ack_reg;
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wire scl_posedge = scl_i_reg && !last_scl_i_reg;
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wire scl_negedge = !scl_i_reg && last_scl_i_reg;
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wire sda_posedge = sda_i_reg && !last_sda_i_reg;
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wire sda_negedge = !sda_i_reg && last_sda_i_reg;
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wire start_bit = sda_negedge && scl_i_reg;
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wire stop_bit = sda_posedge && scl_i_reg;
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always_comb begin
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state_next = STATE_IDLE;
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phy_start_bit = 1'b0;
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phy_stop_bit = 1'b0;
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phy_write_bit = 1'b0;
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phy_read_bit = 1'b0;
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phy_tx_data = 1'b0;
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phy_release_bus = 1'b0;
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addr_next = addr_reg;
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data_next = data_reg;
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last_next = last_reg;
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mode_read_next = mode_read_reg;
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mode_write_multiple_next = mode_write_multiple_reg;
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mode_stop_next = mode_stop_reg;
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bit_count_next = bit_count_reg;
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s_axis_cmd_ready_next = 1'b0;
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s_axis_data_tready_next = 1'b0;
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m_axis_data_tdata_next = m_axis_data_tdata_reg;
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m_axis_data_tvalid_next = m_axis_data_tvalid_reg && !m_axis_data.tready;
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m_axis_data_tlast_next = m_axis_data_tlast_reg;
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missed_ack_next = 1'b0;
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// generate delays
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if (phy_state_reg != PHY_STATE_IDLE && phy_state_reg != PHY_STATE_ACTIVE) begin
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// wait for phy operation
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state_next = state_reg;
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end else begin
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// process states
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case (state_reg)
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STATE_IDLE: begin
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// line idle
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s_axis_cmd_ready_next = 1'b1;
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if (s_axis_cmd.tready && s_axis_cmd.tvalid) begin
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// command valid
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if (s_axis_cmd_read ^ (s_axis_cmd_write || s_axis_cmd_write_multi)) begin
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// read or write command
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addr_next = s_axis_cmd_address;
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mode_read_next = s_axis_cmd_read;
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mode_write_multiple_next = s_axis_cmd_write_multi;
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mode_stop_next = s_axis_cmd_stop;
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s_axis_cmd_ready_next = 1'b0;
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// start bit
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if (bus_active) begin
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state_next = STATE_START_WAIT;
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end else begin
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phy_start_bit = 1'b1;
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bit_count_next = 4'd8;
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state_next = STATE_ADDRESS_1;
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end
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end else begin
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// invalid or unspecified - ignore
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state_next = STATE_IDLE;
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end
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_ACTIVE_WRITE: begin
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// line active with current address and read/write mode
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s_axis_cmd_ready_next = 1'b1;
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if (s_axis_cmd.tready && s_axis_cmd.tvalid) begin
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// command valid
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if (s_axis_cmd_read ^ (s_axis_cmd_write || s_axis_cmd_write_multi)) begin
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// read or write command
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addr_next = s_axis_cmd_address;
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mode_read_next = s_axis_cmd_read;
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mode_write_multiple_next = s_axis_cmd_write_multi;
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mode_stop_next = s_axis_cmd_stop;
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s_axis_cmd_ready_next = 1'b0;
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if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_read) begin
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// address or mode mismatch or forced start - repeated start
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// repeated start bit
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phy_start_bit = 1'b1;
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bit_count_next = 4'd8;
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state_next = STATE_ADDRESS_1;
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end else begin
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// address and mode match
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// start write
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s_axis_data_tready_next = 1'b1;
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state_next = STATE_WRITE_1;
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end
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end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multi)) begin
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// stop command
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phy_stop_bit = 1'b1;
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state_next = STATE_IDLE;
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end else begin
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// invalid or unspecified - ignore
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state_next = STATE_ACTIVE_WRITE;
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end
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end else begin
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if (stop_on_idle && s_axis_cmd.tready && !s_axis_cmd.tvalid) begin
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// no waiting command and stop_on_idle selected, issue stop condition
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phy_stop_bit = 1'b1;
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_ACTIVE_WRITE;
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end
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end
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end
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STATE_ACTIVE_READ: begin
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// line active to current address
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s_axis_cmd_ready_next = !m_axis_data.tvalid;
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if (s_axis_cmd.tready && s_axis_cmd.tvalid) begin
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// command valid
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if (s_axis_cmd_read ^ (s_axis_cmd_write || s_axis_cmd_write_multi)) begin
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// read or write command
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addr_next = s_axis_cmd_address;
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mode_read_next = s_axis_cmd_read;
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mode_write_multiple_next = s_axis_cmd_write_multi;
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mode_stop_next = s_axis_cmd_stop;
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s_axis_cmd_ready_next = 1'b0;
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if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_write) begin
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// address or mode mismatch or forced start - repeated start
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// write nack for previous read
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phy_write_bit = 1'b1;
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phy_tx_data = 1'b1;
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// repeated start bit
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state_next = STATE_START;
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end else begin
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// address and mode match
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// write ack for previous read
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phy_write_bit = 1'b1;
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phy_tx_data = 1'b0;
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// start next read
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bit_count_next = 4'd8;
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data_next = 8'd0;
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state_next = STATE_READ;
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end
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end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multi)) begin
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// stop command
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// write nack for previous read
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phy_write_bit = 1'b1;
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phy_tx_data = 1'b1;
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// send stop bit
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state_next = STATE_STOP;
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end else begin
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// invalid or unspecified - ignore
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state_next = STATE_ACTIVE_READ;
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end
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end else begin
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if (stop_on_idle && s_axis_cmd.tready && !s_axis_cmd.tvalid) begin
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// no waiting command and stop_on_idle selected, issue stop condition
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// write ack for previous read
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phy_write_bit = 1'b1;
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phy_tx_data = 1'b1;
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// send stop bit
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state_next = STATE_STOP;
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end else begin
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state_next = STATE_ACTIVE_READ;
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end
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end
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end
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STATE_START_WAIT: begin
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// wait for bus idle
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if (bus_active) begin
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state_next = STATE_START_WAIT;
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end else begin
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// bus is idle, take control
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phy_start_bit = 1'b1;
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bit_count_next = 4'd8;
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state_next = STATE_ADDRESS_1;
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end
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end
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STATE_START: begin
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// send start bit
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phy_start_bit = 1'b1;
|
|
bit_count_next = 4'd8;
|
|
state_next = STATE_ADDRESS_1;
|
|
end
|
|
STATE_ADDRESS_1: begin
|
|
// send address
|
|
bit_count_next = bit_count_reg - 1;
|
|
if (bit_count_reg > 1) begin
|
|
// send address
|
|
phy_write_bit = 1'b1;
|
|
phy_tx_data = addr_reg[bit_count_reg-2];
|
|
state_next = STATE_ADDRESS_1;
|
|
end else if (bit_count_reg != 0) begin
|
|
// send read/write bit
|
|
phy_write_bit = 1'b1;
|
|
phy_tx_data = mode_read_reg;
|
|
state_next = STATE_ADDRESS_1;
|
|
end else begin
|
|
// read ack bit
|
|
phy_read_bit = 1'b1;
|
|
state_next = STATE_ADDRESS_2;
|
|
end
|
|
end
|
|
STATE_ADDRESS_2: begin
|
|
// read ack bit
|
|
missed_ack_next = phy_rx_data_reg;
|
|
|
|
if (mode_read_reg) begin
|
|
// start read
|
|
bit_count_next = 4'd8;
|
|
state_next = STATE_READ;
|
|
end else begin
|
|
// start write
|
|
s_axis_data_tready_next = 1'b1;
|
|
state_next = STATE_WRITE_1;
|
|
end
|
|
end
|
|
STATE_WRITE_1: begin
|
|
s_axis_data_tready_next = 1'b1;
|
|
|
|
if (s_axis_data.tready && s_axis_data.tvalid) begin
|
|
// got data, start write
|
|
data_next = s_axis_data.tdata;
|
|
last_next = s_axis_data.tlast;
|
|
bit_count_next = 4'd8;
|
|
s_axis_data_tready_next = 1'b0;
|
|
state_next = STATE_WRITE_2;
|
|
end else begin
|
|
// wait for data
|
|
state_next = STATE_WRITE_1;
|
|
end
|
|
end
|
|
STATE_WRITE_2: begin
|
|
// send data
|
|
bit_count_next = bit_count_reg - 1;
|
|
if (bit_count_reg != 0) begin
|
|
// write data bit
|
|
phy_write_bit = 1'b1;
|
|
phy_tx_data = data_reg[bit_count_reg-1];
|
|
state_next = STATE_WRITE_2;
|
|
end else begin
|
|
// read ack bit
|
|
phy_read_bit = 1'b1;
|
|
state_next = STATE_WRITE_3;
|
|
end
|
|
end
|
|
STATE_WRITE_3: begin
|
|
// read ack bit
|
|
missed_ack_next = phy_rx_data_reg;
|
|
|
|
if (mode_write_multiple_reg && !last_reg) begin
|
|
// more to write
|
|
state_next = STATE_WRITE_1;
|
|
end else if (mode_stop_reg) begin
|
|
// last cycle and stop selected
|
|
phy_stop_bit = 1'b1;
|
|
state_next = STATE_IDLE;
|
|
end else begin
|
|
// otherwise, return to bus active state
|
|
state_next = STATE_ACTIVE_WRITE;
|
|
end
|
|
end
|
|
STATE_READ: begin
|
|
// read data
|
|
|
|
bit_count_next = bit_count_reg - 1;
|
|
data_next = {data_reg[6:0], phy_rx_data_reg};
|
|
if (bit_count_reg != 0) begin
|
|
// read next bit
|
|
phy_read_bit = 1'b1;
|
|
state_next = STATE_READ;
|
|
end else begin
|
|
// output data word
|
|
m_axis_data_tdata_next = data_next;
|
|
m_axis_data_tvalid_next = 1'b1;
|
|
m_axis_data_tlast_next = 1'b0;
|
|
if (mode_stop_reg) begin
|
|
// send nack and stop
|
|
m_axis_data_tlast_next = 1'b1;
|
|
phy_write_bit = 1'b1;
|
|
phy_tx_data = 1'b1;
|
|
state_next = STATE_STOP;
|
|
end else begin
|
|
// return to bus active state
|
|
state_next = STATE_ACTIVE_READ;
|
|
end
|
|
end
|
|
end
|
|
STATE_STOP: begin
|
|
// send stop bit
|
|
phy_stop_bit = 1'b1;
|
|
state_next = STATE_IDLE;
|
|
end
|
|
default: begin
|
|
state_next = STATE_IDLE;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
always_comb begin
|
|
phy_state_next = PHY_STATE_IDLE;
|
|
|
|
phy_rx_data_next = phy_rx_data_reg;
|
|
|
|
delay_next = delay_reg;
|
|
delay_scl_next = delay_scl_reg;
|
|
delay_sda_next = delay_sda_reg;
|
|
|
|
scl_o_next = scl_o_reg;
|
|
sda_o_next = sda_o_reg;
|
|
|
|
bus_control_next = bus_control_reg;
|
|
|
|
if (phy_release_bus) begin
|
|
// release bus and return to idle state
|
|
sda_o_next = 1'b1;
|
|
scl_o_next = 1'b1;
|
|
delay_scl_next = 1'b0;
|
|
delay_sda_next = 1'b0;
|
|
delay_next = '0;
|
|
phy_state_next = PHY_STATE_IDLE;
|
|
end else if (delay_scl_reg) begin
|
|
// wait for SCL to match command
|
|
delay_scl_next = scl_o_reg && !scl_i_reg;
|
|
phy_state_next = phy_state_reg;
|
|
end else if (delay_sda_reg) begin
|
|
// wait for SDA to match command
|
|
delay_sda_next = sda_o_reg && !sda_i_reg;
|
|
phy_state_next = phy_state_reg;
|
|
end else if (delay_reg != 0) begin
|
|
// time delay
|
|
delay_next = delay_reg - 1;
|
|
phy_state_next = phy_state_reg;
|
|
end else begin
|
|
case (phy_state_reg)
|
|
PHY_STATE_IDLE: begin
|
|
// bus idle - wait for start command
|
|
sda_o_next = 1'b1;
|
|
scl_o_next = 1'b1;
|
|
if (phy_start_bit) begin
|
|
sda_o_next = 1'b0;
|
|
delay_next = 17'(prescale);
|
|
phy_state_next = PHY_STATE_START_1;
|
|
end else begin
|
|
phy_state_next = PHY_STATE_IDLE;
|
|
end
|
|
end
|
|
PHY_STATE_ACTIVE: begin
|
|
// bus active
|
|
if (phy_start_bit) begin
|
|
sda_o_next = 1'b1;
|
|
delay_next = 17'(prescale);
|
|
phy_state_next = PHY_STATE_REPEATED_START_1;
|
|
end else if (phy_write_bit) begin
|
|
sda_o_next = phy_tx_data;
|
|
delay_next = 17'(prescale);
|
|
phy_state_next = PHY_STATE_WRITE_BIT_1;
|
|
end else if (phy_read_bit) begin
|
|
sda_o_next = 1'b1;
|
|
delay_next = 17'(prescale);
|
|
phy_state_next = PHY_STATE_READ_BIT_1;
|
|
end else if (phy_stop_bit) begin
|
|
sda_o_next = 1'b0;
|
|
delay_next = 17'(prescale);
|
|
phy_state_next = PHY_STATE_STOP_1;
|
|
end else begin
|
|
phy_state_next = PHY_STATE_ACTIVE;
|
|
end
|
|
end
|
|
PHY_STATE_REPEATED_START_1: begin
|
|
// generate repeated start bit
|
|
// ______
|
|
// sda XXX/ \_______
|
|
// _______
|
|
// scl ______/ \___
|
|
//
|
|
|
|
scl_o_next = 1'b1;
|
|
delay_scl_next = 1'b1;
|
|
delay_next = 17'(prescale);
|
|
phy_state_next = PHY_STATE_REPEATED_START_2;
|
|
end
|
|
PHY_STATE_REPEATED_START_2: begin
|
|
// generate repeated start bit
|
|
// ______
|
|
// sda XXX/ \_______
|
|
// _______
|
|
// scl ______/ \___
|
|
//
|
|
|
|
sda_o_next = 1'b0;
|
|
delay_next = 17'(prescale);
|
|
phy_state_next = PHY_STATE_START_1;
|
|
end
|
|
PHY_STATE_START_1: begin
|
|
// generate start bit
|
|
// ___
|
|
// sda \_______
|
|
// _______
|
|
// scl \___
|
|
//
|
|
|
|
scl_o_next = 1'b0;
|
|
delay_next = 17'(prescale);
|
|
phy_state_next = PHY_STATE_START_2;
|
|
end
|
|
PHY_STATE_START_2: begin
|
|
// generate start bit
|
|
// ___
|
|
// sda \_______
|
|
// _______
|
|
// scl \___
|
|
//
|
|
|
|
bus_control_next = 1'b1;
|
|
phy_state_next = PHY_STATE_ACTIVE;
|
|
end
|
|
PHY_STATE_WRITE_BIT_1: begin
|
|
// write bit
|
|
// ________
|
|
// sda X________X
|
|
// ____
|
|
// scl __/ \__
|
|
|
|
scl_o_next = 1'b1;
|
|
delay_scl_next = 1'b1;
|
|
delay_next = 17'(prescale);
|
|
phy_state_next = PHY_STATE_WRITE_BIT_2;
|
|
end
|
|
PHY_STATE_WRITE_BIT_2: begin
|
|
// write bit
|
|
// ________
|
|
// sda X________X
|
|
// ____
|
|
// scl __/ \__
|
|
|
|
scl_o_next = 1'b0;
|
|
delay_next = 17'(prescale);
|
|
phy_state_next = PHY_STATE_WRITE_BIT_3;
|
|
end
|
|
PHY_STATE_WRITE_BIT_3: begin
|
|
// write bit
|
|
// ________
|
|
// sda X________X
|
|
// ____
|
|
// scl __/ \__
|
|
|
|
phy_state_next = PHY_STATE_ACTIVE;
|
|
end
|
|
PHY_STATE_READ_BIT_1: begin
|
|
// read bit
|
|
// ________
|
|
// sda X________X
|
|
// ____
|
|
// scl __/ \__
|
|
|
|
scl_o_next = 1'b1;
|
|
delay_scl_next = 1'b1;
|
|
delay_next = 17'(prescale);
|
|
phy_state_next = PHY_STATE_READ_BIT_2;
|
|
end
|
|
PHY_STATE_READ_BIT_2: begin
|
|
// read bit
|
|
// ________
|
|
// sda X________X
|
|
// ____
|
|
// scl __/ \__
|
|
|
|
phy_rx_data_next = sda_i_reg;
|
|
delay_next = 17'(prescale);
|
|
phy_state_next = PHY_STATE_READ_BIT_3;
|
|
end
|
|
PHY_STATE_READ_BIT_3: begin
|
|
// read bit
|
|
// ________
|
|
// sda X________X
|
|
// ____
|
|
// scl __/ \__
|
|
|
|
scl_o_next = 1'b0;
|
|
delay_next = 17'(prescale);
|
|
phy_state_next = PHY_STATE_READ_BIT_4;
|
|
end
|
|
PHY_STATE_READ_BIT_4: begin
|
|
// read bit
|
|
// ________
|
|
// sda X________X
|
|
// ____
|
|
// scl __/ \__
|
|
|
|
phy_state_next = PHY_STATE_ACTIVE;
|
|
end
|
|
PHY_STATE_STOP_1: begin
|
|
// stop bit
|
|
// ___
|
|
// sda XXX\_______/
|
|
// _______
|
|
// scl _______/
|
|
|
|
scl_o_next = 1'b1;
|
|
delay_scl_next = 1'b1;
|
|
delay_next = 17'(prescale);
|
|
phy_state_next = PHY_STATE_STOP_2;
|
|
end
|
|
PHY_STATE_STOP_2: begin
|
|
// stop bit
|
|
// ___
|
|
// sda XXX\_______/
|
|
// _______
|
|
// scl _______/
|
|
|
|
sda_o_next = 1'b1;
|
|
delay_next = 17'(prescale);
|
|
phy_state_next = PHY_STATE_STOP_3;
|
|
end
|
|
PHY_STATE_STOP_3: begin
|
|
// stop bit
|
|
// ___
|
|
// sda XXX\_______/
|
|
// _______
|
|
// scl _______/
|
|
|
|
bus_control_next = 1'b0;
|
|
phy_state_next = PHY_STATE_IDLE;
|
|
end
|
|
default: begin
|
|
phy_state_next = PHY_STATE_IDLE;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
always_ff @(posedge clk) begin
|
|
state_reg <= state_next;
|
|
phy_state_reg <= phy_state_next;
|
|
|
|
phy_rx_data_reg <= phy_rx_data_next;
|
|
|
|
addr_reg <= addr_next;
|
|
data_reg <= data_next;
|
|
last_reg <= last_next;
|
|
|
|
mode_read_reg <= mode_read_next;
|
|
mode_write_multiple_reg <= mode_write_multiple_next;
|
|
mode_stop_reg <= mode_stop_next;
|
|
|
|
delay_reg <= delay_next;
|
|
delay_scl_reg <= delay_scl_next;
|
|
delay_sda_reg <= delay_sda_next;
|
|
|
|
bit_count_reg <= bit_count_next;
|
|
|
|
s_axis_cmd_ready_reg <= s_axis_cmd_ready_next;
|
|
|
|
s_axis_data_tready_reg <= s_axis_data_tready_next;
|
|
|
|
m_axis_data_tdata_reg <= m_axis_data_tdata_next;
|
|
m_axis_data_tlast_reg <= m_axis_data_tlast_next;
|
|
m_axis_data_tvalid_reg <= m_axis_data_tvalid_next;
|
|
|
|
scl_i_reg <= scl_i;
|
|
sda_i_reg <= sda_i;
|
|
|
|
scl_o_reg <= scl_o_next;
|
|
sda_o_reg <= sda_o_next;
|
|
|
|
last_scl_i_reg <= scl_i_reg;
|
|
last_sda_i_reg <= sda_i_reg;
|
|
|
|
busy_reg <= !(state_reg == STATE_IDLE || state_reg == STATE_ACTIVE_WRITE || state_reg == STATE_ACTIVE_READ) || !(phy_state_reg == PHY_STATE_IDLE || phy_state_reg == PHY_STATE_ACTIVE);
|
|
|
|
if (start_bit) begin
|
|
bus_active_reg <= 1'b1;
|
|
end else if (stop_bit) begin
|
|
bus_active_reg <= 1'b0;
|
|
end else begin
|
|
bus_active_reg <= bus_active_reg;
|
|
end
|
|
|
|
bus_control_reg <= bus_control_next;
|
|
missed_ack_reg <= missed_ack_next;
|
|
|
|
if (rst) begin
|
|
state_reg <= STATE_IDLE;
|
|
phy_state_reg <= PHY_STATE_IDLE;
|
|
delay_reg <= '0;
|
|
delay_scl_reg <= 1'b0;
|
|
delay_sda_reg <= 1'b0;
|
|
s_axis_cmd_ready_reg <= 1'b0;
|
|
s_axis_data_tready_reg <= 1'b0;
|
|
m_axis_data_tvalid_reg <= 1'b0;
|
|
scl_o_reg <= 1'b1;
|
|
sda_o_reg <= 1'b1;
|
|
busy_reg <= 1'b0;
|
|
bus_active_reg <= 1'b0;
|
|
bus_control_reg <= 1'b0;
|
|
missed_ack_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|