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https://github.com/fpganinja/taxi.git
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140 lines
3.1 KiB
Systemverilog
140 lines
3.1 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream UART (RX)
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*/
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module taxi_uart_rx
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4-Stream output (source)
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*/
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taxi_axis_if.src m_axis_rx,
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/*
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* UART interface
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*/
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input wire logic rxd,
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/*
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* Status
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*/
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output wire logic busy,
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output wire logic overrun_error,
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output wire logic frame_error,
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/*
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* Baud rate pulse in
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*/
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input wire logic baud_clk
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);
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localparam DATA_W = m_axis_rx.DATA_W;
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logic [DATA_W-1:0] m_axis_tdata_reg = 0;
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logic m_axis_tvalid_reg = 1'b0;
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logic rxd_reg = 1'b1;
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logic overrun_error_reg = 1'b0;
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logic frame_error_reg = 1'b0;
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logic [DATA_W-1:0] data_reg = 0;
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logic [2:0] baud_cnt_reg = 0;
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logic run_reg = 1'b0;
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logic start_reg = 1'b0;
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logic stop_reg = 1'b0;
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assign m_axis_rx.tdata = m_axis_tdata_reg;
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assign m_axis_rx.tkeep = 1'b1;
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assign m_axis_rx.tstrb = m_axis_rx.tkeep;
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assign m_axis_rx.tvalid = m_axis_tvalid_reg;
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assign m_axis_rx.tlast = 1'b1;
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assign m_axis_rx.tid = '0;
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assign m_axis_rx.tdest = '0;
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assign m_axis_rx.tuser = '0;
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assign busy = run_reg;
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assign overrun_error = overrun_error_reg;
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assign frame_error = frame_error_reg;
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always_ff @(posedge clk) begin
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rxd_reg <= rxd;
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overrun_error_reg <= 1'b0;
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frame_error_reg <= 1'b0;
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if (m_axis_rx.tvalid && m_axis_rx.tready) begin
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m_axis_tvalid_reg <= 1'b0;
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end
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if (!baud_clk) begin
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// wait
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end else if (baud_cnt_reg != 0) begin
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baud_cnt_reg <= baud_cnt_reg - 1;
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end else if (run_reg) begin
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start_reg <= 1'b0;
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if (start_reg) begin
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// wait bit period for start bit
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baud_cnt_reg <= '1;
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if (rxd_reg) begin
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// start bit high, clear run bit
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run_reg <= 1'b0;
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frame_error_reg <= 1'b1;
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end
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end else begin
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{data_reg, stop_reg} <= {rxd_reg, data_reg};
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if (stop_reg) begin
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run_reg <= 1'b0;
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if (rxd_reg) begin
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// stop bit high, transfer data
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m_axis_tdata_reg <= data_reg;
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m_axis_tvalid_reg <= 1'b1;
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overrun_error_reg <= m_axis_tvalid_reg;
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end else begin
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// stop bit low
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frame_error_reg <= 1'b1;
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end
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end else begin
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baud_cnt_reg <= '1;
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end
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end
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end else begin
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data_reg <= {1'b1, {DATA_W-1{1'b0}}}; // marker bit
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start_reg <= 1'b1;
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stop_reg <= 1'b0;
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if (!rxd_reg) begin
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// falling edge of start bit
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// wait half bit period
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baud_cnt_reg <= 3'b011;
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run_reg <= 1'b1;
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end
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end
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if (rst) begin
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m_axis_tvalid_reg <= 1'b0;
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rxd_reg <= 1'b1;
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run_reg <= 1'b0;
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overrun_error_reg <= 1'b0;
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frame_error_reg <= 1'b0;
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end
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end
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endmodule
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`resetall
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