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120 lines
2.8 KiB
Systemverilog
120 lines
2.8 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2018-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream pipeline register
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*/
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module taxi_axis_pipeline_register #
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(
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// Register type
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter REG_TYPE = 2,
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// Number of registers in pipeline
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parameter LENGTH = 2
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4-Stream input (sink)
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*/
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taxi_axis_if.snk s_axis,
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/*
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* AXI4-Stream output (source)
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*/
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taxi_axis_if.src m_axis
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);
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// extract parameters
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localparam DATA_W = s_axis.DATA_W;
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localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis.KEEP_EN;
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localparam KEEP_W = s_axis.KEEP_W;
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localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN;
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localparam logic LAST_EN = s_axis.LAST_EN && m_axis.LAST_EN;
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localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN;
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localparam ID_W = s_axis.ID_W;
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localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN;
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localparam DEST_W = s_axis.DEST_W;
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localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN;
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localparam USER_W = s_axis.USER_W;
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// check configuration
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if (m_axis.DATA_W != DATA_W)
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$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
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if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
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$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
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taxi_axis_if #(
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.DATA_W(DATA_W),
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.KEEP_EN(KEEP_EN),
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.KEEP_W(KEEP_W),
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.STRB_EN(STRB_EN),
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.LAST_EN(LAST_EN),
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.ID_EN(ID_EN),
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.ID_W(ID_W),
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.DEST_EN(DEST_EN),
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.DEST_W(DEST_W),
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.USER_EN(USER_EN),
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.USER_W(USER_W)
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) axis_pipe[LENGTH+1]();
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assign axis_pipe[0].tdata = s_axis.tdata;
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assign axis_pipe[0].tkeep = s_axis.tkeep;
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assign axis_pipe[0].tstrb = s_axis.tstrb;
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assign axis_pipe[0].tvalid = s_axis.tvalid;
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assign s_axis.tready = axis_pipe[0].tready;
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assign axis_pipe[0].tlast = s_axis.tlast;
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assign axis_pipe[0].tid = s_axis.tid;
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assign axis_pipe[0].tdest = s_axis.tdest;
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assign axis_pipe[0].tuser = s_axis.tuser;
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assign m_axis.tdata = axis_pipe[LENGTH].tdata;
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assign m_axis.tkeep = axis_pipe[LENGTH].tkeep;
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assign m_axis.tstrb = axis_pipe[LENGTH].tstrb;
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assign m_axis.tvalid = axis_pipe[LENGTH].tvalid;
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assign axis_pipe[LENGTH].tready = m_axis.tready;
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assign m_axis.tlast = axis_pipe[LENGTH].tlast;
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assign m_axis.tid = axis_pipe[LENGTH].tid;
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assign m_axis.tdest = axis_pipe[LENGTH].tdest;
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assign m_axis.tuser = axis_pipe[LENGTH].tuser;
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for (genvar i = 0; i < LENGTH; i = i + 1) begin : pipe_reg
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taxi_axis_register #(
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.REG_TYPE(REG_TYPE)
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)
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reg_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4-Stream input (sink)
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*/
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.s_axis(axis_pipe[i]),
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/*
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* AXI4-Stream output (source)
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*/
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.m_axis(axis_pipe[i+1])
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);
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end
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endmodule
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`resetall
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