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100 lines
2.5 KiB
Systemverilog
100 lines
2.5 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2026 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* True dual-port RAM
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*/
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module taxi_ram_2rw_1c #
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(
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parameter ADDR_W = 16,
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parameter DATA_W = 16,
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parameter logic STRB_EN = 1'b1,
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parameter STRB_W = DATA_W/8
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)
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(
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input wire logic clk,
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input wire logic a_en,
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input wire logic [ADDR_W-1:0] a_addr,
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input wire logic a_wr_en,
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input wire logic [DATA_W-1:0] a_wr_data,
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input wire logic [STRB_W-1:0] a_wr_strb = '1,
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output wire logic [DATA_W-1:0] a_rd_data,
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input wire logic b_en,
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input wire logic [ADDR_W-1:0] b_addr,
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input wire logic b_wr_en,
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input wire logic [DATA_W-1:0] b_wr_data,
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input wire logic [STRB_W-1:0] b_wr_strb = '1,
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output wire logic [DATA_W-1:0] b_rd_data
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);
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localparam BYTE_LANES = STRB_W;
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localparam BYTE_W = DATA_W/BYTE_LANES;
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// check configuration
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if (STRB_EN && BYTE_W * STRB_W != DATA_W)
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$fatal(0, "Error: Data width not evenly divisible (instance %m)");
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reg [DATA_W-1:0] a_rd_data_reg = '0;
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reg [DATA_W-1:0] b_rd_data_reg = '0;
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assign a_rd_data = a_rd_data_reg;
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assign b_rd_data = b_rd_data_reg;
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// verilator lint_off MULTIDRIVEN
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// (* RAM_STYLE="BLOCK" *)
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logic [DATA_W-1:0] mem[2**ADDR_W] = '{default: '0};
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// verilator lint_on MULTIDRIVEN
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always_ff @(posedge clk) begin
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if (a_en) begin
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if (a_wr_en) begin
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if (STRB_EN) begin
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for (integer i = 0; i < BYTE_LANES; i = i + 1) begin
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if (a_wr_strb[i]) begin
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mem[a_addr][BYTE_W*i +: BYTE_W] <= a_wr_data[BYTE_W*i +: BYTE_W];
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end
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end
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end else begin
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mem[a_addr] <= a_wr_data;
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end
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end else begin
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a_rd_data_reg <= mem[a_addr];
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end
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end
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end
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always_ff @(posedge clk) begin
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if (b_en) begin
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if (b_wr_en) begin
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if (STRB_EN) begin
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for (integer i = 0; i < BYTE_LANES; i = i + 1) begin
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if (b_wr_strb[i]) begin
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mem[b_addr][BYTE_W*i +: BYTE_W] <= b_wr_data[BYTE_W*i +: BYTE_W];
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end
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end
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end else begin
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mem[b_addr] <= b_wr_data;
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end
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end else begin
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b_rd_data_reg <= mem[b_addr];
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end
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end
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end
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endmodule
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`resetall
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