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https://github.com/fpganinja/taxi.git
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799 lines
26 KiB
Systemverilog
799 lines
26 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2015-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream XGMII frame transmitter (AXI in, XGMII out)
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*/
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module taxi_axis_xgmii_tx_64 #
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(
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parameter DATA_W = 64,
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parameter CTRL_W = (DATA_W/8),
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parameter logic PADDING_EN = 1'b1,
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parameter logic DIC_EN = 1'b1,
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parameter MIN_FRAME_LEN = 64,
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parameter logic PTP_TS_EN = 1'b0,
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parameter logic PTP_TS_FMT_TOD = 1'b1,
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parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
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parameter logic TX_CPL_CTRL_IN_TUSER = 1'b1
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* Transmit interface (AXI stream)
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*/
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taxi_axis_if.snk s_axis_tx,
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taxi_axis_if.src m_axis_tx_cpl,
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/*
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* XGMII output
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*/
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output wire logic [DATA_W-1:0] xgmii_txd,
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output wire logic [CTRL_W-1:0] xgmii_txc,
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/*
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* PTP
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*/
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input wire logic [PTP_TS_W-1:0] ptp_ts,
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/*
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* Configuration
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*/
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input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
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input wire logic [7:0] cfg_tx_ifg = 8'd12,
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input wire logic cfg_tx_enable,
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/*
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* Status
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*/
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output wire logic [1:0] tx_start_packet,
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output wire logic [3:0] stat_tx_byte,
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output wire logic [15:0] stat_tx_pkt_len,
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output wire logic stat_tx_pkt_ucast,
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output wire logic stat_tx_pkt_mcast,
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output wire logic stat_tx_pkt_bcast,
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output wire logic stat_tx_pkt_vlan,
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output wire logic stat_tx_pkt_good,
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output wire logic stat_tx_pkt_bad,
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output wire logic stat_tx_err_oversize,
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output wire logic stat_tx_err_user,
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output wire logic stat_tx_err_underflow
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);
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// extract parameters
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localparam KEEP_W = DATA_W/8;
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localparam USER_W = TX_CPL_CTRL_IN_TUSER ? 2 : 1;
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localparam TX_TAG_W = s_axis_tx.ID_W;
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localparam EMPTY_W = $clog2(KEEP_W);
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localparam MIN_LEN_W = $clog2(MIN_FRAME_LEN-4-CTRL_W+1);
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// check configuration
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if (DATA_W != 64)
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$fatal(0, "Error: Interface width must be 64 (instance %m)");
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if (KEEP_W*8 != DATA_W || CTRL_W*8 != DATA_W)
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$fatal(0, "Error: Interface requires byte (8-bit) granularity (instance %m)");
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if (s_axis_tx.DATA_W != DATA_W)
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$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
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if (s_axis_tx.USER_W != USER_W)
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$fatal(0, "Error: Interface USER_W parameter mismatch (instance %m)");
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localparam [7:0]
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ETH_PRE = 8'h55,
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ETH_SFD = 8'hD5;
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localparam [7:0]
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XGMII_IDLE = 8'h07,
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XGMII_START = 8'hfb,
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XGMII_TERM = 8'hfd,
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XGMII_ERROR = 8'hfe;
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localparam [2:0]
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STATE_IDLE = 3'd0,
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STATE_PAYLOAD = 3'd1,
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STATE_PAD = 3'd2,
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STATE_FCS_1 = 3'd3,
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STATE_FCS_2 = 3'd4,
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STATE_ERR = 3'd5,
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STATE_IFG = 3'd6;
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logic [2:0] state_reg = STATE_IDLE, state_next;
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// datapath control signals
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logic reset_crc;
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logic update_crc;
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logic swap_lanes_reg = 1'b0, swap_lanes_next;
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logic [31:0] swap_txd = 32'd0;
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logic [3:0] swap_txc = 4'd0;
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logic [DATA_W-1:0] s_tdata_reg = '0, s_tdata_next;
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logic [EMPTY_W-1:0] s_empty_reg = '0, s_empty_next;
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logic [DATA_W-1:0] fcs_output_txd_0;
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logic [DATA_W-1:0] fcs_output_txd_1;
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logic [CTRL_W-1:0] fcs_output_txc_0;
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logic [CTRL_W-1:0] fcs_output_txc_1;
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logic [7:0] ifg_offset;
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logic frame_start_reg = 1'b0, frame_start_next;
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logic frame_reg = 1'b0, frame_next;
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logic frame_error_reg = 1'b0, frame_error_next;
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logic frame_oversize_reg = 1'b0, frame_oversize_next;
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logic [MIN_LEN_W-1:0] frame_min_count_reg = '0, frame_min_count_next;
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logic [0:0] hdr_ptr_reg = '0, hdr_ptr_next;
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logic is_mcast_reg = 1'b0, is_mcast_next;
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logic is_bcast_reg = 1'b0, is_bcast_next;
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logic is_8021q_reg = 1'b0, is_8021q_next;
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logic [15:0] frame_len_reg = '0, frame_len_next;
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logic [15:0] frame_len_lim_reg = '0, frame_len_lim_next;
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logic [7:0] ifg_cnt_reg = '0, ifg_cnt_next;
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logic [7:0] ifg_count_reg = 8'd0, ifg_count_next;
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logic [1:0] deficit_idle_count_reg = 2'd0, deficit_idle_count_next;
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logic s_axis_tx_tready_reg = 1'b0, s_axis_tx_tready_next;
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logic [PTP_TS_W-1:0] m_axis_tx_cpl_ts_reg = '0;
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logic [PTP_TS_W-1:0] m_axis_tx_cpl_ts_adj_reg = '0;
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logic [TX_TAG_W-1:0] m_axis_tx_cpl_tag_reg = '0;
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logic m_axis_tx_cpl_valid_reg = 1'b0;
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logic m_axis_tx_cpl_valid_int_reg = 1'b0;
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logic m_axis_tx_cpl_ts_borrow_reg = 1'b0;
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logic [31:0] crc_state_reg[7:0];
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wire [31:0] crc_state_next[7:0];
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logic [4+16-1:0] last_ts_reg = '0;
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logic [4+16-1:0] ts_inc_reg = '0;
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logic [DATA_W-1:0] xgmii_txd_reg = {CTRL_W{XGMII_IDLE}}, xgmii_txd_next;
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logic [CTRL_W-1:0] xgmii_txc_reg = {CTRL_W{1'b1}}, xgmii_txc_next;
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logic [1:0] start_packet_reg = 2'b00;
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logic [3:0] stat_tx_byte_reg = '0, stat_tx_byte_next;
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logic [15:0] stat_tx_pkt_len_reg = '0, stat_tx_pkt_len_next;
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logic stat_tx_pkt_ucast_reg = 1'b0, stat_tx_pkt_ucast_next;
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logic stat_tx_pkt_mcast_reg = 1'b0, stat_tx_pkt_mcast_next;
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logic stat_tx_pkt_bcast_reg = 1'b0, stat_tx_pkt_bcast_next;
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logic stat_tx_pkt_vlan_reg = 1'b0, stat_tx_pkt_vlan_next;
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logic stat_tx_pkt_good_reg = 1'b0, stat_tx_pkt_good_next;
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logic stat_tx_pkt_bad_reg = 1'b0, stat_tx_pkt_bad_next;
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logic stat_tx_err_oversize_reg = 1'b0, stat_tx_err_oversize_next;
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logic stat_tx_err_user_reg = 1'b0, stat_tx_err_user_next;
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logic stat_tx_err_underflow_reg = 1'b0, stat_tx_err_underflow_next;
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assign s_axis_tx.tready = s_axis_tx_tready_reg;
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assign xgmii_txd = xgmii_txd_reg;
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assign xgmii_txc = xgmii_txc_reg;
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assign m_axis_tx_cpl.tdata = PTP_TS_EN ? ((!PTP_TS_FMT_TOD || m_axis_tx_cpl_ts_borrow_reg) ? m_axis_tx_cpl_ts_reg : m_axis_tx_cpl_ts_adj_reg) : '0;
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assign m_axis_tx_cpl.tkeep = 1'b1;
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assign m_axis_tx_cpl.tstrb = m_axis_tx_cpl.tkeep;
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assign m_axis_tx_cpl.tvalid = m_axis_tx_cpl_valid_reg;
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assign m_axis_tx_cpl.tlast = 1'b1;
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assign m_axis_tx_cpl.tid = m_axis_tx_cpl_tag_reg;
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assign m_axis_tx_cpl.tdest = '0;
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assign m_axis_tx_cpl.tuser = '0;
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assign tx_start_packet = start_packet_reg;
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assign stat_tx_byte = stat_tx_byte_reg;
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assign stat_tx_pkt_len = stat_tx_pkt_len_reg;
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assign stat_tx_pkt_ucast = stat_tx_pkt_ucast_reg;
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assign stat_tx_pkt_mcast = stat_tx_pkt_mcast_reg;
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assign stat_tx_pkt_bcast = stat_tx_pkt_bcast_reg;
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assign stat_tx_pkt_vlan = stat_tx_pkt_vlan_reg;
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assign stat_tx_pkt_good = stat_tx_pkt_good_reg;
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assign stat_tx_pkt_bad = stat_tx_pkt_bad_reg;
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assign stat_tx_err_oversize = stat_tx_err_oversize_reg;
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assign stat_tx_err_user = stat_tx_err_user_reg;
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assign stat_tx_err_underflow = stat_tx_err_underflow_reg;
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for (genvar n = 0; n < 8; n = n + 1) begin : crc
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taxi_lfsr #(
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.LFSR_W(32),
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.LFSR_POLY(32'h4c11db7),
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.LFSR_GALOIS(1),
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.LFSR_FEED_FORWARD(0),
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.REVERSE(1),
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.DATA_W(8*(n+1))
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)
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eth_crc (
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.data_in(s_tdata_reg[0 +: 8*(n+1)]),
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.state_in(crc_state_reg[7]),
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.data_out(),
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.state_out(crc_state_next[n])
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);
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end
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function [2:0] keep2empty(input [7:0] k);
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casez (k)
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8'bzzzzzzz0: keep2empty = 3'd7;
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8'bzzzzzz01: keep2empty = 3'd7;
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8'bzzzzz011: keep2empty = 3'd6;
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8'bzzzz0111: keep2empty = 3'd5;
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8'bzzz01111: keep2empty = 3'd4;
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8'bzz011111: keep2empty = 3'd3;
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8'bz0111111: keep2empty = 3'd2;
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8'b01111111: keep2empty = 3'd1;
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8'b11111111: keep2empty = 3'd0;
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endcase
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endfunction
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// Mask input data
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wire [DATA_W-1:0] s_axis_tx_tdata_masked;
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for (genvar n = 0; n < CTRL_W; n = n + 1) begin
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assign s_axis_tx_tdata_masked[n*8 +: 8] = s_axis_tx.tkeep[n] ? s_axis_tx.tdata[n*8 +: 8] : 8'd0;
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end
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// FCS cycle calculation
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always_comb begin
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casez (s_empty_reg)
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3'd7: begin
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fcs_output_txd_0 = {{2{XGMII_IDLE}}, XGMII_TERM, ~crc_state_next[0][31:0], s_tdata_reg[7:0]};
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fcs_output_txd_1 = {8{XGMII_IDLE}};
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fcs_output_txc_0 = 8'b11100000;
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fcs_output_txc_1 = 8'b11111111;
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ifg_offset = 8'd3;
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end
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3'd6: begin
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fcs_output_txd_0 = {XGMII_IDLE, XGMII_TERM, ~crc_state_next[1][31:0], s_tdata_reg[15:0]};
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fcs_output_txd_1 = {8{XGMII_IDLE}};
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fcs_output_txc_0 = 8'b11000000;
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fcs_output_txc_1 = 8'b11111111;
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ifg_offset = 8'd2;
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end
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3'd5: begin
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fcs_output_txd_0 = {XGMII_TERM, ~crc_state_next[2][31:0], s_tdata_reg[23:0]};
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fcs_output_txd_1 = {8{XGMII_IDLE}};
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fcs_output_txc_0 = 8'b10000000;
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fcs_output_txc_1 = 8'b11111111;
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ifg_offset = 8'd1;
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end
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3'd4: begin
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fcs_output_txd_0 = {~crc_state_next[3][31:0], s_tdata_reg[31:0]};
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fcs_output_txd_1 = {{7{XGMII_IDLE}}, XGMII_TERM};
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fcs_output_txc_0 = 8'b00000000;
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fcs_output_txc_1 = 8'b11111111;
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ifg_offset = 8'd8;
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end
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3'd3: begin
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fcs_output_txd_0 = {~crc_state_next[4][23:0], s_tdata_reg[39:0]};
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fcs_output_txd_1 = {{6{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[4][31:24]};
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fcs_output_txc_0 = 8'b00000000;
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fcs_output_txc_1 = 8'b11111110;
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ifg_offset = 8'd7;
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end
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3'd2: begin
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fcs_output_txd_0 = {~crc_state_next[5][15:0], s_tdata_reg[47:0]};
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fcs_output_txd_1 = {{5{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[5][31:16]};
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fcs_output_txc_0 = 8'b00000000;
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fcs_output_txc_1 = 8'b11111100;
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ifg_offset = 8'd6;
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end
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3'd1: begin
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fcs_output_txd_0 = {~crc_state_next[6][7:0], s_tdata_reg[55:0]};
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fcs_output_txd_1 = {{4{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[6][31:8]};
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fcs_output_txc_0 = 8'b00000000;
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fcs_output_txc_1 = 8'b11111000;
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ifg_offset = 8'd5;
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end
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3'd0: begin
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fcs_output_txd_0 = s_tdata_reg;
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fcs_output_txd_1 = {{3{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[7][31:0]};
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fcs_output_txc_0 = 8'b00000000;
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fcs_output_txc_1 = 8'b11110000;
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ifg_offset = 8'd4;
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end
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endcase
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end
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always_comb begin
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state_next = STATE_IDLE;
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reset_crc = 1'b0;
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update_crc = 1'b0;
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swap_lanes_next = swap_lanes_reg;
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frame_start_next = 1'b0;
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frame_next = frame_reg;
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frame_error_next = frame_error_reg;
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frame_oversize_next = frame_oversize_reg;
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frame_min_count_next = frame_min_count_reg;
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hdr_ptr_next = hdr_ptr_reg;
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is_mcast_next = is_mcast_reg;
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is_bcast_next = is_bcast_reg;
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is_8021q_next = is_8021q_reg;
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frame_len_next = frame_len_reg;
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frame_len_lim_next = frame_len_lim_reg;
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ifg_cnt_next = ifg_cnt_reg;
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ifg_count_next = ifg_count_reg;
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deficit_idle_count_next = deficit_idle_count_reg;
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s_axis_tx_tready_next = 1'b0;
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s_tdata_next = s_tdata_reg;
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s_empty_next = s_empty_reg;
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// XGMII idle
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xgmii_txd_next = {CTRL_W{XGMII_IDLE}};
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xgmii_txc_next = {CTRL_W{1'b1}};
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stat_tx_byte_next = '0;
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stat_tx_pkt_len_next = '0;
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stat_tx_pkt_ucast_next = 1'b0;
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stat_tx_pkt_mcast_next = 1'b0;
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stat_tx_pkt_bcast_next = 1'b0;
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stat_tx_pkt_vlan_next = 1'b0;
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stat_tx_pkt_good_next = 1'b0;
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stat_tx_pkt_bad_next = 1'b0;
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stat_tx_err_oversize_next = 1'b0;
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stat_tx_err_user_next = 1'b0;
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stat_tx_err_underflow_next = 1'b0;
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if (s_axis_tx.tvalid && s_axis_tx.tready) begin
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frame_next = !s_axis_tx.tlast;
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end
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// counter for min frame length enforcement
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if (frame_min_count_reg > MIN_LEN_W'(CTRL_W)) begin
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frame_min_count_next = MIN_LEN_W'(frame_min_count_reg - CTRL_W);
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end else begin
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frame_min_count_next = 0;
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end
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// counter to measure frame length
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if (&frame_len_reg[15:3] == 0) begin
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frame_len_next = frame_len_reg + 16'(CTRL_W);
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end else begin
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frame_len_next = '1;
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end
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// counter for max frame length enforcement
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if (frame_len_lim_reg[15:3] != 0) begin
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frame_len_lim_next = frame_len_lim_reg - 16'(CTRL_W);
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end else begin
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frame_len_lim_next = '0;
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end
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// address and ethertype checks
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if (&hdr_ptr_reg == 0) begin
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hdr_ptr_next = hdr_ptr_reg + 1;
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end
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case (hdr_ptr_reg)
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1'd0: begin
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is_mcast_next = s_tdata_reg[0];
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is_bcast_next = &s_tdata_reg[47:0];
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end
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1'd1: is_8021q_next = {s_tdata_reg[39:32], s_tdata_reg[47:40]} == 16'h8100;
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default: begin
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// do nothing
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end
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endcase
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if (ifg_cnt_reg[7:3] != 0) begin
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ifg_cnt_next = ifg_cnt_reg - 8'(CTRL_W);
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end else begin
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ifg_cnt_next = '0;
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end
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case (state_reg)
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STATE_IDLE: begin
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// idle state - wait for data
|
|
frame_error_next = 1'b0;
|
|
frame_min_count_next = MIN_LEN_W'(MIN_FRAME_LEN-4-CTRL_W);
|
|
hdr_ptr_next = 0;
|
|
frame_len_next = 0;
|
|
frame_len_lim_next = cfg_tx_max_pkt_len;
|
|
reset_crc = 1'b1;
|
|
s_axis_tx_tready_next = cfg_tx_enable;
|
|
|
|
// XGMII idle
|
|
xgmii_txd_next = {CTRL_W{XGMII_IDLE}};
|
|
xgmii_txc_next = {CTRL_W{1'b1}};
|
|
|
|
s_tdata_next = s_axis_tx_tdata_masked;
|
|
s_empty_next = keep2empty(s_axis_tx.tkeep);
|
|
|
|
if (s_axis_tx.tvalid && s_axis_tx.tready) begin
|
|
// XGMII start, preamble, and SFD
|
|
xgmii_txd_next = {ETH_SFD, {6{ETH_PRE}}, XGMII_START};
|
|
xgmii_txc_next = 8'b00000001;
|
|
frame_start_next = 1'b1;
|
|
s_axis_tx_tready_next = 1'b1;
|
|
state_next = STATE_PAYLOAD;
|
|
end else begin
|
|
swap_lanes_next = 1'b0;
|
|
ifg_count_next = 8'd0;
|
|
deficit_idle_count_next = 2'd0;
|
|
state_next = STATE_IDLE;
|
|
end
|
|
end
|
|
STATE_PAYLOAD: begin
|
|
// transfer payload
|
|
update_crc = 1'b1;
|
|
s_axis_tx_tready_next = 1'b1;
|
|
|
|
xgmii_txd_next = s_tdata_reg;
|
|
xgmii_txc_next = {CTRL_W{1'b0}};
|
|
|
|
s_tdata_next = s_axis_tx_tdata_masked;
|
|
s_empty_next = keep2empty(s_axis_tx.tkeep);
|
|
|
|
stat_tx_byte_next = 4'(CTRL_W);
|
|
|
|
if (s_axis_tx.tvalid && s_axis_tx.tlast) begin
|
|
frame_oversize_next = frame_len_lim_reg < 16'(8+8+4-keep2empty(s_axis_tx.tkeep));
|
|
end else begin
|
|
frame_oversize_next = frame_len_lim_reg < 8+8;
|
|
end
|
|
|
|
if (!s_axis_tx.tvalid || s_axis_tx.tlast || frame_oversize_next) begin
|
|
s_axis_tx_tready_next = frame_next; // drop frame
|
|
frame_error_next = !s_axis_tx.tvalid || s_axis_tx.tuser[0] || frame_oversize_next;
|
|
stat_tx_err_user_next = s_axis_tx.tuser[0];
|
|
stat_tx_err_underflow_next = !s_axis_tx.tvalid;
|
|
|
|
if (PADDING_EN && frame_min_count_reg != 0) begin
|
|
if (frame_min_count_reg > MIN_LEN_W'(CTRL_W)) begin
|
|
s_empty_next = 0;
|
|
state_next = STATE_PAD;
|
|
end else begin
|
|
if (keep2empty(s_axis_tx.tkeep) > 3'(CTRL_W-frame_min_count_reg)) begin
|
|
s_empty_next = 3'(CTRL_W-frame_min_count_reg);
|
|
end
|
|
if (frame_error_next) begin
|
|
state_next = STATE_ERR;
|
|
end else begin
|
|
state_next = STATE_FCS_1;
|
|
end
|
|
end
|
|
end else begin
|
|
if (frame_error_next) begin
|
|
state_next = STATE_ERR;
|
|
end else begin
|
|
state_next = STATE_FCS_1;
|
|
end
|
|
end
|
|
end else begin
|
|
state_next = STATE_PAYLOAD;
|
|
end
|
|
end
|
|
STATE_PAD: begin
|
|
// pad frame to MIN_FRAME_LEN
|
|
s_axis_tx_tready_next = frame_next; // drop frame
|
|
|
|
xgmii_txd_next = s_tdata_reg;
|
|
xgmii_txc_next = {CTRL_W{1'b0}};
|
|
|
|
s_tdata_next = 64'd0;
|
|
s_empty_next = 0;
|
|
|
|
stat_tx_byte_next = 4'(CTRL_W);
|
|
|
|
update_crc = 1'b1;
|
|
|
|
if (frame_min_count_reg > MIN_LEN_W'(CTRL_W)) begin
|
|
state_next = STATE_PAD;
|
|
end else begin
|
|
s_empty_next = 3'(CTRL_W-frame_min_count_reg);
|
|
if (frame_error_reg) begin
|
|
state_next = STATE_ERR;
|
|
end else begin
|
|
state_next = STATE_FCS_1;
|
|
end
|
|
end
|
|
end
|
|
STATE_FCS_1: begin
|
|
// last cycle
|
|
s_axis_tx_tready_next = frame_next; // drop frame
|
|
|
|
xgmii_txd_next = fcs_output_txd_0;
|
|
xgmii_txc_next = fcs_output_txc_0;
|
|
|
|
update_crc = 1'b1;
|
|
|
|
ifg_count_next = (cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + 8'(deficit_idle_count_reg);
|
|
if (s_empty_reg <= 4) begin
|
|
stat_tx_byte_next = 4'(CTRL_W);
|
|
state_next = STATE_FCS_2;
|
|
end else begin
|
|
stat_tx_byte_next = 12-s_empty_reg;
|
|
frame_len_next = frame_len_reg + 16'(12-s_empty_reg);
|
|
stat_tx_pkt_len_next = frame_len_next;
|
|
stat_tx_pkt_good_next = !frame_error_reg;
|
|
stat_tx_pkt_bad_next = frame_error_reg;
|
|
stat_tx_pkt_ucast_next = !is_mcast_reg;
|
|
stat_tx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
|
|
stat_tx_pkt_bcast_next = is_bcast_reg;
|
|
stat_tx_pkt_vlan_next = is_8021q_reg;
|
|
stat_tx_err_oversize_next = frame_oversize_reg;
|
|
|
|
state_next = STATE_IFG;
|
|
end
|
|
end
|
|
STATE_FCS_2: begin
|
|
// last cycle
|
|
s_axis_tx_tready_next = frame_next; // drop frame
|
|
|
|
xgmii_txd_next = fcs_output_txd_1;
|
|
xgmii_txc_next = fcs_output_txc_1;
|
|
|
|
stat_tx_byte_next = 4-s_empty_reg;
|
|
frame_len_next = frame_len_reg + 16'(4-s_empty_reg);
|
|
|
|
stat_tx_pkt_len_next = frame_len_next;
|
|
stat_tx_pkt_good_next = !frame_error_reg;
|
|
stat_tx_pkt_bad_next = frame_error_reg;
|
|
stat_tx_pkt_ucast_next = !is_mcast_reg;
|
|
stat_tx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
|
|
stat_tx_pkt_bcast_next = is_bcast_reg;
|
|
stat_tx_pkt_vlan_next = is_8021q_reg;
|
|
stat_tx_err_oversize_next = frame_oversize_reg;
|
|
|
|
if (DIC_EN) begin
|
|
if (ifg_count_next > 8'd7) begin
|
|
state_next = STATE_IFG;
|
|
end else begin
|
|
if (ifg_count_next >= 8'd4) begin
|
|
deficit_idle_count_next = 2'(ifg_count_next - 8'd4);
|
|
swap_lanes_next = 1'b1;
|
|
end else begin
|
|
deficit_idle_count_next = 2'(ifg_count_next);
|
|
ifg_count_next = 8'd0;
|
|
swap_lanes_next = 1'b0;
|
|
end
|
|
s_axis_tx_tready_next = cfg_tx_enable;
|
|
state_next = STATE_IDLE;
|
|
end
|
|
end else begin
|
|
if (ifg_count_next > 8'd4) begin
|
|
state_next = STATE_IFG;
|
|
end else begin
|
|
s_axis_tx_tready_next = cfg_tx_enable;
|
|
swap_lanes_next = ifg_count_next != 0;
|
|
state_next = STATE_IDLE;
|
|
end
|
|
end
|
|
end
|
|
STATE_ERR: begin
|
|
// terminate packet with error
|
|
s_axis_tx_tready_next = frame_next; // drop frame
|
|
|
|
// XGMII error
|
|
xgmii_txd_next = {XGMII_TERM, {7{XGMII_ERROR}}};
|
|
xgmii_txc_next = {CTRL_W{1'b1}};
|
|
|
|
ifg_count_next = cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12;
|
|
|
|
stat_tx_pkt_len_next = frame_len_reg;
|
|
stat_tx_pkt_good_next = !frame_error_reg;
|
|
stat_tx_pkt_bad_next = frame_error_reg;
|
|
stat_tx_pkt_ucast_next = !is_mcast_reg;
|
|
stat_tx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
|
|
stat_tx_pkt_bcast_next = is_bcast_reg;
|
|
stat_tx_pkt_vlan_next = is_8021q_reg;
|
|
stat_tx_err_oversize_next = frame_oversize_reg;
|
|
|
|
state_next = STATE_IFG;
|
|
end
|
|
STATE_IFG: begin
|
|
// send IFG
|
|
s_axis_tx_tready_next = frame_next; // drop frame
|
|
|
|
// XGMII idle
|
|
xgmii_txd_next = {CTRL_W{XGMII_IDLE}};
|
|
xgmii_txc_next = {CTRL_W{1'b1}};
|
|
|
|
if (ifg_count_reg > 8'd8) begin
|
|
ifg_count_next = ifg_count_reg - 8'd8;
|
|
end else begin
|
|
ifg_count_next = 8'd0;
|
|
end
|
|
|
|
if (DIC_EN) begin
|
|
if (ifg_count_next > 8'd7 || frame_reg) begin
|
|
state_next = STATE_IFG;
|
|
end else begin
|
|
if (ifg_count_next >= 8'd4) begin
|
|
deficit_idle_count_next = 2'(ifg_count_next - 8'd4);
|
|
swap_lanes_next = 1'b1;
|
|
end else begin
|
|
deficit_idle_count_next = 2'(ifg_count_next);
|
|
ifg_count_next = 8'd0;
|
|
swap_lanes_next = 1'b0;
|
|
end
|
|
s_axis_tx_tready_next = cfg_tx_enable;
|
|
state_next = STATE_IDLE;
|
|
end
|
|
end else begin
|
|
if (ifg_count_next > 8'd4 || frame_reg) begin
|
|
state_next = STATE_IFG;
|
|
end else begin
|
|
s_axis_tx_tready_next = cfg_tx_enable;
|
|
swap_lanes_next = ifg_count_next != 0;
|
|
state_next = STATE_IDLE;
|
|
end
|
|
end
|
|
end
|
|
default: begin
|
|
// invalid state, return to idle
|
|
state_next = STATE_IDLE;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always_ff @(posedge clk) begin
|
|
state_reg <= state_next;
|
|
|
|
swap_lanes_reg <= swap_lanes_next;
|
|
|
|
frame_start_reg <= frame_start_next;
|
|
frame_reg <= frame_next;
|
|
frame_error_reg <= frame_error_next;
|
|
frame_oversize_reg <= frame_oversize_next;
|
|
frame_min_count_reg <= frame_min_count_next;
|
|
hdr_ptr_reg <= hdr_ptr_next;
|
|
is_mcast_reg <= is_mcast_next;
|
|
is_bcast_reg <= is_bcast_next;
|
|
is_8021q_reg <= is_8021q_next;
|
|
frame_len_reg <= frame_len_next;
|
|
frame_len_lim_reg <= frame_len_lim_next;
|
|
ifg_cnt_reg <= ifg_cnt_next;
|
|
|
|
ifg_count_reg <= ifg_count_next;
|
|
deficit_idle_count_reg <= deficit_idle_count_next;
|
|
|
|
s_tdata_reg <= s_tdata_next;
|
|
s_empty_reg <= s_empty_next;
|
|
|
|
s_axis_tx_tready_reg <= s_axis_tx_tready_next;
|
|
|
|
m_axis_tx_cpl_valid_reg <= 1'b0;
|
|
m_axis_tx_cpl_valid_int_reg <= 1'b0;
|
|
|
|
start_packet_reg <= 2'b00;
|
|
|
|
stat_tx_byte_reg <= stat_tx_byte_next;
|
|
stat_tx_pkt_len_reg <= stat_tx_pkt_len_next;
|
|
stat_tx_pkt_ucast_reg <= stat_tx_pkt_ucast_next;
|
|
stat_tx_pkt_mcast_reg <= stat_tx_pkt_mcast_next;
|
|
stat_tx_pkt_bcast_reg <= stat_tx_pkt_bcast_next;
|
|
stat_tx_pkt_vlan_reg <= stat_tx_pkt_vlan_next;
|
|
stat_tx_pkt_good_reg <= stat_tx_pkt_good_next;
|
|
stat_tx_pkt_bad_reg <= stat_tx_pkt_bad_next;
|
|
stat_tx_err_oversize_reg <= stat_tx_err_oversize_next;
|
|
stat_tx_err_user_reg <= stat_tx_err_user_next;
|
|
stat_tx_err_underflow_reg <= stat_tx_err_underflow_next;
|
|
|
|
if (PTP_TS_EN && PTP_TS_FMT_TOD) begin
|
|
m_axis_tx_cpl_valid_reg <= m_axis_tx_cpl_valid_int_reg;
|
|
m_axis_tx_cpl_ts_adj_reg[15:0] <= m_axis_tx_cpl_ts_reg[15:0];
|
|
{m_axis_tx_cpl_ts_borrow_reg, m_axis_tx_cpl_ts_adj_reg[45:16]} <= $signed({1'b0, m_axis_tx_cpl_ts_reg[45:16]}) - $signed(31'd1000000000);
|
|
m_axis_tx_cpl_ts_adj_reg[47:46] <= 0;
|
|
m_axis_tx_cpl_ts_adj_reg[95:48] <= m_axis_tx_cpl_ts_reg[95:48] + 1;
|
|
end
|
|
|
|
if (frame_start_reg) begin
|
|
if (swap_lanes_reg) begin
|
|
if (PTP_TS_EN) begin
|
|
if (PTP_TS_FMT_TOD) begin
|
|
m_axis_tx_cpl_ts_reg[45:0] <= ptp_ts[45:0] + 46'(ts_inc_reg >> 1);
|
|
m_axis_tx_cpl_ts_reg[95:48] <= ptp_ts[95:48];
|
|
end else begin
|
|
m_axis_tx_cpl_ts_reg <= ptp_ts + PTP_TS_W'(ts_inc_reg >> 1);
|
|
end
|
|
end
|
|
start_packet_reg <= 2'b10;
|
|
end else begin
|
|
if (PTP_TS_EN) begin
|
|
m_axis_tx_cpl_ts_reg <= ptp_ts;
|
|
end
|
|
start_packet_reg <= 2'b01;
|
|
end
|
|
m_axis_tx_cpl_tag_reg <= s_axis_tx.tid;
|
|
if (TX_CPL_CTRL_IN_TUSER) begin
|
|
if (PTP_TS_FMT_TOD) begin
|
|
m_axis_tx_cpl_valid_int_reg <= (s_axis_tx.tuser >> 1) == 0;
|
|
end else begin
|
|
m_axis_tx_cpl_valid_reg <= (s_axis_tx.tuser >> 1) == 0;
|
|
end
|
|
end else begin
|
|
if (PTP_TS_FMT_TOD) begin
|
|
m_axis_tx_cpl_valid_int_reg <= 1'b1;
|
|
end else begin
|
|
m_axis_tx_cpl_valid_reg <= 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
for (integer i = 0; i < 7; i = i + 1) begin
|
|
crc_state_reg[i] <= crc_state_next[i];
|
|
end
|
|
|
|
if (update_crc) begin
|
|
crc_state_reg[7] <= crc_state_next[7];
|
|
end
|
|
|
|
if (reset_crc) begin
|
|
crc_state_reg[7] <= '1;
|
|
end
|
|
|
|
swap_txd <= xgmii_txd_next[63:32];
|
|
swap_txc <= xgmii_txc_next[7:4];
|
|
|
|
if (swap_lanes_reg) begin
|
|
xgmii_txd_reg <= {xgmii_txd_next[31:0], swap_txd};
|
|
xgmii_txc_reg <= {xgmii_txc_next[3:0], swap_txc};
|
|
end else begin
|
|
xgmii_txd_reg <= xgmii_txd_next;
|
|
xgmii_txc_reg <= xgmii_txc_next;
|
|
end
|
|
|
|
last_ts_reg <= (4+16)'(ptp_ts);
|
|
ts_inc_reg <= (4+16)'(ptp_ts) - last_ts_reg;
|
|
|
|
if (rst) begin
|
|
state_reg <= STATE_IDLE;
|
|
|
|
frame_start_reg <= 1'b0;
|
|
frame_reg <= 1'b0;
|
|
|
|
swap_lanes_reg <= 1'b0;
|
|
|
|
ifg_count_reg <= 8'd0;
|
|
deficit_idle_count_reg <= 2'd0;
|
|
|
|
s_axis_tx_tready_reg <= 1'b0;
|
|
|
|
m_axis_tx_cpl_valid_reg <= 1'b0;
|
|
m_axis_tx_cpl_valid_int_reg <= 1'b0;
|
|
|
|
xgmii_txd_reg <= {CTRL_W{XGMII_IDLE}};
|
|
xgmii_txc_reg <= {CTRL_W{1'b1}};
|
|
|
|
start_packet_reg <= 2'b00;
|
|
|
|
stat_tx_byte_reg <= '0;
|
|
stat_tx_pkt_len_reg <= '0;
|
|
stat_tx_pkt_ucast_reg <= 1'b0;
|
|
stat_tx_pkt_mcast_reg <= 1'b0;
|
|
stat_tx_pkt_bcast_reg <= 1'b0;
|
|
stat_tx_pkt_vlan_reg <= 1'b0;
|
|
stat_tx_pkt_good_reg <= 1'b0;
|
|
stat_tx_pkt_bad_reg <= 1'b0;
|
|
stat_tx_err_oversize_reg <= 1'b0;
|
|
stat_tx_err_user_reg <= 1'b0;
|
|
stat_tx_err_underflow_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|