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75 lines
2.1 KiB
Makefile
75 lines
2.1 KiB
Makefile
# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2020-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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RTL_DIR = ../../rtl
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LIB_DIR = ../../lib
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TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
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DUT = cndm_micro_pcie_us
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = test_$(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
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VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
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VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
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VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
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VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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# module parameters
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export PARAM_SIM := "1'b1"
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export PARAM_VENDOR := "\"XILINX\""
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export PARAM_FAMILY := "\"virtexuplus\""
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# Structural configuration
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export PARAM_PORTS := 2
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# PTP configuration
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export PARAM_PTP_TS_EN := 1
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export PARAM_PTP_TS_FMT_TOD := 0
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export PARAM_PTP_CLK_PER_NS_NUM := 512
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export PARAM_PTP_CLK_PER_NS_DENOM := 165
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# PCIe interface configuration
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export PARAM_AXIS_PCIE_DATA_W := 256
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# AXI lite interface configuration (control)
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export PARAM_AXIL_CTRL_DATA_W := 32
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export PARAM_AXIL_CTRL_ADDR_W := 24
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# MAC configuration
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export PARAM_MAC_DATA_W := 32
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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VERILATOR_TRACE = 1
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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