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https://github.com/fpganinja/taxi.git
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904 lines
32 KiB
Systemverilog
904 lines
32 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream asynchronous FIFO
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*/
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module taxi_axis_async_fifo #
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(
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// FIFO depth in words
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// KEEP_W words per cycle if KEEP_EN set
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// Rounded up to nearest power of 2 cycles
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parameter DEPTH = 4096,
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// FIFO ramstyle attribute
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parameter FIFO_RAMSTYLE = "auto",
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// number of RAM pipeline registers
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parameter RAM_PIPELINE = 1,
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// use output FIFO
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// When set, the RAM read enable and pipeline clock enables are removed
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parameter logic OUTPUT_FIFO_EN = 1'b0,
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// output FIFO ramstyle attribute
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parameter OUTPUT_FIFO_RAMSTYLE = "distributed",
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// Frame FIFO mode - operate on frames instead of cycles
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// When set, m_axis_tvalid will not be deasserted within a frame
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// Requires LAST_EN set
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parameter logic FRAME_FIFO = 1'b0,
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// tuser value for bad frame marker
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parameter USER_BAD_FRAME_VALUE = 1'b1,
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// tuser mask for bad frame marker
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parameter USER_BAD_FRAME_MASK = 1'b1,
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// Drop frames larger than FIFO
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// Requires FRAME_FIFO set
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parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
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// Drop frames marked bad
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// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
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parameter logic DROP_BAD_FRAME = 1'b0,
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// Drop incoming frames when full
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// When set, s_axis_tready is always asserted
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// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
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parameter logic DROP_WHEN_FULL = 1'b0,
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// Mark incoming frames as bad frames when full
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// When set, s_axis_tready is always asserted
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// Requires FRAME_FIFO to be clear
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parameter logic MARK_WHEN_FULL = 1'b0,
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// Enable pause request input
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parameter logic PAUSE_EN = 1'b0,
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// Pause between frames
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parameter logic FRAME_PAUSE = FRAME_FIFO
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)
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(
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/*
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* AXI4-Stream input (sink)
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*/
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input wire logic s_clk,
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input wire logic s_rst,
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taxi_axis_if.snk s_axis,
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/*
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* AXI4-Stream output (source)
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*/
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input wire logic m_clk,
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input wire logic m_rst,
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taxi_axis_if.src m_axis,
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/*
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* Pause
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*/
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input wire logic s_pause_req = 1'b0,
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output wire logic s_pause_ack,
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input wire logic m_pause_req = 1'b0,
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output wire logic m_pause_ack,
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/*
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* Status
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*/
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output wire logic [$clog2(DEPTH):0] s_status_depth,
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output wire logic [$clog2(DEPTH):0] s_status_depth_commit,
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output wire logic s_status_overflow,
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output wire logic s_status_bad_frame,
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output wire logic s_status_good_frame,
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output wire logic [$clog2(DEPTH):0] m_status_depth,
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output wire logic [$clog2(DEPTH):0] m_status_depth_commit,
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output wire logic m_status_overflow,
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output wire logic m_status_bad_frame,
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output wire logic m_status_good_frame
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);
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// extract parameters
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localparam DATA_W = s_axis.DATA_W;
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localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis.KEEP_EN;
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localparam KEEP_W = s_axis.KEEP_W;
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localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN;
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localparam logic LAST_EN = s_axis.LAST_EN && m_axis.LAST_EN;
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localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN;
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localparam ID_W = s_axis.ID_W;
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localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN;
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localparam DEST_W = s_axis.DEST_W;
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localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN;
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localparam USER_W = s_axis.USER_W;
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localparam CL_DEPTH = $clog2(DEPTH);
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localparam CL_KEEP_W = $clog2(KEEP_W);
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localparam FIFO_AW = (KEEP_EN && KEEP_W > 1) ? $clog2(DEPTH/KEEP_W) : CL_DEPTH;
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localparam OUTPUT_FIFO_AW = RAM_PIPELINE < 2 ? 3 : $clog2(RAM_PIPELINE*2+7);
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// check configuration
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if (FRAME_FIFO && !LAST_EN)
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$fatal(0, "Error: FRAME_FIFO set requires LAST_EN set (instance %m)");
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if (DROP_OVERSIZE_FRAME && !FRAME_FIFO)
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$fatal(0, "Error: DROP_OVERSIZE_FRAME set requires FRAME_FIFO set (instance %m)");
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if (DROP_BAD_FRAME && !(FRAME_FIFO && DROP_OVERSIZE_FRAME))
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$fatal(0, "Error: DROP_BAD_FRAME set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
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if (DROP_WHEN_FULL && !(FRAME_FIFO && DROP_OVERSIZE_FRAME))
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$fatal(0, "Error: DROP_WHEN_FULL set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
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if ((DROP_BAD_FRAME || MARK_WHEN_FULL) && (USER_BAD_FRAME_MASK & {USER_W{1'b1}}) == 0)
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$fatal(0, "Error: Invalid USER_BAD_FRAME_MASK value (instance %m)");
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if (MARK_WHEN_FULL && FRAME_FIFO)
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$fatal(0, "Error: MARK_WHEN_FULL is not compatible with FRAME_FIFO (instance %m)");
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if (MARK_WHEN_FULL && !LAST_EN)
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$fatal(0, "Error: MARK_WHEN_FULL set requires LAST_EN set (instance %m)");
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if (m_axis.DATA_W != DATA_W)
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$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
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if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
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$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
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localparam KEEP_OFFSET = DATA_W;
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localparam STRB_OFFSET = KEEP_OFFSET + (KEEP_EN ? KEEP_W : 0);
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localparam LAST_OFFSET = STRB_OFFSET + (STRB_EN ? KEEP_W : 0);
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localparam ID_OFFSET = LAST_OFFSET + (LAST_EN ? 1 : 0);
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localparam DEST_OFFSET = ID_OFFSET + (ID_EN ? ID_W : 0);
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localparam USER_OFFSET = DEST_OFFSET + (DEST_EN ? DEST_W : 0);
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localparam WIDTH = USER_OFFSET + (USER_EN ? USER_W : 0);
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function [FIFO_AW:0] bin2gray(input [FIFO_AW:0] b);
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bin2gray = b ^ (b >> 1);
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endfunction
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function [FIFO_AW:0] gray2bin(input [FIFO_AW:0] g);
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for (integer i = 0; i <= FIFO_AW; i = i + 1) begin
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gray2bin[i] = ^(g >> i);
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end
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endfunction
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logic [FIFO_AW:0] wr_ptr_reg = '0;
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logic [FIFO_AW:0] wr_ptr_commit_reg = '0;
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logic [FIFO_AW:0] wr_ptr_gray_reg = '0;
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logic [FIFO_AW:0] wr_ptr_sync_commit_reg = '0;
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logic [FIFO_AW:0] rd_ptr_reg = '0;
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logic [FIFO_AW:0] rd_ptr_gray_reg = '0;
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logic [FIFO_AW:0] wr_ptr_conv_reg = '0;
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logic [FIFO_AW:0] rd_ptr_conv_reg = '0;
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logic [FIFO_AW:0] wr_ptr_temp;
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logic [FIFO_AW:0] rd_ptr_temp;
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(* SHREG_EXTRACT = "NO" *)
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logic [FIFO_AW:0] wr_ptr_gray_sync1_reg = '0;
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(* SHREG_EXTRACT = "NO" *)
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logic [FIFO_AW:0] wr_ptr_gray_sync2_reg = '0;
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(* SHREG_EXTRACT = "NO" *)
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logic [FIFO_AW:0] wr_ptr_commit_sync_reg = '0;
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(* SHREG_EXTRACT = "NO" *)
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logic [FIFO_AW:0] rd_ptr_gray_sync1_reg = '0;
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(* SHREG_EXTRACT = "NO" *)
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logic [FIFO_AW:0] rd_ptr_gray_sync2_reg = '0;
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logic wr_ptr_update_valid_reg = 1'b0;
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logic wr_ptr_update_reg = 1'b0;
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(* SHREG_EXTRACT = "NO" *)
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logic wr_ptr_update_sync1_reg = 1'b0;
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(* SHREG_EXTRACT = "NO" *)
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logic wr_ptr_update_sync2_reg = 1'b0;
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(* SHREG_EXTRACT = "NO" *)
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logic wr_ptr_update_sync3_reg = 1'b0;
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(* SHREG_EXTRACT = "NO" *)
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logic wr_ptr_update_ack_sync1_reg = 1'b0;
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(* SHREG_EXTRACT = "NO" *)
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logic wr_ptr_update_ack_sync2_reg = 1'b0;
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(* SHREG_EXTRACT = "NO" *)
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logic s_rst_sync1_reg = 1'b1;
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(* SHREG_EXTRACT = "NO" *)
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logic s_rst_sync2_reg = 1'b1;
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(* SHREG_EXTRACT = "NO" *)
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logic s_rst_sync3_reg = 1'b1;
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(* SHREG_EXTRACT = "NO" *)
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logic m_rst_sync1_reg = 1'b1;
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(* SHREG_EXTRACT = "NO" *)
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logic m_rst_sync2_reg = 1'b1;
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(* SHREG_EXTRACT = "NO" *)
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logic m_rst_sync3_reg = 1'b1;
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(* ramstyle = "no_rw_check" *)
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logic [WIDTH-1:0] mem[(2**FIFO_AW)-1:0];
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logic mem_read_data_valid_reg = 1'b0;
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(* shreg_extract = "no" *)
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logic [WIDTH-1:0] mem_rd_data_pipe_reg[RAM_PIPELINE+1-1:0];
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logic [RAM_PIPELINE+1-1:0] mem_rd_valid_pipe_reg = 0;
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// full when first TWO MSBs do NOT match, but rest matches
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// (gray code equivalent of first MSB different but rest same)
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wire full = wr_ptr_gray_reg == (rd_ptr_gray_sync2_reg ^ {2'b11, {FIFO_AW-1{1'b0}}});
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// empty when pointers match exactly
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wire empty = FRAME_FIFO ? (rd_ptr_reg == wr_ptr_commit_sync_reg) : (rd_ptr_gray_reg == wr_ptr_gray_sync2_reg);
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// overflow within packet
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wire full_wr = wr_ptr_reg == (wr_ptr_commit_reg ^ {1'b1, {FIFO_AW{1'b0}}});
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// control signals
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logic write;
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logic read;
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logic store_output;
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logic s_frame_reg = 1'b0;
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logic m_frame_reg = 1'b0;
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logic drop_frame_reg = 1'b0;
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logic mark_frame_reg = 1'b0;
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logic send_frame_reg = 1'b0;
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logic overflow_reg = 1'b0;
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logic bad_frame_reg = 1'b0;
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logic good_frame_reg = 1'b0;
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logic m_empty_pipe_reg = 1'b0;
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logic m_terminate_frame_reg = 1'b0;
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logic [FIFO_AW:0] s_depth_reg = '0;
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logic [FIFO_AW:0] s_depth_commit_reg = '0;
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logic [FIFO_AW:0] m_depth_reg = '0;
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logic [FIFO_AW:0] m_depth_commit_reg = '0;
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logic overflow_sync1_reg = 1'b0;
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logic overflow_sync2_reg = 1'b0;
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logic overflow_sync3_reg = 1'b0;
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logic overflow_sync4_reg = 1'b0;
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logic bad_frame_sync1_reg = 1'b0;
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logic bad_frame_sync2_reg = 1'b0;
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logic bad_frame_sync3_reg = 1'b0;
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logic bad_frame_sync4_reg = 1'b0;
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logic good_frame_sync1_reg = 1'b0;
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logic good_frame_sync2_reg = 1'b0;
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logic good_frame_sync3_reg = 1'b0;
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logic good_frame_sync4_reg = 1'b0;
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assign s_axis.tready = (FRAME_FIFO ? (!full || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : (!full || MARK_WHEN_FULL)) && !s_rst_sync3_reg;
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wire [WIDTH-1:0] mem_wr_data;
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generate
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assign mem_wr_data[DATA_W-1:0] = s_axis.tdata;
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if (KEEP_EN) assign mem_wr_data[KEEP_OFFSET +: KEEP_W] = s_axis.tkeep;
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if (STRB_EN) assign mem_wr_data[STRB_OFFSET +: KEEP_W] = s_axis.tstrb;
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if (LAST_EN) assign mem_wr_data[LAST_OFFSET] = s_axis.tlast | mark_frame_reg;
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if (ID_EN) assign mem_wr_data[ID_OFFSET +: ID_W] = s_axis.tid;
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if (DEST_EN) assign mem_wr_data[DEST_OFFSET +: DEST_W] = s_axis.tdest;
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if (USER_EN) assign mem_wr_data[USER_OFFSET +: USER_W] = mark_frame_reg ? USER_BAD_FRAME_VALUE : s_axis.tuser;
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endgenerate
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wire [WIDTH-1:0] mem_rd_data = mem_rd_data_pipe_reg[RAM_PIPELINE+1-1];
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wire m_axis_tready_pipe;
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wire m_axis_tvalid_pipe = mem_rd_valid_pipe_reg[RAM_PIPELINE+1-1];
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wire [DATA_W-1:0] m_axis_tdata_pipe = mem_rd_data[DATA_W-1:0];
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wire [KEEP_W-1:0] m_axis_tkeep_pipe;
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wire [KEEP_W-1:0] m_axis_tstrb_pipe;
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wire m_axis_tlast_pipe;
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wire [ID_W-1:0] m_axis_tid_pipe;
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wire [DEST_W-1:0] m_axis_tdest_pipe;
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wire [USER_W-1:0] m_axis_tuser_pipe;
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if (KEEP_EN) begin
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assign m_axis_tkeep_pipe = mem_rd_data[KEEP_OFFSET +: KEEP_W];
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end else begin
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assign m_axis_tkeep_pipe = '1;
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end
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if (STRB_EN) begin
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assign m_axis_tstrb_pipe = mem_rd_data[STRB_OFFSET +: KEEP_W];
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end else begin
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assign m_axis_tstrb_pipe = m_axis_tkeep_pipe;
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end
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if (LAST_EN) begin
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assign m_axis_tlast_pipe = mem_rd_data[LAST_OFFSET] | m_terminate_frame_reg;
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end else begin
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assign m_axis_tlast_pipe = 1'b1;
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end
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if (ID_EN) begin
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assign m_axis_tid_pipe = mem_rd_data[ID_OFFSET +: ID_W];
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end else begin
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assign m_axis_tid_pipe = '0;
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end
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if (DEST_EN) begin
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assign m_axis_tdest_pipe = mem_rd_data[DEST_OFFSET +: DEST_W];
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end else begin
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assign m_axis_tdest_pipe = '0;
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end
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if (USER_EN) begin
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assign m_axis_tuser_pipe = m_terminate_frame_reg ? USER_BAD_FRAME_VALUE : mem_rd_data[USER_OFFSET +: USER_W];
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end else begin
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assign m_axis_tuser_pipe = '0;
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end
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wire m_axis_tready_out;
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wire m_axis_tvalid_out;
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wire [DATA_W-1:0] m_axis_tdata_out;
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wire [KEEP_W-1:0] m_axis_tkeep_out;
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wire [KEEP_W-1:0] m_axis_tstrb_out;
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wire m_axis_tlast_out;
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wire [ID_W-1:0] m_axis_tid_out;
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wire [DEST_W-1:0] m_axis_tdest_out;
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wire [USER_W-1:0] m_axis_tuser_out;
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wire pipe_ready;
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assign s_status_depth = (KEEP_EN && KEEP_W > 1) ? {s_depth_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(s_depth_reg);
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assign s_status_depth_commit = (KEEP_EN && KEEP_W > 1) ? {s_depth_commit_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(s_depth_commit_reg);
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assign s_status_overflow = overflow_reg;
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assign s_status_bad_frame = bad_frame_reg;
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assign s_status_good_frame = good_frame_reg;
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assign m_status_depth = (KEEP_EN && KEEP_W > 1) ? {m_depth_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(m_depth_reg);
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assign m_status_depth_commit = (KEEP_EN && KEEP_W > 1) ? {m_depth_commit_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(m_depth_commit_reg);
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assign m_status_overflow = overflow_sync3_reg ^ overflow_sync4_reg;
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assign m_status_bad_frame = bad_frame_sync3_reg ^ bad_frame_sync4_reg;
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assign m_status_good_frame = good_frame_sync3_reg ^ good_frame_sync4_reg;
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// reset synchronization
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always_ff @(posedge m_clk or posedge m_rst) begin
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if (m_rst) begin
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s_rst_sync1_reg <= 1'b1;
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end else begin
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s_rst_sync1_reg <= 1'b0;
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end
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end
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always_ff @(posedge s_clk) begin
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s_rst_sync2_reg <= s_rst_sync1_reg;
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s_rst_sync3_reg <= s_rst_sync2_reg;
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end
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always_ff @(posedge s_clk or posedge s_rst) begin
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if (s_rst) begin
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m_rst_sync1_reg <= 1'b1;
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end else begin
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m_rst_sync1_reg <= 1'b0;
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end
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end
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always_ff @(posedge m_clk) begin
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m_rst_sync2_reg <= m_rst_sync1_reg;
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m_rst_sync3_reg <= m_rst_sync2_reg;
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end
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// Write logic
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always_ff @(posedge s_clk) begin
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overflow_reg <= 1'b0;
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bad_frame_reg <= 1'b0;
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good_frame_reg <= 1'b0;
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if (FRAME_FIFO && wr_ptr_update_valid_reg) begin
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// have updated pointer to sync
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if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
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// no sync in progress; sync update
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wr_ptr_update_valid_reg <= 1'b0;
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wr_ptr_sync_commit_reg <= wr_ptr_commit_reg;
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wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
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end
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end
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if (s_axis.tready && s_axis.tvalid && LAST_EN) begin
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// track input frame status
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s_frame_reg <= !s_axis.tlast;
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end
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if (s_rst_sync3_reg && LAST_EN) begin
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// if sink side is reset during transfer, drop partial frame
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if (s_frame_reg && !(s_axis.tready && s_axis.tvalid && s_axis.tlast)) begin
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drop_frame_reg <= 1'b1;
|
|
end
|
|
if (s_axis.tready && s_axis.tvalid && !s_axis.tlast) begin
|
|
drop_frame_reg <= 1'b1;
|
|
end
|
|
end
|
|
|
|
if (FRAME_FIFO) begin
|
|
// frame FIFO mode
|
|
if (s_axis.tready && s_axis.tvalid) begin
|
|
// transfer in
|
|
if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
|
|
// full, packet overflow, or currently dropping frame
|
|
// drop frame
|
|
drop_frame_reg <= 1'b1;
|
|
if (s_axis.tlast) begin
|
|
// end of frame, reset write pointer
|
|
wr_ptr_temp = wr_ptr_commit_reg;
|
|
wr_ptr_reg <= wr_ptr_temp;
|
|
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
|
|
drop_frame_reg <= 1'b0;
|
|
overflow_reg <= 1'b1;
|
|
end
|
|
end else begin
|
|
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
|
|
wr_ptr_temp = wr_ptr_reg + 1;
|
|
wr_ptr_reg <= wr_ptr_temp;
|
|
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
|
|
if (s_axis.tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin
|
|
// end of frame or send frame
|
|
send_frame_reg <= !s_axis.tlast;
|
|
if (s_axis.tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis.tuser ^ USER_BAD_FRAME_VALUE)) begin
|
|
// bad packet, reset write pointer
|
|
wr_ptr_temp = wr_ptr_commit_reg;
|
|
wr_ptr_reg <= wr_ptr_temp;
|
|
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
|
|
bad_frame_reg <= 1'b1;
|
|
end else begin
|
|
// good packet or packet overflow, update write pointer
|
|
wr_ptr_temp = wr_ptr_reg + 1;
|
|
wr_ptr_reg <= wr_ptr_temp;
|
|
wr_ptr_commit_reg <= wr_ptr_temp;
|
|
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
|
|
|
|
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
|
|
// no sync in progress; sync update
|
|
wr_ptr_update_valid_reg <= 1'b0;
|
|
wr_ptr_sync_commit_reg <= wr_ptr_temp;
|
|
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
|
|
end else begin
|
|
// sync in progress; flag it for later
|
|
wr_ptr_update_valid_reg <= 1'b1;
|
|
end
|
|
|
|
good_frame_reg <= s_axis.tlast;
|
|
end
|
|
end
|
|
end
|
|
end else if (s_axis.tvalid && full_wr && FRAME_FIFO && !DROP_OVERSIZE_FRAME) begin
|
|
// data valid with packet overflow
|
|
// update write pointer
|
|
send_frame_reg <= 1'b1;
|
|
wr_ptr_temp = wr_ptr_reg;
|
|
wr_ptr_reg <= wr_ptr_temp;
|
|
wr_ptr_commit_reg <= wr_ptr_temp;
|
|
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
|
|
|
|
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
|
|
// no sync in progress; sync update
|
|
wr_ptr_update_valid_reg <= 1'b0;
|
|
wr_ptr_sync_commit_reg <= wr_ptr_temp;
|
|
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
|
|
end else begin
|
|
// sync in progress; flag it for later
|
|
wr_ptr_update_valid_reg <= 1'b1;
|
|
end
|
|
end
|
|
end else begin
|
|
// normal FIFO mode
|
|
if (s_axis.tready && s_axis.tvalid) begin
|
|
if (drop_frame_reg && LAST_EN) begin
|
|
// currently dropping frame
|
|
if (s_axis.tlast) begin
|
|
// end of frame
|
|
if (!full && mark_frame_reg && MARK_WHEN_FULL) begin
|
|
// terminate marked frame
|
|
mark_frame_reg <= 1'b0;
|
|
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
|
|
wr_ptr_temp = wr_ptr_reg + 1;
|
|
wr_ptr_reg <= wr_ptr_temp;
|
|
wr_ptr_commit_reg <= wr_ptr_temp;
|
|
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
|
|
end
|
|
// end of frame, clear drop flag
|
|
drop_frame_reg <= 1'b0;
|
|
overflow_reg <= 1'b1;
|
|
end
|
|
end else if ((full || mark_frame_reg) && MARK_WHEN_FULL) begin
|
|
// full or marking frame
|
|
// drop frame; mark if this isn't the first cycle
|
|
drop_frame_reg <= 1'b1;
|
|
mark_frame_reg <= mark_frame_reg || s_frame_reg;
|
|
if (s_axis.tlast) begin
|
|
drop_frame_reg <= 1'b0;
|
|
overflow_reg <= 1'b1;
|
|
end
|
|
end else begin
|
|
// transfer in
|
|
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
|
|
wr_ptr_temp = wr_ptr_reg + 1;
|
|
wr_ptr_reg <= wr_ptr_temp;
|
|
wr_ptr_commit_reg <= wr_ptr_temp;
|
|
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
|
|
end
|
|
end else if ((!full && !drop_frame_reg && mark_frame_reg) && MARK_WHEN_FULL) begin
|
|
// terminate marked frame
|
|
mark_frame_reg <= 1'b0;
|
|
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
|
|
wr_ptr_temp = wr_ptr_reg + 1;
|
|
wr_ptr_reg <= wr_ptr_temp;
|
|
wr_ptr_commit_reg <= wr_ptr_temp;
|
|
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
|
|
end
|
|
end
|
|
|
|
if (s_rst_sync3_reg) begin
|
|
wr_ptr_reg <= '0;
|
|
wr_ptr_commit_reg <= '0;
|
|
wr_ptr_gray_reg <= '0;
|
|
wr_ptr_sync_commit_reg <= '0;
|
|
|
|
wr_ptr_update_valid_reg <= 1'b0;
|
|
wr_ptr_update_reg <= 1'b0;
|
|
end
|
|
|
|
if (s_rst) begin
|
|
wr_ptr_reg <= '0;
|
|
wr_ptr_commit_reg <= '0;
|
|
wr_ptr_gray_reg <= '0;
|
|
wr_ptr_sync_commit_reg <= '0;
|
|
|
|
wr_ptr_update_valid_reg <= 1'b0;
|
|
wr_ptr_update_reg <= 1'b0;
|
|
|
|
s_frame_reg <= 1'b0;
|
|
|
|
drop_frame_reg <= 1'b0;
|
|
mark_frame_reg <= 1'b0;
|
|
send_frame_reg <= 1'b0;
|
|
overflow_reg <= 1'b0;
|
|
bad_frame_reg <= 1'b0;
|
|
good_frame_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
// Write-side status
|
|
always_ff @(posedge s_clk) begin
|
|
rd_ptr_conv_reg <= gray2bin(rd_ptr_gray_sync2_reg);
|
|
s_depth_reg <= wr_ptr_reg - rd_ptr_conv_reg;
|
|
s_depth_commit_reg <= wr_ptr_commit_reg - rd_ptr_conv_reg;
|
|
end
|
|
|
|
// pointer synchronization
|
|
always_ff @(posedge s_clk) begin
|
|
rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg;
|
|
rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg;
|
|
wr_ptr_update_ack_sync1_reg <= wr_ptr_update_sync3_reg;
|
|
wr_ptr_update_ack_sync2_reg <= wr_ptr_update_ack_sync1_reg;
|
|
|
|
if (s_rst) begin
|
|
rd_ptr_gray_sync1_reg <= '0;
|
|
rd_ptr_gray_sync2_reg <= '0;
|
|
wr_ptr_update_ack_sync1_reg <= 1'b0;
|
|
wr_ptr_update_ack_sync2_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
always_ff @(posedge m_clk) begin
|
|
wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;
|
|
wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg;
|
|
if (FRAME_FIFO && wr_ptr_update_sync2_reg ^ wr_ptr_update_sync3_reg) begin
|
|
wr_ptr_commit_sync_reg <= wr_ptr_sync_commit_reg;
|
|
end
|
|
wr_ptr_update_sync1_reg <= wr_ptr_update_reg;
|
|
wr_ptr_update_sync2_reg <= wr_ptr_update_sync1_reg;
|
|
wr_ptr_update_sync3_reg <= wr_ptr_update_sync2_reg;
|
|
|
|
if (FRAME_FIFO && m_rst_sync3_reg) begin
|
|
wr_ptr_gray_sync1_reg <= '0;
|
|
end
|
|
|
|
if (m_rst) begin
|
|
wr_ptr_gray_sync1_reg <= '0;
|
|
wr_ptr_gray_sync2_reg <= '0;
|
|
wr_ptr_commit_sync_reg <= '0;
|
|
wr_ptr_update_sync1_reg <= 1'b0;
|
|
wr_ptr_update_sync2_reg <= 1'b0;
|
|
wr_ptr_update_sync3_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
// status synchronization
|
|
always_ff @(posedge s_clk) begin
|
|
overflow_sync1_reg <= overflow_sync1_reg ^ overflow_reg;
|
|
bad_frame_sync1_reg <= bad_frame_sync1_reg ^ bad_frame_reg;
|
|
good_frame_sync1_reg <= good_frame_sync1_reg ^ good_frame_reg;
|
|
|
|
if (s_rst) begin
|
|
overflow_sync1_reg <= 1'b0;
|
|
bad_frame_sync1_reg <= 1'b0;
|
|
good_frame_sync1_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
always_ff @(posedge m_clk) begin
|
|
overflow_sync2_reg <= overflow_sync1_reg;
|
|
overflow_sync3_reg <= overflow_sync2_reg;
|
|
overflow_sync4_reg <= overflow_sync3_reg;
|
|
bad_frame_sync2_reg <= bad_frame_sync1_reg;
|
|
bad_frame_sync3_reg <= bad_frame_sync2_reg;
|
|
bad_frame_sync4_reg <= bad_frame_sync3_reg;
|
|
good_frame_sync2_reg <= good_frame_sync1_reg;
|
|
good_frame_sync3_reg <= good_frame_sync2_reg;
|
|
good_frame_sync4_reg <= good_frame_sync3_reg;
|
|
|
|
if (m_rst) begin
|
|
overflow_sync2_reg <= 1'b0;
|
|
overflow_sync3_reg <= 1'b0;
|
|
overflow_sync4_reg <= 1'b0;
|
|
bad_frame_sync2_reg <= 1'b0;
|
|
bad_frame_sync3_reg <= 1'b0;
|
|
bad_frame_sync4_reg <= 1'b0;
|
|
good_frame_sync2_reg <= 1'b0;
|
|
good_frame_sync3_reg <= 1'b0;
|
|
good_frame_sync4_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
// Read logic
|
|
always_ff @(posedge m_clk) begin
|
|
if (m_axis_tready_pipe) begin
|
|
// output ready; invalidate stage
|
|
mem_rd_valid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0;
|
|
m_terminate_frame_reg <= 1'b0;
|
|
end
|
|
|
|
for (integer j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin
|
|
// if (m_axis_tready_pipe || ((~mem_rd_valid_pipe_reg) >> j)) begin
|
|
if (m_axis_tready_pipe || ((RAM_PIPELINE+1)'(~mem_rd_valid_pipe_reg) >> j) != 0) begin
|
|
// output ready or bubble in pipeline; transfer down pipeline
|
|
mem_rd_valid_pipe_reg[j] <= mem_rd_valid_pipe_reg[j-1];
|
|
mem_rd_data_pipe_reg[j] <= mem_rd_data_pipe_reg[j-1];
|
|
mem_rd_valid_pipe_reg[j-1] <= 1'b0;
|
|
end
|
|
end
|
|
|
|
if (m_axis_tready_pipe || &mem_rd_valid_pipe_reg == 0) begin
|
|
// output ready or bubble in pipeline; read new data from FIFO
|
|
mem_rd_valid_pipe_reg[0] <= 1'b0;
|
|
mem_rd_data_pipe_reg[0] <= mem[rd_ptr_reg[FIFO_AW-1:0]];
|
|
if (!empty && !m_rst_sync3_reg && !m_empty_pipe_reg && pipe_ready) begin
|
|
// not empty, increment pointer
|
|
mem_rd_valid_pipe_reg[0] <= 1'b1;
|
|
rd_ptr_temp = rd_ptr_reg + 1;
|
|
rd_ptr_reg <= rd_ptr_temp;
|
|
rd_ptr_gray_reg <= rd_ptr_temp ^ (rd_ptr_temp >> 1);
|
|
end
|
|
end
|
|
|
|
if (m_axis_tvalid_pipe && LAST_EN) begin
|
|
// track output frame status
|
|
if (m_axis_tlast_pipe && m_axis_tready_pipe) begin
|
|
m_frame_reg <= 1'b0;
|
|
end else begin
|
|
m_frame_reg <= 1'b1;
|
|
end
|
|
end
|
|
|
|
if (m_empty_pipe_reg && mem_rd_valid_pipe_reg == 0 && LAST_EN) begin
|
|
// terminate frame
|
|
// (only for frame transfers interrupted by source reset)
|
|
if (m_frame_reg) begin
|
|
mem_rd_valid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b1;
|
|
m_terminate_frame_reg <= 1'b1;
|
|
end
|
|
m_empty_pipe_reg <= 1'b0;
|
|
end
|
|
|
|
if (m_rst_sync3_reg && LAST_EN) begin
|
|
// if source side is reset during transfer, drop partial frame
|
|
m_empty_pipe_reg <= 1'b1;
|
|
end
|
|
|
|
if (m_rst_sync3_reg) begin
|
|
rd_ptr_reg <= '0;
|
|
rd_ptr_gray_reg <= '0;
|
|
end
|
|
|
|
if (m_rst) begin
|
|
rd_ptr_reg <= '0;
|
|
rd_ptr_gray_reg <= '0;
|
|
mem_rd_valid_pipe_reg <= '0;
|
|
m_frame_reg <= 1'b0;
|
|
m_empty_pipe_reg <= 1'b0;
|
|
m_terminate_frame_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
// Read-side status
|
|
always_ff @(posedge m_clk) begin
|
|
wr_ptr_conv_reg <= gray2bin(wr_ptr_gray_sync2_reg);
|
|
m_depth_reg <= wr_ptr_conv_reg - rd_ptr_reg;
|
|
m_depth_commit_reg <= FRAME_FIFO ? wr_ptr_commit_sync_reg - rd_ptr_reg : wr_ptr_conv_reg - rd_ptr_reg;
|
|
end
|
|
|
|
if (!OUTPUT_FIFO_EN) begin
|
|
|
|
assign pipe_ready = 1'b1;
|
|
|
|
assign m_axis_tready_pipe = m_axis_tready_out;
|
|
assign m_axis_tvalid_out = m_axis_tvalid_pipe;
|
|
|
|
assign m_axis_tdata_out = m_axis_tdata_pipe;
|
|
assign m_axis_tkeep_out = m_axis_tkeep_pipe;
|
|
assign m_axis_tstrb_out = m_axis_tstrb_pipe;
|
|
assign m_axis_tlast_out = m_axis_tlast_pipe;
|
|
assign m_axis_tid_out = m_axis_tid_pipe;
|
|
assign m_axis_tdest_out = m_axis_tdest_pipe;
|
|
assign m_axis_tuser_out = m_axis_tuser_pipe;
|
|
|
|
end else begin : output_fifo
|
|
|
|
// output datapath logic
|
|
logic [DATA_W-1:0] m_axis_tdata_reg = '0;
|
|
logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
|
|
logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
|
|
logic m_axis_tvalid_reg = 1'b0;
|
|
logic m_axis_tlast_reg = 1'b0;
|
|
logic [ID_W-1:0] m_axis_tid_reg = '0;
|
|
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
|
|
logic [USER_W-1:0] m_axis_tuser_reg = '0;
|
|
|
|
logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_wr_ptr_reg = 0;
|
|
logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_rd_ptr_reg = 0;
|
|
logic out_fifo_half_full_reg = 1'b0;
|
|
|
|
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_AW{1'b0}}});
|
|
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
|
|
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
logic [DATA_W-1:0] out_fifo_tdata[2**OUTPUT_FIFO_AW-1:0];
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
logic [KEEP_W-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_AW-1:0];
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
logic [KEEP_W-1:0] out_fifo_tstrb[2**OUTPUT_FIFO_AW-1:0];
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
logic out_fifo_tlast[2**OUTPUT_FIFO_AW-1:0];
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
logic [ID_W-1:0] out_fifo_tid[2**OUTPUT_FIFO_AW-1:0];
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
logic [DEST_W-1:0] out_fifo_tdest[2**OUTPUT_FIFO_AW-1:0];
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
logic [USER_W-1:0] out_fifo_tuser[2**OUTPUT_FIFO_AW-1:0];
|
|
|
|
assign pipe_ready = !out_fifo_half_full_reg;
|
|
|
|
assign m_axis_tready_pipe = 1'b1;
|
|
|
|
assign m_axis_tdata_out = m_axis_tdata_reg;
|
|
assign m_axis_tkeep_out = KEEP_EN ? m_axis_tkeep_reg : '1;
|
|
assign m_axis_tstrb_out = STRB_EN ? m_axis_tkeep_reg : m_axis_tkeep_out;
|
|
assign m_axis_tvalid_out = m_axis_tvalid_reg;
|
|
assign m_axis_tlast_out = LAST_EN ? m_axis_tlast_reg : 1'b1;
|
|
assign m_axis_tid_out = ID_EN ? m_axis_tid_reg : '0;
|
|
assign m_axis_tdest_out = DEST_EN ? m_axis_tdest_reg : '0;
|
|
assign m_axis_tuser_out = USER_EN ? m_axis_tuser_reg : '0;
|
|
|
|
always_ff @(posedge m_clk) begin
|
|
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready_out;
|
|
|
|
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_AW-1);
|
|
|
|
if (!out_fifo_full && m_axis_tvalid_pipe) begin
|
|
out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tdata_pipe;
|
|
out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tkeep_pipe;
|
|
out_fifo_tstrb[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tstrb_pipe;
|
|
out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tlast_pipe;
|
|
out_fifo_tid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tid_pipe;
|
|
out_fifo_tdest[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tdest_pipe;
|
|
out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tuser_pipe;
|
|
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
|
|
end
|
|
|
|
if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready_out)) begin
|
|
m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
|
|
m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
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m_axis_tstrb_reg <= out_fifo_tstrb[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
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m_axis_tvalid_reg <= 1'b1;
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m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
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m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
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m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
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m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
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out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
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end
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if (m_rst) begin
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out_fifo_wr_ptr_reg <= 0;
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out_fifo_rd_ptr_reg <= 0;
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m_axis_tvalid_reg <= 1'b0;
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end
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end
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end
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if (PAUSE_EN) begin : pause
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// Pause logic
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logic pause_reg = 1'b0;
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logic pause_frame_reg = 1'b0;
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logic s_pause_req_sync1_reg;
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logic s_pause_req_sync2_reg;
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logic s_pause_req_sync3_reg;
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logic s_pause_ack_sync1_reg;
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logic s_pause_ack_sync2_reg;
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logic s_pause_ack_sync3_reg;
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|
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always_ff @(posedge s_clk) begin
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s_pause_req_sync1_reg <= s_pause_req;
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s_pause_ack_sync2_reg <= s_pause_ack_sync1_reg;
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s_pause_ack_sync3_reg <= s_pause_ack_sync2_reg;
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end
|
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always_ff @(posedge m_clk) begin
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s_pause_req_sync2_reg <= s_pause_req_sync1_reg;
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s_pause_req_sync3_reg <= s_pause_req_sync2_reg;
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s_pause_ack_sync1_reg <= pause_reg;
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end
|
|
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assign m_axis_tready_out = m_axis.tready && !pause_reg;
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assign m_axis.tvalid = m_axis_tvalid_out && !pause_reg;
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|
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assign m_axis.tdata = m_axis_tdata_out;
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assign m_axis.tkeep = m_axis_tkeep_out;
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assign m_axis.tstrb = m_axis_tstrb_out;
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assign m_axis.tlast = m_axis_tlast_out;
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assign m_axis.tid = m_axis_tid_out;
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assign m_axis.tdest = m_axis_tdest_out;
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assign m_axis.tuser = m_axis_tuser_out;
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|
|
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assign s_pause_ack = s_pause_ack_sync3_reg;
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assign m_pause_ack = pause_reg;
|
|
|
|
always_ff @(posedge m_clk) begin
|
|
if (FRAME_PAUSE) begin
|
|
if (pause_reg) begin
|
|
// paused; update pause status
|
|
pause_reg <= m_pause_req || s_pause_req_sync3_reg;
|
|
end else if (m_axis_tvalid_out) begin
|
|
// frame transfer; set frame bit
|
|
pause_frame_reg <= 1'b1;
|
|
if (m_axis.tready && m_axis.tlast) begin
|
|
// end of frame; clear frame bit and update pause status
|
|
pause_frame_reg <= 1'b0;
|
|
pause_reg <= m_pause_req || s_pause_req_sync3_reg;
|
|
end
|
|
end else if (!pause_frame_reg) begin
|
|
// idle; update pause status
|
|
pause_reg <= m_pause_req || s_pause_req_sync3_reg;
|
|
end
|
|
end else begin
|
|
pause_reg <= m_pause_req || s_pause_req_sync3_reg;
|
|
end
|
|
|
|
if (m_rst) begin
|
|
pause_frame_reg <= 1'b0;
|
|
pause_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
end else begin
|
|
|
|
assign m_axis_tready_out = m_axis.tready;
|
|
assign m_axis.tvalid = m_axis_tvalid_out;
|
|
|
|
assign m_axis.tdata = m_axis_tdata_out;
|
|
assign m_axis.tkeep = m_axis_tkeep_out;
|
|
assign m_axis.tstrb = m_axis_tstrb_out;
|
|
assign m_axis.tlast = m_axis_tlast_out;
|
|
assign m_axis.tid = m_axis_tid_out;
|
|
assign m_axis.tdest = m_axis_tdest_out;
|
|
assign m_axis.tuser = m_axis_tuser_out;
|
|
|
|
assign s_pause_ack = 1'b0;
|
|
assign m_pause_ack = 1'b0;
|
|
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|