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22 lines
488 B
Tcl
22 lines
488 B
Tcl
# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# Generate bit file with different IODELAY settings without rebuilding the full project
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open_project fpga.xpr
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open_run impl_1
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# IDELAY from PHY chip (RGMII)
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set_property IDELAY_VALUE 0 [get_cells {phy_if.phy_rx_ctl_idelay phy_if.phy_rxd_idelay_bit[*].idelay_inst}]
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# MMCM phase (RGMII)
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set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]
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write_bitstream -force fpga.bit
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exit
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