mirror of
https://github.com/fpganinja/taxi.git
synced 2025-12-09 08:58:40 -08:00
454 lines
10 KiB
Systemverilog
454 lines
10 KiB
Systemverilog
// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA core logic
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*/
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module fpga_core #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter string VENDOR = "XILINX",
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// device family
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parameter string FAMILY = "kintex7",
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// Use 90 degree clock for RGMII transmit
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parameter logic USE_CLK90 = 1'b1,
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// BASE-T PHY type (GMII, RGMII, SGMII)
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parameter BASET_PHY_TYPE = "GMII",
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// Invert SFP data pins
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parameter logic SFP_INVERT = 1'b1
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)
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(
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/*
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* Clock: 125MHz
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* Synchronous reset
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*/
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input wire logic clk,
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input wire logic clk90,
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input wire logic rst,
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/*
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* GPIO
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*/
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input wire logic btnu,
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input wire logic btnl,
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input wire logic btnd,
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input wire logic btnr,
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input wire logic btnc,
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input wire logic [7:0] sw,
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output wire logic [7:0] led,
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/*
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* UART: 115200 bps, 8N1
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*/
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input wire logic uart_rxd,
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output wire logic uart_txd,
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output wire logic uart_rts,
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input wire logic uart_cts,
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/*
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* Ethernet: 1000BASE-X SFP
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*/
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input wire logic sfp_gmii_clk,
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input wire logic sfp_gmii_rst,
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input wire logic sfp_gmii_clk_en,
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input wire logic [7:0] sfp_gmii_rxd,
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input wire logic sfp_gmii_rx_dv,
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input wire logic sfp_gmii_rx_er,
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output wire logic [7:0] sfp_gmii_txd,
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output wire logic sfp_gmii_tx_en,
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output wire logic sfp_gmii_tx_er,
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output wire logic sfp_tx_disable_b,
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/*
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* Ethernet: 1000BASE-T
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*/
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input wire logic phy_sgmii_clk,
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input wire logic phy_sgmii_rst,
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input wire logic phy_sgmii_clk_en,
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input wire logic [7:0] phy_sgmii_rxd,
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input wire logic phy_sgmii_rx_dv,
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input wire logic phy_sgmii_rx_er,
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output wire logic [7:0] phy_sgmii_txd,
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output wire logic phy_sgmii_tx_en,
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output wire logic phy_sgmii_tx_er,
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input wire logic phy_rgmii_rx_clk,
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input wire logic [3:0] phy_rgmii_rxd,
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input wire logic phy_rgmii_rx_ctl,
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output wire logic phy_rgmii_tx_clk,
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output wire logic [3:0] phy_rgmii_txd,
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output wire logic phy_rgmii_tx_ctl,
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input wire logic phy_gmii_rx_clk,
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input wire logic [7:0] phy_gmii_rxd,
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input wire logic phy_gmii_rx_dv,
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input wire logic phy_gmii_rx_er,
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output wire logic phy_gmii_gtx_clk,
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input wire logic phy_gmii_tx_clk,
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output wire logic [7:0] phy_gmii_txd,
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output wire logic phy_gmii_tx_en,
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output wire logic phy_gmii_tx_er,
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output wire logic phy_reset_n,
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input wire logic phy_int_n
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);
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assign led = sw;
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// UART
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assign uart_rts = 0;
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taxi_axis_if #(.DATA_W(8)) axis_uart();
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taxi_uart
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uut (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4-Stream input (sink)
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*/
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.s_axis_tx(axis_uart),
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/*
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* AXI4-Stream output (source)
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*/
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.m_axis_rx(axis_uart),
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/*
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* UART interface
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*/
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.rxd(uart_rxd),
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.txd(uart_txd),
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/*
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* Status
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*/
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.tx_busy(),
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.rx_busy(),
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.rx_overrun_error(),
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.rx_frame_error(),
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/*
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* Configuration
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*/
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.prescale(16'(125000000/115200/8))
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);
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// BASE-T PHY
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assign phy_reset_n = !rst;
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taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth();
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taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
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if (BASET_PHY_TYPE == "GMII") begin : baset_mac_gmii
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taxi_eth_mac_1g_gmii_fifo #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.PADDING_EN(1),
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.MIN_FRAME_LEN(64),
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.TX_FIFO_DEPTH(16384),
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.TX_FRAME_FIFO(1),
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.RX_FIFO_DEPTH(16384),
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.RX_FRAME_FIFO(1)
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)
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eth_mac_inst (
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.gtx_clk(clk),
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.gtx_rst(rst),
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.logic_clk(clk),
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.logic_rst(rst),
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/*
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* Transmit interface (AXI stream)
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*/
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.s_axis_tx(axis_eth),
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.m_axis_tx_cpl(axis_tx_cpl),
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/*
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* Receive interface (AXI stream)
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*/
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.m_axis_rx(axis_eth),
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/*
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* GMII interface
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*/
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.gmii_rx_clk(phy_gmii_rx_clk),
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.gmii_rxd(phy_gmii_rxd),
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.gmii_rx_dv(phy_gmii_rx_dv),
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.gmii_rx_er(phy_gmii_rx_er),
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.gmii_tx_clk(phy_gmii_gtx_clk),
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.mii_tx_clk(phy_gmii_tx_clk),
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.gmii_txd(phy_gmii_txd),
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.gmii_tx_en(phy_gmii_tx_en),
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.gmii_tx_er(phy_gmii_tx_er),
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/*
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* Status
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*/
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.tx_error_underflow(),
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.tx_fifo_overflow(),
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.tx_fifo_bad_frame(),
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.tx_fifo_good_frame(),
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.rx_error_bad_frame(),
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.rx_error_bad_fcs(),
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.rx_fifo_overflow(),
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.rx_fifo_bad_frame(),
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.rx_fifo_good_frame(),
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.link_speed(),
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/*
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* Configuration
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*/
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.cfg_ifg(8'd12),
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.cfg_tx_enable(1'b1),
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.cfg_rx_enable(1'b1)
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);
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assign phy_sgmii_txd = '0;
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assign phy_sgmii_tx_en = 1'b0;
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assign phy_sgmii_tx_er = 1'b0;
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assign phy_rgmii_tx_clk = 1'b0;
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assign phy_rgmii_txd = '0;
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assign phy_rgmii_tx_ctl = 1'b0;
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end else if (BASET_PHY_TYPE == "RGMII") begin : baset_mac_rgmii
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taxi_eth_mac_1g_rgmii_fifo #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.USE_CLK90(USE_CLK90),
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.PADDING_EN(1),
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.MIN_FRAME_LEN(64),
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.TX_FIFO_DEPTH(16384),
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.TX_FRAME_FIFO(1),
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.RX_FIFO_DEPTH(16384),
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.RX_FRAME_FIFO(1)
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)
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eth_mac_inst (
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.gtx_clk(clk),
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.gtx_clk90(clk90),
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.gtx_rst(rst),
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.logic_clk(clk),
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.logic_rst(rst),
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/*
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* Transmit interface (AXI stream)
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*/
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.s_axis_tx(axis_eth),
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.m_axis_tx_cpl(axis_tx_cpl),
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/*
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* Receive interface (AXI stream)
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*/
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.m_axis_rx(axis_eth),
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/*
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* RGMII interface
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*/
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.rgmii_rx_clk(phy_rgmii_rx_clk),
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.rgmii_rxd(phy_rgmii_rxd),
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.rgmii_rx_ctl(phy_rgmii_rx_ctl),
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.rgmii_tx_clk(phy_rgmii_tx_clk),
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.rgmii_txd(phy_rgmii_txd),
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.rgmii_tx_ctl(phy_rgmii_tx_ctl),
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/*
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* Status
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*/
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.tx_error_underflow(),
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.tx_fifo_overflow(),
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.tx_fifo_bad_frame(),
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.tx_fifo_good_frame(),
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.rx_error_bad_frame(),
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.rx_error_bad_fcs(),
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.rx_fifo_overflow(),
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.rx_fifo_bad_frame(),
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.rx_fifo_good_frame(),
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.link_speed(),
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/*
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* Configuration
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*/
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.cfg_ifg(8'd12),
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.cfg_tx_enable(1'b1),
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.cfg_rx_enable(1'b1)
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);
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assign phy_gmii_gtx_clk = 1'b0;
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assign phy_gmii_txd = '0;
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assign phy_gmii_tx_en = 1'b0;
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assign phy_gmii_tx_er = 1'b0;
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assign phy_sgmii_txd = '0;
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assign phy_sgmii_tx_en = 1'b0;
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assign phy_sgmii_tx_er = 1'b0;
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end else if (BASET_PHY_TYPE == "SGMII") begin : baset_mac_sgmii
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taxi_eth_mac_1g_fifo #(
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.PADDING_EN(1),
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.MIN_FRAME_LEN(64),
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.TX_FIFO_DEPTH(16384),
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.TX_FRAME_FIFO(1),
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.RX_FIFO_DEPTH(16384),
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.RX_FRAME_FIFO(1)
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)
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eth_mac_inst (
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.rx_clk(phy_sgmii_clk),
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.rx_rst(phy_sgmii_rst),
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.tx_clk(phy_sgmii_clk),
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.tx_rst(phy_sgmii_rst),
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.logic_clk(clk),
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.logic_rst(rst),
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/*
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* Transmit interface (AXI stream)
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*/
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.s_axis_tx(axis_eth),
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.m_axis_tx_cpl(axis_tx_cpl),
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/*
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* Receive interface (AXI stream)
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*/
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.m_axis_rx(axis_eth),
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/*
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* GMII interface
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*/
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.gmii_rxd(phy_sgmii_rxd),
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.gmii_rx_dv(phy_sgmii_rx_dv),
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.gmii_rx_er(phy_sgmii_rx_er),
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.gmii_txd(phy_sgmii_txd),
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.gmii_tx_en(phy_sgmii_tx_en),
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.gmii_tx_er(phy_sgmii_tx_er),
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/*
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* Control
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*/
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.rx_clk_enable(phy_sgmii_clk_en),
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.tx_clk_enable(phy_sgmii_clk_en),
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.rx_mii_select(1'b0),
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.tx_mii_select(1'b0),
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/*
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* Status
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*/
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.tx_error_underflow(),
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.tx_fifo_overflow(),
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.tx_fifo_bad_frame(),
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.tx_fifo_good_frame(),
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.rx_error_bad_frame(),
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.rx_error_bad_fcs(),
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.rx_fifo_overflow(),
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.rx_fifo_bad_frame(),
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.rx_fifo_good_frame(),
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/*
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* Configuration
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*/
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.cfg_ifg(8'd12),
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.cfg_tx_enable(1'b1),
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.cfg_rx_enable(1'b1)
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);
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assign phy_gmii_gtx_clk = 1'b0;
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assign phy_gmii_txd = '0;
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assign phy_gmii_tx_en = 1'b0;
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assign phy_gmii_tx_er = 1'b0;
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assign phy_rgmii_tx_clk = 1'b0;
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assign phy_rgmii_txd = '0;
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assign phy_rgmii_tx_ctl = 1'b0;
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end
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// SFP+
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assign sfp_tx_disable_b = 1'b1;
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taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_sfp_eth();
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taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl();
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taxi_eth_mac_1g_fifo #(
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.PADDING_EN(1),
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.MIN_FRAME_LEN(64),
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.TX_FIFO_DEPTH(16384),
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.TX_FRAME_FIFO(1),
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.RX_FIFO_DEPTH(16384),
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.RX_FRAME_FIFO(1)
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)
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eth_mac_inst (
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.rx_clk(sfp_gmii_clk),
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.rx_rst(sfp_gmii_rst),
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.tx_clk(sfp_gmii_clk),
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.tx_rst(sfp_gmii_rst),
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.logic_clk(clk),
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.logic_rst(rst),
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/*
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* Transmit interface (AXI stream)
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*/
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.s_axis_tx(axis_sfp_eth),
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.m_axis_tx_cpl(axis_sfp_tx_cpl),
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/*
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* Receive interface (AXI stream)
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*/
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.m_axis_rx(axis_sfp_eth),
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/*
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* GMII interface
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*/
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.gmii_rxd(sfp_gmii_rxd),
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.gmii_rx_dv(sfp_gmii_rx_dv),
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.gmii_rx_er(sfp_gmii_rx_er),
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.gmii_txd(sfp_gmii_txd),
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.gmii_tx_en(sfp_gmii_tx_en),
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.gmii_tx_er(sfp_gmii_tx_er),
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/*
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* Control
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*/
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.rx_clk_enable(sfp_gmii_clk_en),
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.tx_clk_enable(sfp_gmii_clk_en),
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.rx_mii_select(1'b0),
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.tx_mii_select(1'b0),
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/*
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* Status
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*/
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.tx_error_underflow(),
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.tx_fifo_overflow(),
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.tx_fifo_bad_frame(),
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.tx_fifo_good_frame(),
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.rx_error_bad_frame(),
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.rx_error_bad_fcs(),
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.rx_fifo_overflow(),
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.rx_fifo_bad_frame(),
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.rx_fifo_good_frame(),
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/*
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* Configuration
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*/
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.cfg_ifg(8'd12),
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.cfg_tx_enable(1'b1),
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.cfg_rx_enable(1'b1)
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);
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endmodule
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`resetall
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