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https://github.com/fpganinja/taxi.git
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108 lines
2.1 KiB
Systemverilog
108 lines
2.1 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2016-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Generic source synchronous DDR input
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*/
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module taxi_ssio_ddr_in_diff #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter string VENDOR = "XILINX",
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// device family
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parameter string FAMILY = "virtex7",
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// Width of register in bits
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parameter WIDTH = 1
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)
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(
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input wire logic input_clk_p,
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input wire logic input_clk_n,
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input wire logic [WIDTH-1:0] input_d_p,
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input wire logic [WIDTH-1:0] input_d_n,
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output wire logic output_clk,
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output wire logic [WIDTH-1:0] output_q1,
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output wire logic [WIDTH-1:0] output_q2
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);
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wire input_clk;
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wire [WIDTH-1:0] input_d;
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if (!SIM && VENDOR == "XILINX") begin
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// Xilinx/AMD device support
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IBUFDS
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clk_ibufds_inst (
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.I(input_clk_p),
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.IB(input_clk_n),
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.O(input_clk)
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);
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for (genvar n = 0; n < WIDTH; n = n + 1) begin
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IBUFDS
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data_ibufds_inst (
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.I(input_d_p[n]),
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.IB(input_d_n[n]),
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.O(input_d[n])
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);
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end
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end else if (!SIM && VENDOR == "ALTERA") begin
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// Altera/Intel/Altera device support
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ALT_INBUF_DIFF
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clk_inbuf_diff_inst (
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.i(input_clk_p),
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.ibar(input_clk_n),
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.o(input_clk)
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);
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for (genvar n = 0; n < WIDTH; n = n + 1) begin
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ALT_INBUF_DIFF
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data_inbuf_diff_inst (
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.i(input_d_p[n]),
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.ibar(input_d_n[n]),
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.o(input_d[n])
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);
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end
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end else begin
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// generic/simulation implementation (no vendor primitives)
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assign input_clk = input_clk_p;
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assign input_d = input_d_p;
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end
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taxi_ssio_ddr_in #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.WIDTH(WIDTH)
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)
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ssio_ddr_in_inst(
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.input_clk(input_clk),
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.input_d(input_d),
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.output_clk(output_clk),
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.output_q1(output_q1),
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.output_q2(output_q2)
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);
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endmodule
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`resetall
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