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https://github.com/fpganinja/taxi.git
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114 lines
2.4 KiB
Systemverilog
114 lines
2.4 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2016-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Generic source synchronous DDR output
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*/
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module taxi_ssio_ddr_out_diff #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter string VENDOR = "XILINX",
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// device family
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parameter string FAMILY = "virtex7",
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// Use 90 degree clock for transmit
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parameter logic USE_CLK90 = 1'b1,
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// Width of register in bits
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parameter WIDTH = 1
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)
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(
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input wire logic clk,
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input wire logic clk90,
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input wire logic [WIDTH-1:0] input_d1,
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input wire logic [WIDTH-1:0] input_d2,
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output wire logic output_clk_p,
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output wire logic output_clk_n,
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output wire logic [WIDTH-1:0] output_q_p,
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output wire logic [WIDTH-1:0] output_q_n
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);
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wire output_clk;
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wire [WIDTH-1:0] output_q;
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taxi_ssio_ddr_out #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.USE_CLK90(USE_CLK90),
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.WIDTH(WIDTH)
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)
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ssio_ddr_out_inst(
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.clk(clk),
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.clk90(clk90),
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.input_d1(input_d1),
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.input_d2(input_d2),
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.output_clk(output_clk),
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.output_q(output_q)
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);
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if (!SIM && VENDOR == "XILINX") begin
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// Xilinx/AMD device support
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OBUFDS
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clk_obufds_inst (
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.I(output_clk),
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.O(output_clk_p),
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.OB(output_clk_n)
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);
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for (genvar n = 0; n < WIDTH; n = n + 1) begin
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OBUFDS
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data_obufds_inst (
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.I(output_q[n]),
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.O(output_q_p[n]),
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.OB(output_q_n[n])
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);
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end
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end else if (!SIM && VENDOR == "ALTERA") begin
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// Altera/Intel/Altera device support
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ALT_OUTBUF_DIFF
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clk_outbuf_diff_inst (
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.i(output_clk),
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.o(output_clk_p),
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.obar(output_clk_n)
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);
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for (genvar n = 0; n < WIDTH; n = n + 1) begin
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ALT_OUTBUF_DIFF
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data_outbuf_diff_inst (
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.i(output_q[n]),
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.o(output_q_p[n]),
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.obar(output_q_n[n])
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);
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end
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end else begin
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// generic/simulation implementation (no vendor primitives)
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assign output_clk_p = output_clk;
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assign output_clk_n = ~output_clk;
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assign output_q_p = output_q;
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assign output_q_n = ~output_q;
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end
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endmodule
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`resetall
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