mirror of
https://github.com/fpganinja/taxi.git
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135 lines
2.8 KiB
Systemverilog
135 lines
2.8 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2016-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Generic source synchronous SDR input
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*/
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module taxi_ssio_sdr_in #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter string VENDOR = "XILINX",
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// device family
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parameter string FAMILY = "virtex7",
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// Width of register in bits
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parameter WIDTH = 1
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)
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(
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input wire logic input_clk,
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input wire logic [WIDTH-1:0] input_d,
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output wire logic output_clk,
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output wire logic [WIDTH-1:0] output_q
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);
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wire clk_int;
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wire clk_io;
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if (!SIM && VENDOR == "XILINX") begin
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// Xilinx/AMD device support
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if (FAMILY == "virtex6" || FAMILY == "virtex7" || FAMILY == "kintex7" || FAMILY == "artix7") begin
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// BUFIO + BUFR
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// virtex6, virtex7, kintex7, artix7, zynq
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assign clk_int = input_clk;
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// pass through RX clock to input buffers
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BUFIO
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clk_bufio (
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.I(clk_int),
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.O(clk_io)
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);
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// pass through RX clock to logic
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BUFR #(
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.BUFR_DIVIDE("BYPASS")
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)
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clk_bufr (
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.I(clk_int),
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.O(output_clk),
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.CE(1'b1),
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.CLR(1'b0)
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);
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end else if (FAMILY == "spartan6") begin
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// BUFIO2 + BUFG
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// spartan6
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// pass through RX clock to input buffers
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BUFIO2 #(
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.DIVIDE(1),
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.DIVIDE_BYPASS("TRUE"),
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.I_INVERT("FALSE"),
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.USE_DOUBLER("FALSE")
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)
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clk_bufio (
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.I(input_clk),
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.DIVCLK(clk_int),
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.IOCLK(clk_io),
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.SERDESSTROBE()
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);
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// pass through RX clock to MAC
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BUFG
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clk_bufg (
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.I(clk_int),
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.O(output_clk)
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);
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end else begin
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// BUFG only
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// virtexu, kintexu, virtexuplus, virtexuplusHBM, virtexuplus58g, kintexuplus, zynquplus, zynquplusRFSOC
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// buffer RX clock
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BUFG
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clk_bufg (
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.I(input_clk),
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.O(clk_int)
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);
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// pass through RX clock to logic and input buffers
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assign clk_io = clk_int;
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assign output_clk = clk_int;
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end
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end else begin
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// generic/simulation implementation (no vendor primitives)
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// pass through RX clock to input buffers
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assign clk_io = input_clk;
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// pass through RX clock to logic
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assign clk_int = input_clk;
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assign output_clk = clk_int;
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end
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(* IOB = "TRUE" *)
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logic [WIDTH-1:0] output_q_reg = '0;
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assign output_q = output_q_reg;
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always_ff @(posedge clk_io) begin
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output_q_reg <= input_d;
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end
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endmodule
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`resetall
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