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63 lines
1.0 KiB
Systemverilog
63 lines
1.0 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2016-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Generic source synchronous SDR output
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*/
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module taxi_ssio_sdr_out #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter string VENDOR = "XILINX",
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// device family
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parameter string FAMILY = "virtex7",
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// Width of register in bits
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parameter WIDTH = 1
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)
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(
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input wire logic clk,
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input wire logic [WIDTH-1:0] input_d,
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output wire logic output_clk,
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output wire logic [WIDTH-1:0] output_q
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);
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taxi_oddr #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.WIDTH(1)
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)
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clk_oddr_inst (
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.clk(clk),
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.d1(1'b0),
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.d2(1'b1),
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.q(output_clk)
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);
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(* IOB = "TRUE" *)
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logic [WIDTH-1:0] output_q_reg = '0;
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assign output_q = output_q_reg;
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always_ff @(posedge clk) begin
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output_q_reg <= input_d;
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end
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endmodule
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`resetall
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