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79 lines
1.1 KiB
Systemverilog
79 lines
1.1 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* I2C master testbench
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*/
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module test_taxi_i2c_master
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();
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logic clk;
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logic rst;
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taxi_axis_if #(.DATA_W(12), .KEEP_W(1)) s_axis_cmd();
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taxi_axis_if #(.DATA_W(8)) s_axis_data();
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taxi_axis_if #(.DATA_W(8)) m_axis_data();
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logic scl_i;
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logic scl_o;
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logic sda_i;
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logic sda_o;
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logic busy;
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logic bus_control;
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logic bus_active;
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logic missed_ack;
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logic [15:0] prescale;
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logic stop_on_idle;
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taxi_i2c_master
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uut (
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.clk(clk),
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.rst(rst),
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/*
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* Host interface
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*/
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.s_axis_cmd(s_axis_cmd),
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.s_axis_data(s_axis_data),
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.m_axis_data(m_axis_data),
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/*
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* I2C interface
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*/
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.scl_i(scl_i),
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.scl_o(scl_o),
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.sda_i(sda_i),
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.sda_o(sda_o),
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/*
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* Status
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*/
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.busy(busy),
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.bus_control(bus_control),
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.bus_active(bus_active),
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.missed_ack(missed_ack),
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/*
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* Configuration
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*/
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.prescale(prescale),
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.stop_on_idle(stop_on_idle)
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);
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endmodule
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`resetall
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