mirror of
https://github.com/fpganinja/taxi.git
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620 lines
17 KiB
Systemverilog
620 lines
17 KiB
Systemverilog
// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA core logic
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*/
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module fpga_core #
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(
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parameter logic SIM = 1'b0,
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parameter string VENDOR = "XILINX",
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parameter string FAMILY = "virtexuplus"
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)
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(
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/*
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* Clock: 125 MHz
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* Synchronous reset
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*/
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input wire logic clk_125mhz,
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input wire logic rst_125mhz,
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/*
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* GPIO
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*/
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output wire logic led,
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/*
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* UART: 3000000 bps, 8N1
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*/
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input wire logic uart_rxd,
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output wire logic uart_txd,
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/*
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* I2C
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*/
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input wire logic eeprom_i2c_scl_i,
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output wire logic eeprom_i2c_scl_o,
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input wire logic eeprom_i2c_sda_i,
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output wire logic eeprom_i2c_sda_o,
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/*
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* Ethernet: QSFP28
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*/
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output wire logic [3:0] qsfp0_tx_p,
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output wire logic [3:0] qsfp0_tx_n,
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input wire logic [3:0] qsfp0_rx_p,
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input wire logic [3:0] qsfp0_rx_n,
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input wire logic qsfp0_mgt_refclk_b0_p,
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input wire logic qsfp0_mgt_refclk_b0_n,
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output wire logic qsfp0_resetl,
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input wire logic qsfp0_modprsl,
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input wire logic qsfp0_intl,
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output wire logic qsfp0_lpmode,
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input wire logic qsfp0_i2c_scl_i,
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output wire logic qsfp0_i2c_scl_o,
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input wire logic qsfp0_i2c_sda_i,
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output wire logic qsfp0_i2c_sda_o,
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output wire logic [3:0] qsfp1_tx_p,
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output wire logic [3:0] qsfp1_tx_n,
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input wire logic [3:0] qsfp1_rx_p,
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input wire logic [3:0] qsfp1_rx_n,
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input wire logic qsfp1_mgt_refclk_b0_p,
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input wire logic qsfp1_mgt_refclk_b0_n,
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output wire logic qsfp1_resetl,
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input wire logic qsfp1_modprsl,
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input wire logic qsfp1_intl,
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output wire logic qsfp1_lpmode,
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input wire logic qsfp1_i2c_scl_i,
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output wire logic qsfp1_i2c_scl_o,
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input wire logic qsfp1_i2c_sda_i,
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output wire logic qsfp1_i2c_sda_o,
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output wire logic [3:0] qsfp2_tx_p,
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output wire logic [3:0] qsfp2_tx_n,
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input wire logic [3:0] qsfp2_rx_p,
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input wire logic [3:0] qsfp2_rx_n,
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input wire logic qsfp2_mgt_refclk_b0_p,
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input wire logic qsfp2_mgt_refclk_b0_n,
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output wire logic qsfp2_resetl,
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input wire logic qsfp2_modprsl,
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input wire logic qsfp2_intl,
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output wire logic qsfp2_lpmode,
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input wire logic qsfp2_i2c_scl_i,
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output wire logic qsfp2_i2c_scl_o,
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input wire logic qsfp2_i2c_sda_i,
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output wire logic qsfp2_i2c_sda_o,
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output wire logic [3:0] qsfp3_tx_p,
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output wire logic [3:0] qsfp3_tx_n,
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input wire logic [3:0] qsfp3_rx_p,
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input wire logic [3:0] qsfp3_rx_n,
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input wire logic qsfp3_mgt_refclk_b0_p,
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input wire logic qsfp3_mgt_refclk_b0_n,
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output wire logic qsfp3_resetl,
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input wire logic qsfp3_modprsl,
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input wire logic qsfp3_intl,
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output wire logic qsfp3_lpmode,
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input wire logic qsfp3_i2c_scl_i,
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output wire logic qsfp3_i2c_scl_o,
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input wire logic qsfp3_i2c_sda_i,
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output wire logic qsfp3_i2c_sda_o
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);
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assign eeprom_i2c_scl_o = 1'b1;
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assign eeprom_i2c_sda_o = 1'b1;
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assign qsfp0_i2c_scl_o = 1'b1;
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assign qsfp0_i2c_sda_o = 1'b1;
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assign qsfp1_i2c_scl_o = 1'b1;
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assign qsfp1_i2c_sda_o = 1'b1;
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assign qsfp2_i2c_scl_o = 1'b1;
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assign qsfp2_i2c_sda_o = 1'b1;
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assign qsfp3_i2c_scl_o = 1'b1;
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assign qsfp3_i2c_sda_o = 1'b1;
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// XFCP
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taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
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taxi_xfcp_if_uart #(
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.TX_FIFO_DEPTH(512),
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.RX_FIFO_DEPTH(512)
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)
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xfcp_if_uart_inst (
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.clk(clk_125mhz),
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.rst(rst_125mhz),
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/*
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* UART interface
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*/
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.uart_rxd(uart_rxd),
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.uart_txd(uart_txd),
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/*
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* XFCP downstream interface
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*/
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.xfcp_dsp_ds(xfcp_ds),
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.xfcp_dsp_us(xfcp_us),
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/*
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* Configuration
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*/
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.prescale(16'(125000000/3000000))
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);
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taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[1](), xfcp_sw_us[1]();
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taxi_xfcp_switch #(
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.XFCP_ID_STR(FAMILY == "virtexuplus" ? "XUPP3R" : "XUSP3S"),
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.XFCP_EXT_ID(0),
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.XFCP_EXT_ID_STR("Taxi example"),
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.PORTS($size(xfcp_sw_us))
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)
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xfcp_sw_inst (
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.clk(clk_125mhz),
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.rst(rst_125mhz),
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/*
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* XFCP upstream port
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*/
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.xfcp_usp_ds(xfcp_ds),
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.xfcp_usp_us(xfcp_us),
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/*
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* XFCP downstream ports
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*/
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.xfcp_dsp_ds(xfcp_sw_ds),
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.xfcp_dsp_us(xfcp_sw_us)
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);
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taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_stat();
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taxi_xfcp_mod_stats #(
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.XFCP_ID_STR("Statistics"),
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.XFCP_EXT_ID(0),
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.XFCP_EXT_ID_STR(""),
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.STAT_COUNT_W(64),
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.STAT_PIPELINE(2)
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)
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xfcp_stats_inst (
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.clk(clk_125mhz),
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.rst(rst_125mhz),
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/*
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* XFCP upstream port
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*/
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.xfcp_usp_ds(xfcp_sw_ds[0]),
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.xfcp_usp_us(xfcp_sw_us[0]),
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/*
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* Statistics increment input
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*/
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.s_axis_stat(axis_stat)
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);
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taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[4]();
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taxi_axis_arb_mux #(
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.S_COUNT($size(axis_eth_stat)),
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.UPDATE_TID(1'b0),
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.ARB_ROUND_ROBIN(1'b1),
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.ARB_LSB_HIGH_PRIO(1'b0)
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)
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stat_mux_inst (
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.clk(clk_125mhz),
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.rst(rst_125mhz),
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/*
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* AXI4-Stream inputs (sink)
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*/
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.s_axis(axis_eth_stat),
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/*
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* AXI4-Stream output (source)
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*/
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.m_axis(axis_stat)
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);
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// QSFP28
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assign qsfp0_resetl = 1'b1;
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assign qsfp0_lpmode = 1'b0;
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assign qsfp1_resetl = 1'b1;
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assign qsfp1_lpmode = 1'b0;
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assign qsfp2_resetl = 1'b1;
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assign qsfp2_lpmode = 1'b0;
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assign qsfp3_resetl = 1'b1;
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assign qsfp3_lpmode = 1'b0;
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localparam GTY_QUAD_CNT = 4;
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localparam GTY_CNT = GTY_QUAD_CNT*4;
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localparam GTY_CLK_CNT = GTY_QUAD_CNT;
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wire [GTY_CNT-1:0] eth_gty_tx_p;
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wire [GTY_CNT-1:0] eth_gty_tx_n;
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wire [GTY_CNT-1:0] eth_gty_rx_p = {qsfp3_rx_p, qsfp2_rx_p, qsfp1_rx_p, qsfp0_rx_p};
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wire [GTY_CNT-1:0] eth_gty_rx_n = {qsfp3_rx_n, qsfp2_rx_n, qsfp1_rx_n, qsfp0_rx_n};
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wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_p = {qsfp3_mgt_refclk_b0_p, qsfp2_mgt_refclk_b0_p, qsfp1_mgt_refclk_b0_p, qsfp0_mgt_refclk_b0_p};
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wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_n = {qsfp3_mgt_refclk_b0_n, qsfp2_mgt_refclk_b0_n, qsfp1_mgt_refclk_b0_n, qsfp0_mgt_refclk_b0_n};
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assign qsfp0_tx_p = eth_gty_tx_p[3:0];
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assign qsfp0_tx_n = eth_gty_tx_n[3:0];
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assign qsfp1_tx_p = eth_gty_tx_p[7:4];
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assign qsfp1_tx_n = eth_gty_tx_n[7:4];
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assign qsfp2_tx_p = eth_gty_tx_p[11:8];
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assign qsfp2_tx_n = eth_gty_tx_n[11:8];
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assign qsfp3_tx_p = eth_gty_tx_p[15:12];
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assign qsfp3_tx_n = eth_gty_tx_n[15:12];
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wire [GTY_CNT-1:0] eth_gty_tx_clk;
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wire [GTY_CNT-1:0] eth_gty_tx_rst;
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taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
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taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
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wire [GTY_CNT-1:0] eth_gty_rx_clk;
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wire [GTY_CNT-1:0] eth_gty_rx_rst;
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taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
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wire [GTY_CNT-1:0] eth_gty_rx_status;
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wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood;
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wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk;
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wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_bufg;
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wire [GTY_CLK_CNT-1:0] eth_gty_rst;
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for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
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wire eth_gty_mgt_refclk_int;
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if (SIM) begin
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assign eth_gty_mgt_refclk[n] = eth_gty_mgt_refclk_p[n];
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assign eth_gty_mgt_refclk_int = eth_gty_mgt_refclk_p[n];
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assign eth_gty_mgt_refclk_bufg[n] = eth_gty_mgt_refclk_int;
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end else begin
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if (FAMILY == "virtexuplus") begin
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IBUFDS_GTE4 ibufds_gte4_eth_gty_mgt_refclk_inst (
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.I (eth_gty_mgt_refclk_p[n]),
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.IB (eth_gty_mgt_refclk_n[n]),
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.CEB (1'b0),
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.O (eth_gty_mgt_refclk[n]),
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.ODIV2 (eth_gty_mgt_refclk_int)
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);
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end else begin
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IBUFDS_GTE3 ibufds_gte4_eth_gty_mgt_refclk_inst (
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.I (eth_gty_mgt_refclk_p[n]),
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.IB (eth_gty_mgt_refclk_n[n]),
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.CEB (1'b0),
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.O (eth_gty_mgt_refclk[n]),
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.ODIV2 (eth_gty_mgt_refclk_int)
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);
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end
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BUFG_GT bufg_gt_eth_gty_mgt_refclk_inst (
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.CE (ð_gty_gtpowergood),
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.CEMASK (1'b1),
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.CLR (1'b0),
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.CLRMASK (1'b1),
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.DIV (3'd0),
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.I (eth_gty_mgt_refclk_int),
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.O (eth_gty_mgt_refclk_bufg[n])
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);
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end
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taxi_sync_reset #(
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.N(4)
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)
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qsfp_sync_reset_inst (
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.clk(eth_gty_mgt_refclk_bufg[n]),
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.rst(rst_125mhz),
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.out(eth_gty_rst[n])
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);
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end
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localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP0[4] = '{"QSFP0.1", "QSFP0.2", "QSFP0.3", "QSFP0.4"};
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localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3", "QSFP1.4"};
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localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3", "QSFP2.4"};
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localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP3[4] = '{"QSFP3.1", "QSFP3.2", "QSFP3.3", "QSFP3.4"};
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for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
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localparam CNT = 4;
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taxi_eth_mac_25g_us #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.CNT(4),
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// GT type
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.GT_TYPE("GTY"),
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// PHY parameters
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.PADDING_EN(1'b1),
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.DIC_EN(1'b1),
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.MIN_FRAME_LEN(64),
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.PTP_TS_EN(1'b0),
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.PTP_TS_FMT_TOD(1'b1),
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.PTP_TS_W(96),
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.PRBS31_EN(1'b0),
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.TX_SERDES_PIPELINE(1),
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.RX_SERDES_PIPELINE(1),
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.COUNT_125US(125000/6.4),
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.STAT_EN(1),
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.STAT_TX_LEVEL(1),
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.STAT_RX_LEVEL(1),
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.STAT_ID_BASE(n*CNT*(16+16)),
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.STAT_UPDATE_PERIOD(1024),
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.STAT_STR_EN(1),
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.STAT_PREFIX_STR(n == 0 ? STAT_PREFIX_STR_QSFP0 :
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n == 1 ? STAT_PREFIX_STR_QSFP1 :
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n == 2 ? STAT_PREFIX_STR_QSFP2 : STAT_PREFIX_STR_QSFP3)
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)
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mac_inst (
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.xcvr_ctrl_clk(clk_125mhz),
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.xcvr_ctrl_rst(eth_gty_rst[n]),
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/*
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* Common
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*/
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.xcvr_gtpowergood_out(eth_gty_gtpowergood[n]),
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.xcvr_gtrefclk00_in(eth_gty_mgt_refclk[n]),
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.xcvr_qpll0lock_out(),
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.xcvr_qpll0clk_out(),
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.xcvr_qpll0refclk_out(),
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/*
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* Serial data
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*/
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.xcvr_txp(eth_gty_tx_p[n*CNT +: CNT]),
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.xcvr_txn(eth_gty_tx_n[n*CNT +: CNT]),
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.xcvr_rxp(eth_gty_rx_p[n*CNT +: CNT]),
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.xcvr_rxn(eth_gty_rx_n[n*CNT +: CNT]),
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/*
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* MAC clocks
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*/
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.rx_clk(eth_gty_rx_clk[n*CNT +: CNT]),
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.rx_rst_in('0),
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.rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]),
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.tx_clk(eth_gty_tx_clk[n*CNT +: CNT]),
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.tx_rst_in('0),
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.tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]),
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.ptp_sample_clk('0),
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/*
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* Transmit interface (AXI stream)
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*/
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.s_axis_tx(eth_gty_axis_tx[n*CNT +: CNT]),
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.m_axis_tx_cpl(eth_gty_axis_tx_cpl[n*CNT +: CNT]),
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/*
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* Receive interface (AXI stream)
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*/
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.m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]),
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/*
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* PTP clock
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*/
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.tx_ptp_ts('{CNT{'0}}),
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.tx_ptp_ts_step('0),
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.rx_ptp_ts('{CNT{'0}}),
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.rx_ptp_ts_step('0),
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/*
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* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
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*/
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.tx_lfc_req('0),
|
|
.tx_lfc_resend('0),
|
|
.rx_lfc_en('0),
|
|
.rx_lfc_req(),
|
|
.rx_lfc_ack('0),
|
|
|
|
/*
|
|
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
|
*/
|
|
.tx_pfc_req('{CNT{'0}}),
|
|
.tx_pfc_resend('0),
|
|
.rx_pfc_en('{CNT{'0}}),
|
|
.rx_pfc_req(),
|
|
.rx_pfc_ack('{CNT{'0}}),
|
|
|
|
/*
|
|
* Pause interface
|
|
*/
|
|
.tx_lfc_pause_en('0),
|
|
.tx_pause_req('0),
|
|
.tx_pause_ack(),
|
|
|
|
/*
|
|
* Statistics
|
|
*/
|
|
.stat_clk(clk_125mhz),
|
|
.stat_rst(rst_125mhz),
|
|
.m_axis_stat(axis_eth_stat[n]),
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
.tx_start_packet(),
|
|
.stat_tx_byte(),
|
|
.stat_tx_pkt_len(),
|
|
.stat_tx_pkt_ucast(),
|
|
.stat_tx_pkt_mcast(),
|
|
.stat_tx_pkt_bcast(),
|
|
.stat_tx_pkt_vlan(),
|
|
.stat_tx_pkt_good(),
|
|
.stat_tx_pkt_bad(),
|
|
.stat_tx_err_oversize(),
|
|
.stat_tx_err_user(),
|
|
.stat_tx_err_underflow(),
|
|
.rx_start_packet(),
|
|
.rx_error_count(),
|
|
.rx_block_lock(),
|
|
.rx_high_ber(),
|
|
.rx_status(eth_gty_rx_status[n*CNT +: CNT]),
|
|
.stat_rx_byte(),
|
|
.stat_rx_pkt_len(),
|
|
.stat_rx_pkt_fragment(),
|
|
.stat_rx_pkt_jabber(),
|
|
.stat_rx_pkt_ucast(),
|
|
.stat_rx_pkt_mcast(),
|
|
.stat_rx_pkt_bcast(),
|
|
.stat_rx_pkt_vlan(),
|
|
.stat_rx_pkt_good(),
|
|
.stat_rx_pkt_bad(),
|
|
.stat_rx_err_oversize(),
|
|
.stat_rx_err_bad_fcs(),
|
|
.stat_rx_err_bad_block(),
|
|
.stat_rx_err_framing(),
|
|
.stat_rx_err_preamble(),
|
|
.stat_rx_fifo_drop('0),
|
|
.stat_tx_mcf(),
|
|
.stat_rx_mcf(),
|
|
.stat_tx_lfc_pkt(),
|
|
.stat_tx_lfc_xon(),
|
|
.stat_tx_lfc_xoff(),
|
|
.stat_tx_lfc_paused(),
|
|
.stat_tx_pfc_pkt(),
|
|
.stat_tx_pfc_xon(),
|
|
.stat_tx_pfc_xoff(),
|
|
.stat_tx_pfc_paused(),
|
|
.stat_rx_lfc_pkt(),
|
|
.stat_rx_lfc_xon(),
|
|
.stat_rx_lfc_xoff(),
|
|
.stat_rx_lfc_paused(),
|
|
.stat_rx_pfc_pkt(),
|
|
.stat_rx_pfc_xon(),
|
|
.stat_rx_pfc_xoff(),
|
|
.stat_rx_pfc_paused(),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.cfg_tx_max_pkt_len('{CNT{16'd9218}}),
|
|
.cfg_tx_ifg('{CNT{8'd12}}),
|
|
.cfg_tx_enable('1),
|
|
.cfg_rx_max_pkt_len('{CNT{16'd9218}}),
|
|
.cfg_rx_enable('1),
|
|
.cfg_tx_prbs31_enable('0),
|
|
.cfg_rx_prbs31_enable('0),
|
|
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
|
|
.cfg_mcf_rx_check_eth_dst_mcast('1),
|
|
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
|
|
.cfg_mcf_rx_check_eth_dst_ucast('0),
|
|
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
|
|
.cfg_mcf_rx_check_eth_src('0),
|
|
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
|
|
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
|
|
.cfg_mcf_rx_check_opcode_lfc('1),
|
|
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
|
|
.cfg_mcf_rx_check_opcode_pfc('1),
|
|
.cfg_mcf_rx_forward('0),
|
|
.cfg_mcf_rx_enable('0),
|
|
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
|
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
|
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
|
|
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
|
|
.cfg_tx_lfc_en('0),
|
|
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
|
|
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
|
|
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
|
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
|
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
|
|
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
|
|
.cfg_tx_pfc_en('0),
|
|
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
|
|
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
|
|
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
|
|
.cfg_rx_lfc_en('0),
|
|
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
|
|
.cfg_rx_pfc_en('0)
|
|
);
|
|
|
|
end
|
|
|
|
for (genvar n = 0; n < GTY_CNT; n = n + 1) begin : qsfp_ch
|
|
|
|
taxi_axis_async_fifo #(
|
|
.DEPTH(16384),
|
|
.RAM_PIPELINE(2),
|
|
.FRAME_FIFO(1),
|
|
.USER_BAD_FRAME_VALUE(1'b1),
|
|
.USER_BAD_FRAME_MASK(1'b1),
|
|
.DROP_OVERSIZE_FRAME(1),
|
|
.DROP_BAD_FRAME(1),
|
|
.DROP_WHEN_FULL(1)
|
|
)
|
|
ch_fifo (
|
|
/*
|
|
* AXI4-Stream input (sink)
|
|
*/
|
|
.s_clk(eth_gty_rx_clk[n]),
|
|
.s_rst(eth_gty_rx_rst[n]),
|
|
.s_axis(eth_gty_axis_rx[n]),
|
|
|
|
/*
|
|
* AXI4-Stream output (source)
|
|
*/
|
|
.m_clk(eth_gty_tx_clk[n]),
|
|
.m_rst(eth_gty_tx_rst[n]),
|
|
.m_axis(eth_gty_axis_tx[n]),
|
|
|
|
/*
|
|
* Pause
|
|
*/
|
|
.s_pause_req(1'b0),
|
|
.s_pause_ack(),
|
|
.m_pause_req(1'b0),
|
|
.m_pause_ack(),
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
.s_status_depth(),
|
|
.s_status_depth_commit(),
|
|
.s_status_overflow(),
|
|
.s_status_bad_frame(),
|
|
.s_status_good_frame(),
|
|
.m_status_depth(),
|
|
.m_status_depth_commit(),
|
|
.m_status_overflow(),
|
|
.m_status_bad_frame(),
|
|
.m_status_good_frame()
|
|
);
|
|
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|