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81 lines
2.1 KiB
Systemverilog
81 lines
2.1 KiB
Systemverilog
// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 tie (write)
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*/
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module taxi_axi_tie_wr
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(
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/*
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* AXI4 slave interface
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*/
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taxi_axi_if.wr_slv s_axi_wr,
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/*
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* AXI4 master interface
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*/
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taxi_axi_if.wr_mst m_axi_wr
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);
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// extract parameters
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localparam DATA_W = s_axi_wr.DATA_W;
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localparam ADDR_W = s_axi_wr.ADDR_W;
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localparam STRB_W = s_axi_wr.STRB_W;
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localparam ID_W = s_axi_wr.ID_W;
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localparam logic AWUSER_EN = s_axi_wr.AWUSER_EN && m_axi_wr.AWUSER_EN;
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localparam AWUSER_W = s_axi_wr.AWUSER_W;
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localparam logic WUSER_EN = s_axi_wr.WUSER_EN && m_axi_wr.WUSER_EN;
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localparam WUSER_W = s_axi_wr.WUSER_W;
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localparam logic BUSER_EN = s_axi_wr.BUSER_EN && m_axi_wr.BUSER_EN;
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localparam BUSER_W = s_axi_wr.BUSER_W;
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// check configuration
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if (m_axi_wr.DATA_W != DATA_W)
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$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
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if (m_axi_wr.STRB_W != STRB_W)
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$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
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// bypass AW channel
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assign m_axi_wr.awid = s_axi_wr.awid;
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assign m_axi_wr.awaddr = s_axi_wr.awaddr;
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assign m_axi_wr.awlen = s_axi_wr.awlen;
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assign m_axi_wr.awsize = s_axi_wr.awsize;
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assign m_axi_wr.awburst = s_axi_wr.awburst;
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assign m_axi_wr.awlock = s_axi_wr.awlock;
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assign m_axi_wr.awcache = s_axi_wr.awcache;
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assign m_axi_wr.awprot = s_axi_wr.awprot;
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assign m_axi_wr.awqos = s_axi_wr.awqos;
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assign m_axi_wr.awregion = s_axi_wr.awregion;
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assign m_axi_wr.awuser = AWUSER_EN ? s_axi_wr.awuser : '0;
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assign m_axi_wr.awvalid = s_axi_wr.awvalid;
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assign s_axi_wr.awready = m_axi_wr.awready;
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assign m_axi_wr.wdata = s_axi_wr.wdata;
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assign m_axi_wr.wstrb = s_axi_wr.wstrb;
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assign m_axi_wr.wlast = s_axi_wr.wlast;
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assign m_axi_wr.wuser = WUSER_EN ? s_axi_wr.wuser : '0;
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assign m_axi_wr.wvalid = s_axi_wr.wvalid;
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assign s_axi_wr.wready = m_axi_wr.wready;
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assign s_axi_wr.bid = m_axi_wr.bid;
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assign s_axi_wr.bresp = m_axi_wr.bresp;
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assign s_axi_wr.buser = BUSER_EN ? m_axi_wr.buser : '0;
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assign s_axi_wr.bvalid = m_axi_wr.bvalid;
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assign m_axi_wr.bready = s_axi_wr.bready;
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endmodule
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`resetall
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