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62 lines
1.4 KiB
Systemverilog
62 lines
1.4 KiB
Systemverilog
// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 lite tie (read)
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*/
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module taxi_axil_tie_rd
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(
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/*
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* AXI4 lite slave interface
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*/
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taxi_axil_if.rd_slv s_axil_rd,
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/*
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* AXI4 lite master interface
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*/
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taxi_axil_if.rd_mst m_axil_rd
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);
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// extract parameters
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localparam DATA_W = s_axil_rd.DATA_W;
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localparam ADDR_W = s_axil_rd.ADDR_W;
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localparam STRB_W = s_axil_rd.STRB_W;
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localparam logic ARUSER_EN = s_axil_rd.ARUSER_EN && m_axil_rd.ARUSER_EN;
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localparam ARUSER_W = s_axil_rd.ARUSER_W;
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localparam logic RUSER_EN = s_axil_rd.RUSER_EN && m_axil_rd.RUSER_EN;
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localparam RUSER_W = s_axil_rd.RUSER_W;
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// check configuration
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if (m_axil_rd.DATA_W != DATA_W)
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$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
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if (m_axil_rd.STRB_W != STRB_W)
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$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
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assign m_axil_rd.araddr = s_axil_rd.araddr;
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assign m_axil_rd.arprot = s_axil_rd.arprot;
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assign m_axil_rd.aruser = ARUSER_EN ? s_axil_rd.aruser : '0;
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assign m_axil_rd.arvalid = s_axil_rd.arvalid;
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assign s_axil_rd.arready = m_axil_rd.arready;
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assign s_axil_rd.rdata = m_axil_rd.rdata;
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assign s_axil_rd.rresp = m_axil_rd.rresp;
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assign s_axil_rd.ruser = RUSER_EN ? m_axil_rd.ruser : '0;
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assign s_axil_rd.rvalid = m_axil_rd.rvalid;
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assign m_axil_rd.rready = s_axil_rd.rready;
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endmodule
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`resetall
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