mirror of
https://github.com/fpganinja/taxi.git
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495 lines
13 KiB
Systemverilog
495 lines
13 KiB
Systemverilog
// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2020-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter string VENDOR = "XILINX",
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// device family
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parameter string FAMILY = "zynquplus",
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// SFP rate selection (0 for 1G, 1 for 10G)
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parameter logic SFP_RATE = 1'b1
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)
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(
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/*
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* Clock: 125MHz LVDS
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* Reset: Push button, active low
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*/
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input wire logic clk_125mhz_p,
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input wire logic clk_125mhz_n,
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input wire logic reset,
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/*
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* GPIO
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*/
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input wire logic btnu,
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input wire logic btnl,
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input wire logic btnd,
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input wire logic btnr,
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input wire logic btnc,
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input wire logic [7:0] sw,
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output wire logic [7:0] led,
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/*
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* UART: 115200 bps, 8N1
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*/
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input wire logic uart_rxd,
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output wire logic uart_txd,
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input wire logic uart_rts,
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output wire logic uart_cts,
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/*
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* Ethernet: SFP+
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*/
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input wire logic [1:0] sfp_rx_p,
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input wire logic [1:0] sfp_rx_n,
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output wire logic [1:0] sfp_tx_p,
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output wire logic [1:0] sfp_tx_n,
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input wire logic sfp_mgt_refclk_0_p,
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input wire logic sfp_mgt_refclk_0_n,
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output wire logic [1:0] sfp_tx_disable_b
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);
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wire clk_125mhz_ibufg;
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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// Internal 62.5 MHz clock
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wire clk_62mhz_mmcm_out;
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wire clk_62mhz_int;
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wire mmcm_rst = reset;
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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clk_125mhz_ibufg_inst (
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.O (clk_125mhz_ibufg),
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.I (clk_125mhz_p),
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.IB (clk_125mhz_n)
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);
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// MMCM instance
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MMCME4_BASE #(
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// 125 MHz input
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.CLKIN1_PERIOD(8.0),
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.REF_JITTER1(0.010),
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// 125 MHz input / 1 = 125 MHz PFD (range 10 MHz to 500 MHz)
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.DIVCLK_DIVIDE(1),
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// 125 MHz PFD * 10 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
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.CLKFBOUT_MULT_F(10),
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.CLKFBOUT_PHASE(0),
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// 1250 MHz / 10 = 125 MHz, 0 degrees
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.CLKOUT0_DIVIDE_F(10),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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// 1250 MHz / 20 = 62.5 MHz, 0 degrees
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.CLKOUT1_DIVIDE(20),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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// Not used
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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// Not used
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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// Not used
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT4_CASCADE("FALSE"),
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// Not used
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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// Not used
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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// optimized bandwidth
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.BANDWIDTH("OPTIMIZED"),
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// don't wait for lock during startup
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.STARTUP_WAIT("FALSE")
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)
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clk_mmcm_inst (
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// 125 MHz input
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.CLKIN1(clk_125mhz_ibufg),
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// direct clkfb feeback
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.CLKFBIN(mmcm_clkfb),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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// 125 MHz, 0 degrees
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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// 62.5 MHz, 0 degrees
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.CLKOUT1(clk_62mhz_mmcm_out),
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.CLKOUT1B(),
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// Not used
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.CLKOUT2(),
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.CLKOUT2B(),
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// Not used
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.CLKOUT3(),
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.CLKOUT3B(),
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// Not used
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.CLKOUT4(),
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// Not used
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.CLKOUT5(),
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// Not used
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.CLKOUT6(),
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// reset input
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.RST(mmcm_rst),
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// don't power down
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.PWRDWN(1'b0),
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// locked output
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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BUFG
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clk_62mhz_bufg_inst (
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.I(clk_62mhz_mmcm_out),
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.O(clk_62mhz_int)
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);
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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// GPIO
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wire btnu_int;
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wire btnl_int;
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wire btnd_int;
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wire btnr_int;
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wire btnc_int;
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wire [3:0] sw_int;
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taxi_debounce_switch #(
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.WIDTH(9),
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.N(4),
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.RATE(125000)
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)
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debounce_switch_inst (
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.clk(clk_125mhz_int),
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.rst(rst_125mhz_int),
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.in({btnu,
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btnl,
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btnd,
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btnr,
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btnc,
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sw}),
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.out({btnu_int,
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btnl_int,
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btnd_int,
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btnr_int,
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btnc_int,
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sw_int})
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);
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wire uart_rxd_int;
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wire uart_rts_int;
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taxi_sync_signal #(
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.WIDTH(2),
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.N(2)
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)
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sync_signal_inst (
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.clk(clk_125mhz_int),
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.in({uart_rxd, uart_rts}),
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.out({uart_rxd_int, uart_rts_int})
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);
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wire [7:0] led_int;
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// SFP+
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wire [1:0] sfp_tx_p_int;
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wire [1:0] sfp_tx_n_int;
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wire sfp0_gmii_clk_int;
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wire sfp0_gmii_rst_int;
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wire sfp0_gmii_clk_en_int = 1'b1;
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wire [7:0] sfp0_gmii_txd_int;
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wire sfp0_gmii_tx_en_int;
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wire sfp0_gmii_tx_er_int;
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wire [7:0] sfp0_gmii_rxd_int;
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wire sfp0_gmii_rx_dv_int;
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wire sfp0_gmii_rx_er_int;
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wire [15:0] sfp0_status_vect;
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wire sfp1_gmii_clk_int;
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wire sfp1_gmii_rst_int;
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wire sfp1_gmii_clk_en_int = 1'b1;
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wire [7:0] sfp1_gmii_txd_int;
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wire sfp1_gmii_tx_en_int;
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wire sfp1_gmii_tx_er_int;
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wire [7:0] sfp1_gmii_rxd_int;
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wire sfp1_gmii_rx_dv_int;
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wire sfp1_gmii_rx_er_int;
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wire [15:0] sfp1_status_vect;
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if (SFP_RATE == 0) begin : sfp_phy
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// 1000BASE-X
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wire sfp0_gmii_gtrefclk;
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wire sfp0_gmii_txuserclk;
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wire sfp0_gmii_txuserclk2;
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wire sfp0_gmii_rxuserclk;
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wire sfp0_gmii_rxuserclk2;
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wire sfp0_gmii_resetdone;
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wire sfp0_gmii_pmareset;
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wire sfp0_gmii_mmcm_locked;
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assign sfp0_gmii_clk_int = sfp0_gmii_txuserclk2;
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_sfp0_inst (
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.clk(sfp0_gmii_clk_int),
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.rst(rst_125mhz_int || !sfp0_gmii_resetdone),
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.out(sfp0_gmii_rst_int)
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);
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wire sfp0_status_link_status = sfp0_status_vect[0];
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wire sfp0_status_link_synchronization = sfp0_status_vect[1];
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wire sfp0_status_rudi_c = sfp0_status_vect[2];
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wire sfp0_status_rudi_i = sfp0_status_vect[3];
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wire sfp0_status_rudi_invalid = sfp0_status_vect[4];
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wire sfp0_status_rxdisperr = sfp0_status_vect[5];
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wire sfp0_status_rxnotintable = sfp0_status_vect[6];
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wire sfp0_status_phy_link_status = sfp0_status_vect[7];
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wire [1:0] sfp0_status_remote_fault_encdg = sfp0_status_vect[9:8];
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wire [1:0] sfp0_status_speed = sfp0_status_vect[11:10];
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wire sfp0_status_duplex = sfp0_status_vect[12];
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wire sfp0_status_remote_fault = sfp0_status_vect[13];
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wire [1:0] sfp0_status_pause = sfp0_status_vect[15:14];
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wire [4:0] sfp0_config_vect;
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assign sfp0_config_vect[4] = 1'b0; // autonegotiation enable
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assign sfp0_config_vect[3] = 1'b0; // isolate
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assign sfp0_config_vect[2] = 1'b0; // power down
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assign sfp0_config_vect[1] = 1'b0; // loopback enable
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assign sfp0_config_vect[0] = 1'b0; // unidirectional enable
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basex_pcs_pma_0
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sfp0_pcspma (
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.gtrefclk_p(sfp_mgt_refclk_0_p),
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.gtrefclk_n(sfp_mgt_refclk_0_n),
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.gtrefclk_out(sfp0_gmii_gtrefclk),
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.txn(sfp_tx_n[0]),
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.txp(sfp_tx_p[0]),
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.rxn(sfp_rx_n[0]),
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.rxp(sfp_rx_p[0]),
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.independent_clock_bufg(clk_62mhz_int),
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.userclk_out(sfp0_gmii_txuserclk),
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.userclk2_out(sfp0_gmii_txuserclk2),
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.rxuserclk_out(sfp0_gmii_rxuserclk),
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.rxuserclk2_out(sfp0_gmii_rxuserclk2),
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.gtpowergood(),
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.resetdone(sfp0_gmii_resetdone),
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.pma_reset_out(sfp0_gmii_pmareset),
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.mmcm_locked_out(sfp0_gmii_mmcm_locked),
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.gmii_txd(sfp0_gmii_txd_int),
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.gmii_tx_en(sfp0_gmii_tx_en_int),
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.gmii_tx_er(sfp0_gmii_tx_er_int),
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.gmii_rxd(sfp0_gmii_rxd_int),
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.gmii_rx_dv(sfp0_gmii_rx_dv_int),
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.gmii_rx_er(sfp0_gmii_rx_er_int),
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.gmii_isolate(),
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.configuration_vector(sfp0_config_vect),
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.status_vector(sfp0_status_vect),
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.reset(rst_125mhz_int),
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.signal_detect(1'b1)
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);
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wire sfp1_gmii_txuserclk2 = sfp0_gmii_txuserclk2;
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wire sfp1_gmii_resetdone;
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assign sfp1_gmii_clk_int = sfp1_gmii_txuserclk2;
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_sfp1_inst (
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.clk(sfp1_gmii_clk_int),
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.rst(rst_125mhz_int || !sfp1_gmii_resetdone),
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.out(sfp1_gmii_rst_int)
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);
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wire sfp1_status_link_status = sfp1_status_vect[0];
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wire sfp1_status_link_synchronization = sfp1_status_vect[1];
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wire sfp1_status_rudi_c = sfp1_status_vect[2];
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wire sfp1_status_rudi_i = sfp1_status_vect[3];
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wire sfp1_status_rudi_invalid = sfp1_status_vect[4];
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wire sfp1_status_rxdisperr = sfp1_status_vect[5];
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wire sfp1_status_rxnotintable = sfp1_status_vect[6];
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wire sfp1_status_phy_link_status = sfp1_status_vect[7];
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wire [1:0] sfp1_status_remote_fault_encdg = sfp1_status_vect[9:8];
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wire [1:0] sfp1_status_speed = sfp1_status_vect[11:10];
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wire sfp1_status_duplex = sfp1_status_vect[12];
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wire sfp1_status_remote_fault = sfp1_status_vect[13];
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wire [1:0] sfp1_status_pause = sfp1_status_vect[15:14];
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wire [4:0] sfp1_config_vect;
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assign sfp1_config_vect[4] = 1'b0; // autonegotiation enable
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assign sfp1_config_vect[3] = 1'b0; // isolate
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assign sfp1_config_vect[2] = 1'b0; // power down
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assign sfp1_config_vect[1] = 1'b0; // loopback enable
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assign sfp1_config_vect[0] = 1'b0; // unidirectional enable
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basex_pcs_pma_1
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sfp1_pcspma (
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.gtrefclk(sfp0_gmii_gtrefclk),
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.txn(sfp_tx_n[1]),
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.txp(sfp_tx_p[1]),
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.rxn(sfp_rx_n[1]),
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.rxp(sfp_rx_p[1]),
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.independent_clock_bufg(clk_62mhz_int),
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.txoutclk(),
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.gtpowergood(),
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.rxoutclk(),
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.resetdone(sfp1_gmii_resetdone),
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.cplllock(),
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.mmcm_reset(),
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.userclk(sfp0_gmii_txuserclk),
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.userclk2(sfp0_gmii_txuserclk2),
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.pma_reset(sfp0_gmii_pmareset),
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.mmcm_locked(sfp0_gmii_mmcm_locked),
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.rxuserclk(sfp0_gmii_txuserclk),
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.rxuserclk2(sfp0_gmii_txuserclk2),
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.gmii_txd(sfp1_gmii_txd_int),
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.gmii_tx_en(sfp1_gmii_tx_en_int),
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.gmii_tx_er(sfp1_gmii_tx_er_int),
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.gmii_rxd(sfp1_gmii_rxd_int),
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.gmii_rx_dv(sfp1_gmii_rx_dv_int),
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.gmii_rx_er(sfp1_gmii_rx_er_int),
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.gmii_isolate(),
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.configuration_vector(sfp1_config_vect),
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.status_vector(sfp1_status_vect),
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.reset(rst_125mhz_int),
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.signal_detect(1'b1)
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);
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end else begin
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// 10GBASE-R
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assign sfp_tx_p = sfp_tx_p_int;
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assign sfp_tx_n = sfp_tx_n_int;
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end
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// SGMII interface debug:
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// SW12:1 (sw[3]) off for payload byte, on for status vector
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// SW12:2 (sw[2]) off for SFP0, on for SFP1
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// SW12:4 (sw[0]) off for LSB of status vector, on for MSB
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wire [15:0] sel_sv = sw[2] ? sfp1_status_vect : sfp0_status_vect;
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assign led = sw[3] ? (sw[0] ? sel_sv[15:8] : sel_sv[7:0]) : led_int;
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fpga_core #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.SFP_RATE(SFP_RATE)
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)
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core_inst (
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/*
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* Clock: 125MHz
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* Synchronous reset
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*/
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.clk_125mhz(clk_125mhz_int),
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.rst_125mhz(rst_125mhz_int),
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/*
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* GPIO
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*/
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.btnu(btnu_int),
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.btnl(btnl_int),
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.btnd(btnd_int),
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.btnr(btnr_int),
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.btnc(btnc_int),
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.sw(sw_int),
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.led(led_int),
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/*
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* UART: 115200 bps, 8N1
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*/
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.uart_rxd(uart_rxd_int),
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.uart_txd(uart_txd),
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.uart_rts(uart_rts_int),
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.uart_cts(uart_cts),
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/*
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* Ethernet: SFP+
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*/
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.sfp_rx_p(sfp_rx_p),
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.sfp_rx_n(sfp_rx_n),
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.sfp_tx_p(sfp_tx_p_int),
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.sfp_tx_n(sfp_tx_n_int),
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.sfp_mgt_refclk_0_p(sfp_mgt_refclk_0_p),
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.sfp_mgt_refclk_0_n(sfp_mgt_refclk_0_n),
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.sfp0_gmii_clk(sfp0_gmii_clk_int),
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.sfp0_gmii_rst(sfp0_gmii_rst_int),
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.sfp0_gmii_clk_en(sfp0_gmii_clk_en_int),
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.sfp0_gmii_rxd(sfp0_gmii_rxd_int),
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.sfp0_gmii_rx_dv(sfp0_gmii_rx_dv_int),
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.sfp0_gmii_rx_er(sfp0_gmii_rx_er_int),
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.sfp0_gmii_txd(sfp0_gmii_txd_int),
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.sfp0_gmii_tx_en(sfp0_gmii_tx_en_int),
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.sfp0_gmii_tx_er(sfp0_gmii_tx_er_int),
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.sfp1_gmii_clk(sfp1_gmii_clk_int),
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.sfp1_gmii_rst(sfp1_gmii_rst_int),
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.sfp1_gmii_clk_en(sfp1_gmii_clk_en_int),
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.sfp1_gmii_rxd(sfp1_gmii_rxd_int),
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.sfp1_gmii_rx_dv(sfp1_gmii_rx_dv_int),
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.sfp1_gmii_rx_er(sfp1_gmii_rx_er_int),
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.sfp1_gmii_txd(sfp1_gmii_txd_int),
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.sfp1_gmii_tx_en(sfp1_gmii_tx_en_int),
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.sfp1_gmii_tx_er(sfp1_gmii_tx_er_int),
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.sfp_tx_disable_b(sfp_tx_disable_b)
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);
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endmodule
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`resetall
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