mirror of
https://github.com/fpganinja/taxi.git
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460 lines
14 KiB
Systemverilog
460 lines
14 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* MAC statistics
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*/
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module taxi_eth_mac_stats #
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(
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parameter STAT_TX_LEVEL = 1,
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parameter STAT_RX_LEVEL = 1,
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parameter STAT_ID_BASE = 0,
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parameter STAT_UPDATE_PERIOD = 1024,
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parameter logic STAT_STR_EN = 1'b0,
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parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC",
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parameter INC_W = 1
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)
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(
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input wire logic rx_clk,
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input wire logic rx_rst,
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input wire logic tx_clk,
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input wire logic tx_rst,
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/*
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* Statistics
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*/
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input wire logic stat_clk,
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input wire logic stat_rst,
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taxi_axis_if.src m_axis_stat,
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/*
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* Status
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*/
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input wire logic tx_start_packet,
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input wire logic [INC_W-1:0] stat_tx_byte,
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input wire logic [15:0] stat_tx_pkt_len,
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input wire logic stat_tx_pkt_ucast,
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input wire logic stat_tx_pkt_mcast,
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input wire logic stat_tx_pkt_bcast,
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input wire logic stat_tx_pkt_vlan,
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input wire logic stat_tx_pkt_good,
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input wire logic stat_tx_pkt_bad,
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input wire logic stat_tx_err_oversize,
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input wire logic stat_tx_err_user,
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input wire logic stat_tx_err_underflow,
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input wire logic rx_start_packet,
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input wire logic [INC_W-1:0] stat_rx_byte,
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input wire logic [15:0] stat_rx_pkt_len,
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input wire logic stat_rx_pkt_fragment,
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input wire logic stat_rx_pkt_jabber,
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input wire logic stat_rx_pkt_ucast,
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input wire logic stat_rx_pkt_mcast,
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input wire logic stat_rx_pkt_bcast,
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input wire logic stat_rx_pkt_vlan,
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input wire logic stat_rx_pkt_good,
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input wire logic stat_rx_pkt_bad,
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input wire logic stat_rx_err_oversize,
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input wire logic stat_rx_err_bad_fcs,
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input wire logic stat_rx_err_bad_block,
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input wire logic stat_rx_err_framing,
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input wire logic stat_rx_err_preamble,
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input wire logic stat_rx_fifo_drop,
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input wire logic stat_tx_mcf,
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input wire logic stat_rx_mcf,
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input wire logic stat_tx_lfc_pkt,
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input wire logic stat_tx_lfc_xon,
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input wire logic stat_tx_lfc_xoff,
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input wire logic stat_tx_lfc_paused,
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input wire logic stat_tx_pfc_pkt,
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input wire logic [7:0] stat_tx_pfc_xon,
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input wire logic [7:0] stat_tx_pfc_xoff,
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input wire logic [7:0] stat_tx_pfc_paused,
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input wire logic stat_rx_lfc_pkt,
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input wire logic stat_rx_lfc_xon,
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input wire logic stat_rx_lfc_xoff,
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input wire logic stat_rx_lfc_paused,
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input wire logic stat_rx_pfc_pkt,
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input wire logic [7:0] stat_rx_pfc_xon,
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input wire logic [7:0] stat_rx_pfc_xoff,
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input wire logic [7:0] stat_rx_pfc_paused
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);
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localparam TX_CNT = STAT_TX_LEVEL == 0 ? 8 : (STAT_TX_LEVEL == 1 ? 16: 32);
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localparam RX_CNT = STAT_RX_LEVEL == 0 ? 8 : (STAT_RX_LEVEL == 1 ? 16: 32);
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taxi_axis_if #(
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.DATA_W(m_axis_stat.DATA_W),
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.KEEP_EN(m_axis_stat.KEEP_EN),
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.KEEP_W(m_axis_stat.KEEP_W),
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.LAST_EN(m_axis_stat.LAST_EN),
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.ID_EN(m_axis_stat.ID_EN),
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.ID_W(m_axis_stat.ID_W),
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.USER_EN(m_axis_stat.USER_EN),
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.USER_W(m_axis_stat.USER_W)
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)
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axis_stat_tx(), axis_stat_rx(), axis_stat_int[2]();
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wire [8*8-1:0] tx_str[TX_CNT];
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wire [INC_W-1:0] tx_inc[TX_CNT];
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wire hist_tx_pkt_small = (stat_tx_pkt_len != 0) && stat_tx_pkt_len[15:6] == 0;
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wire hist_tx_pkt_64 = stat_tx_pkt_len == 64;
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wire hist_tx_pkt_65_127 = stat_tx_pkt_len[15:6] == 1 && stat_tx_pkt_len != 64;
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wire hist_tx_pkt_128_255 = stat_tx_pkt_len[15:7] == 1;
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wire hist_tx_pkt_256_511 = stat_tx_pkt_len[15:8] == 1;
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wire hist_tx_pkt_512_1023 = stat_tx_pkt_len[15:9] == 1;
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wire hist_tx_pkt_1024_1518 = stat_tx_pkt_len[15:10] == 1 && stat_tx_pkt_len <= 1518;
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wire hist_tx_pkt_large_1 = stat_tx_pkt_len > 1518;
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wire hist_tx_pkt_1519_2047 = stat_tx_pkt_len[15:11] == 0 && stat_tx_pkt_len > 1518;
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wire hist_tx_pkt_2048_4095 = stat_tx_pkt_len[15:11] == 1;
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wire hist_tx_pkt_4096_8192 = stat_tx_pkt_len[15:12] == 1;
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wire hist_tx_pkt_8192_9215 = stat_tx_pkt_len[15:13] == 1 && stat_tx_pkt_len <= 9215;
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wire hist_tx_pkt_large_2 = stat_tx_pkt_len > 9215;
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assign tx_str[0] = "TX_BYTES";
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assign tx_inc[0] = stat_tx_byte;
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assign tx_str[1] = "TX_PKTS";
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assign tx_inc[1] = INC_W'(tx_start_packet);
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assign tx_str[2] = "TX_ERR";
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assign tx_inc[2] = INC_W'(stat_tx_err_user);
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assign tx_str[3] = "TX_UNDR";
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assign tx_inc[3] = INC_W'(stat_tx_err_underflow);
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assign tx_str[4] = "TX_OVRSZ";
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assign tx_inc[4] = INC_W'(stat_tx_err_oversize);
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assign tx_str[5] = "TX_CTRL";
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assign tx_inc[5] = INC_W'(stat_tx_mcf);
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assign tx_str[6] = "TX_COL";
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assign tx_inc[6] = INC_W'(0);
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assign tx_str[7] = "";
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assign tx_inc[7] = INC_W'(0);
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if (STAT_TX_LEVEL > 0) begin
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assign tx_str[8] = "TX_PSM";
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assign tx_inc[8] = INC_W'(hist_tx_pkt_small);
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assign tx_str[9] = "TX_P64";
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assign tx_inc[9] = INC_W'(hist_tx_pkt_64);
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assign tx_str[10] = "TX_P65";
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assign tx_inc[10] = INC_W'(hist_tx_pkt_65_127);
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assign tx_str[11] = "TX_P128";
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assign tx_inc[11] = INC_W'(hist_tx_pkt_128_255);
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assign tx_str[12] = "TX_P256";
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assign tx_inc[12] = INC_W'(hist_tx_pkt_256_511);
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assign tx_str[13] = "TX_P512";
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assign tx_inc[13] = INC_W'(hist_tx_pkt_512_1023);
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assign tx_str[14] = "TX_P1024";
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assign tx_inc[14] = INC_W'(hist_tx_pkt_1024_1518);
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assign tx_str[15] = "TX_PLG";
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assign tx_inc[15] = INC_W'(STAT_TX_LEVEL > 1 ? hist_tx_pkt_large_2 : hist_tx_pkt_large_1);
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end
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if (STAT_TX_LEVEL > 1) begin
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assign tx_str[16] = "TX_P1519";
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assign tx_inc[16] = INC_W'(hist_tx_pkt_1519_2047);
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assign tx_str[17] = "TX_P2048";
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assign tx_inc[17] = INC_W'(hist_tx_pkt_2048_4095);
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assign tx_str[18] = "TX_P4096";
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assign tx_inc[18] = INC_W'(hist_tx_pkt_4096_8192);
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assign tx_str[19] = "TX_P8192";
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assign tx_inc[19] = INC_W'(hist_tx_pkt_8192_9215);
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assign tx_str[20] = "TX_UCAST";
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assign tx_inc[20] = INC_W'(stat_tx_pkt_ucast);
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assign tx_str[21] = "TX_MCAST";
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assign tx_inc[21] = INC_W'(stat_tx_pkt_mcast);
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assign tx_str[22] = "TX_BCAST";
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assign tx_inc[22] = INC_W'(stat_tx_pkt_bcast);
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assign tx_str[23] = "TX_VLAN";
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assign tx_inc[23] = INC_W'(stat_tx_pkt_vlan);
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assign tx_str[24] = "TX_LFC";
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assign tx_inc[24] = INC_W'(stat_tx_lfc_pkt);
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assign tx_str[25] = "TX_PFC";
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assign tx_inc[25] = INC_W'(stat_tx_pfc_pkt);
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assign tx_str[26] = "TX_MCOL";
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assign tx_inc[26] = INC_W'(0);
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assign tx_str[27] = "TX_DEFER";
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assign tx_inc[27] = INC_W'(0);
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assign tx_str[28] = "TX_LCOL";
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assign tx_inc[28] = INC_W'(0);
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assign tx_str[29] = "TX_ECOL";
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assign tx_inc[29] = INC_W'(0);
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assign tx_str[30] = "TX_EDEF";
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assign tx_inc[30] = INC_W'(0);
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assign tx_str[31] = "";
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assign tx_inc[31] = INC_W'(0);
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end
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taxi_stats_collect #(
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.CNT(TX_CNT),
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.INC_W(INC_W),
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.ID_BASE(STAT_ID_BASE),
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.UPDATE_PERIOD(STAT_UPDATE_PERIOD),
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.STR_EN(STAT_STR_EN),
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.PREFIX_STR(STAT_PREFIX_STR)
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)
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tx_stats_inst (
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.clk(tx_clk),
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.rst(tx_rst),
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/*
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* Increment inputs
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*/
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.stat_inc(tx_inc),
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.stat_valid('{TX_CNT{1'b1}}),
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.stat_str(tx_str),
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/*
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* Statistics increment output
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*/
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.m_axis_stat(axis_stat_tx),
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/*
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* Control inputs
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*/
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.gate(1'b1),
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.update(1'b0)
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);
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taxi_axis_async_fifo #(
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.DEPTH(32),
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.RAM_PIPELINE(0),
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.FRAME_FIFO(1'b0),
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.DROP_BAD_FRAME(1'b0),
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.DROP_WHEN_FULL(1'b0)
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)
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tx_stat_fifo (
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/*
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* AXI4-Stream input (sink)
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*/
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.s_clk(tx_clk),
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.s_rst(tx_rst),
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.s_axis(axis_stat_tx),
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/*
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* AXI4-Stream output (source)
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*/
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.m_clk(stat_clk),
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.m_rst(stat_rst),
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.m_axis(axis_stat_int[0]),
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/*
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* Pause
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*/
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.s_pause_req(1'b0),
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.s_pause_ack(),
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.m_pause_req(1'b0),
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.m_pause_ack(),
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/*
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* Status
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*/
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.s_status_depth(),
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.s_status_depth_commit(),
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.s_status_overflow(),
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.s_status_bad_frame(),
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.s_status_good_frame(),
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.m_status_depth(),
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.m_status_depth_commit(),
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.m_status_overflow(),
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.m_status_bad_frame(),
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.m_status_good_frame()
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);
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wire [8*8-1:0] rx_str[TX_CNT];
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wire [INC_W-1:0] rx_inc[RX_CNT];
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wire hist_rx_pkt_small = (stat_rx_pkt_len != 0) && stat_rx_pkt_len[15:6] == 0;
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wire hist_rx_pkt_64 = stat_rx_pkt_len == 64;
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wire hist_rx_pkt_65_127 = stat_rx_pkt_len[15:6] == 1 && stat_rx_pkt_len != 64;
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wire hist_rx_pkt_128_255 = stat_rx_pkt_len[15:7] == 1;
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wire hist_rx_pkt_256_511 = stat_rx_pkt_len[15:8] == 1;
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wire hist_rx_pkt_512_1023 = stat_rx_pkt_len[15:9] == 1;
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wire hist_rx_pkt_1024_1518 = stat_rx_pkt_len[15:10] == 1 && stat_rx_pkt_len <= 1518;
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wire hist_rx_pkt_large_1 = stat_rx_pkt_len > 1518;
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wire hist_rx_pkt_1519_2047 = stat_rx_pkt_len[15:11] == 0 && stat_rx_pkt_len > 1518;
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wire hist_rx_pkt_2048_4095 = stat_rx_pkt_len[15:11] == 1;
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wire hist_rx_pkt_4096_8192 = stat_rx_pkt_len[15:12] == 1;
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wire hist_rx_pkt_8192_9215 = stat_rx_pkt_len[15:13] == 1 && stat_rx_pkt_len <= 9215;
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wire hist_rx_pkt_large_2 = stat_rx_pkt_len > 9215;
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assign rx_str[0] = "RX_BYTES";
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assign rx_inc[0] = stat_rx_byte;
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assign rx_str[1] = "RX_PKTS";
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assign rx_inc[1] = INC_W'(rx_start_packet);
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assign rx_str[2] = "RX_FCSER";
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assign rx_inc[2] = INC_W'(stat_rx_err_bad_fcs);
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assign rx_str[3] = "RX_FDRP";
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assign rx_inc[3] = INC_W'(stat_rx_fifo_drop);
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assign rx_str[4] = "RX_OVRSZ";
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assign rx_inc[4] = INC_W'(stat_rx_err_oversize);
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assign rx_str[5] = "RX_CTRL";
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assign rx_inc[5] = INC_W'(stat_rx_mcf);
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assign rx_str[6] = "RX_ERBLK";
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assign rx_inc[6] = INC_W'(stat_rx_err_bad_block);
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assign rx_str[7] = "RX_ERFRM";
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assign rx_inc[7] = INC_W'(stat_rx_err_framing);
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if (STAT_RX_LEVEL > 0) begin
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assign rx_str[8] = "RX_PSM";
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assign rx_inc[8] = INC_W'(hist_rx_pkt_small);
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assign rx_str[9] = "RX_P64";
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assign rx_inc[9] = INC_W'(hist_rx_pkt_64);
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assign rx_str[10] = "RX_P65";
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assign rx_inc[10] = INC_W'(hist_rx_pkt_65_127);
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assign rx_str[11] = "RX_P128";
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assign rx_inc[11] = INC_W'(hist_rx_pkt_128_255);
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assign rx_str[12] = "RX_P256";
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assign rx_inc[12] = INC_W'(hist_rx_pkt_256_511);
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assign rx_str[13] = "RX_P512";
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assign rx_inc[13] = INC_W'(hist_rx_pkt_512_1023);
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assign rx_str[14] = "RX_P1024";
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assign rx_inc[14] = INC_W'(hist_rx_pkt_1024_1518);
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assign rx_str[15] = "RX_PLG";
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assign rx_inc[15] = INC_W'(STAT_RX_LEVEL > 1 ? hist_rx_pkt_large_2 : hist_rx_pkt_large_1);
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end
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if (STAT_RX_LEVEL > 1) begin
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assign rx_str[16] = "RX_P1519";
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assign rx_inc[16] = INC_W'(hist_rx_pkt_1519_2047);
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assign rx_str[17] = "RX_P2048";
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assign rx_inc[17] = INC_W'(hist_rx_pkt_2048_4095);
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assign rx_str[18] = "RX_P4096";
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assign rx_inc[18] = INC_W'(hist_rx_pkt_4096_8192);
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assign rx_str[19] = "RX_P8192";
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assign rx_inc[19] = INC_W'(hist_rx_pkt_8192_9215);
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assign rx_str[20] = "RX_UCAST";
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assign rx_inc[20] = INC_W'(stat_rx_pkt_ucast);
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assign rx_str[21] = "RX_MCAST";
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assign rx_inc[21] = INC_W'(stat_rx_pkt_mcast);
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assign rx_str[22] = "RX_BCAST";
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assign rx_inc[22] = INC_W'(stat_rx_pkt_bcast);
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assign rx_str[23] = "RX_VLAN";
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assign rx_inc[23] = INC_W'(stat_rx_pkt_vlan);
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assign rx_str[24] = "RX_LFC";
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assign rx_inc[24] = INC_W'(stat_rx_lfc_pkt);
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assign rx_str[25] = "RX_PFC";
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assign rx_inc[25] = INC_W'(stat_rx_pfc_pkt);
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assign rx_str[26] = "RX_ERPRE";
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assign rx_inc[26] = INC_W'(stat_rx_err_preamble);
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assign rx_str[27] = "RX_FRG";
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assign rx_inc[27] = INC_W'(stat_rx_pkt_fragment);
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assign rx_str[28] = "RX_JBR";
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assign rx_inc[28] = INC_W'(stat_rx_pkt_jabber);
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assign rx_str[29] = "";
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assign rx_inc[29] = INC_W'(0);
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assign rx_str[30] = "";
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assign rx_inc[30] = INC_W'(0);
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assign rx_str[31] = "";
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assign rx_inc[31] = INC_W'(0);
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end
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taxi_stats_collect #(
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.CNT(RX_CNT),
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.INC_W(INC_W),
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.ID_BASE(STAT_ID_BASE+TX_CNT),
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.UPDATE_PERIOD(STAT_UPDATE_PERIOD),
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.STR_EN(STAT_STR_EN),
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.PREFIX_STR(STAT_PREFIX_STR)
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)
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rx_stats_inst (
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.clk(rx_clk),
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.rst(rx_rst),
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/*
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* Increment inputs
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*/
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.stat_inc(rx_inc),
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.stat_valid('{RX_CNT{1'b1}}),
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.stat_str(rx_str),
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/*
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* Statistics increment output
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*/
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.m_axis_stat(axis_stat_rx),
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/*
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* Control inputs
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*/
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.gate(1'b1),
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.update(1'b0)
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);
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taxi_axis_async_fifo #(
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.DEPTH(32),
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.RAM_PIPELINE(0),
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.FRAME_FIFO(1'b0),
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.DROP_BAD_FRAME(1'b0),
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.DROP_WHEN_FULL(1'b0)
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)
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rx_stat_fifo (
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/*
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* AXI4-Stream input (sink)
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*/
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.s_clk(rx_clk),
|
|
.s_rst(rx_rst),
|
|
.s_axis(axis_stat_rx),
|
|
|
|
/*
|
|
* AXI4-Stream output (source)
|
|
*/
|
|
.m_clk(stat_clk),
|
|
.m_rst(stat_rst),
|
|
.m_axis(axis_stat_int[1]),
|
|
|
|
/*
|
|
* Pause
|
|
*/
|
|
.s_pause_req(1'b0),
|
|
.s_pause_ack(),
|
|
.m_pause_req(1'b0),
|
|
.m_pause_ack(),
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
.s_status_depth(),
|
|
.s_status_depth_commit(),
|
|
.s_status_overflow(),
|
|
.s_status_bad_frame(),
|
|
.s_status_good_frame(),
|
|
.m_status_depth(),
|
|
.m_status_depth_commit(),
|
|
.m_status_overflow(),
|
|
.m_status_bad_frame(),
|
|
.m_status_good_frame()
|
|
);
|
|
|
|
taxi_axis_arb_mux #(
|
|
.S_COUNT($size(axis_stat_int)),
|
|
.UPDATE_TID(1'b0),
|
|
.ARB_ROUND_ROBIN(1'b1),
|
|
.ARB_LSB_HIGH_PRIO(1'b0)
|
|
)
|
|
stat_mux_inst (
|
|
.clk(stat_clk),
|
|
.rst(stat_rst),
|
|
|
|
/*
|
|
* AXI4-Stream inputs (sink)
|
|
*/
|
|
.s_axis(axis_stat_int),
|
|
|
|
/*
|
|
* AXI4-Stream output (source)
|
|
*/
|
|
.m_axis(m_axis_stat)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|