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https://github.com/fpganinja/taxi.git
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322 lines
11 KiB
Systemverilog
322 lines
11 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2016-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream consistent overhead byte stuffing (COBS) decoder
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*/
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module taxi_axis_cobs_decode
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4-Stream input (sink)
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*/
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taxi_axis_if.snk s_axis,
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/*
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* AXI4-Stream output (source)
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*/
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taxi_axis_if.src m_axis
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);
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// check configuration
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if (m_axis.DATA_W != 8 || s_axis.DATA_W != 8)
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$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
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// state register
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localparam [1:0]
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STATE_IDLE = 2'd0,
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STATE_SEGMENT = 2'd1,
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STATE_NEXT_SEGMENT = 2'd2;
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logic [1:0] state_reg = STATE_IDLE, state_next;
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logic [7:0] count_reg = 8'd0, count_next;
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logic suppress_zero_reg = 1'b0, suppress_zero_next;
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logic [7:0] temp_tdata_reg = 8'd0, temp_tdata_next;
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logic temp_tvalid_reg = 1'b0, temp_tvalid_next;
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// internal datapath
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logic [7:0] m_axis_tdata_int;
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logic m_axis_tvalid_int;
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logic m_axis_tready_int_reg = 1'b0;
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logic m_axis_tlast_int;
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logic m_axis_tuser_int;
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wire m_axis_tready_int_early;
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logic s_axis_tready_reg = 1'b0, s_axis_tready_next;
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assign s_axis.tready = s_axis_tready_reg;
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always_comb begin
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state_next = STATE_IDLE;
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count_next = count_reg;
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suppress_zero_next = suppress_zero_reg;
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temp_tdata_next = temp_tdata_reg;
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temp_tvalid_next = temp_tvalid_reg;
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m_axis_tdata_int = 8'd0;
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m_axis_tvalid_int = 1'b0;
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m_axis_tlast_int = 1'b0;
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m_axis_tuser_int = 1'b0;
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s_axis_tready_next = 1'b0;
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case (state_reg)
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STATE_IDLE: begin
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// idle state
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s_axis_tready_next = m_axis_tready_int_early || !temp_tvalid_reg;
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// output final word
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m_axis_tdata_int = temp_tdata_reg;
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m_axis_tvalid_int = temp_tvalid_reg;
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m_axis_tlast_int = temp_tvalid_reg;
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temp_tvalid_next = temp_tvalid_reg && !m_axis_tready_int_reg;
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if (s_axis.tready && s_axis.tvalid) begin
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// valid input data
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// skip any leading zeros
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if (s_axis.tdata != 8'd0) begin
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// store count value and zero suppress
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count_next = s_axis.tdata-1;
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suppress_zero_next = (s_axis.tdata == 8'd255);
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s_axis_tready_next = m_axis_tready_int_early;
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if (s_axis.tdata == 8'd1) begin
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// next byte will be count value
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state_next = STATE_NEXT_SEGMENT;
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end else begin
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// next byte will be data
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state_next = STATE_SEGMENT;
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end
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end else begin
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state_next = STATE_IDLE;
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end
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_SEGMENT: begin
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// receive segment
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s_axis_tready_next = m_axis_tready_int_early;
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if (s_axis.tready && s_axis.tvalid) begin
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// valid input data
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// store in temp register
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temp_tdata_next = s_axis.tdata;
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temp_tvalid_next = 1'b1;
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// move temp to output
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m_axis_tdata_int = temp_tdata_reg;
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m_axis_tvalid_int = temp_tvalid_reg;
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// decrement count
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count_next = count_reg - 1;
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if (s_axis.tdata == 8'd0) begin
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// got a zero byte in a frame - mark it as an error and re-sync
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temp_tvalid_next = 1'b0;
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m_axis_tvalid_int = 1'b1;
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m_axis_tuser_int = 1'b1;
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m_axis_tlast_int = 1'b1;
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s_axis_tready_next = 1'b1;
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state_next = STATE_IDLE;
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end else if (s_axis.LAST_EN && s_axis.tlast) begin
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// end of frame
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if (count_reg == 8'd1 && (!s_axis.USER_EN || !s_axis.tuser)) begin
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// end of frame indication at correct time, go to idle to output final byte
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state_next = STATE_IDLE;
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end else begin
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// end of frame indication at invalid time or tuser assert, so mark as an error and re-sync
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temp_tvalid_next = 1'b0;
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m_axis_tvalid_int = 1'b1;
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m_axis_tuser_int = 1'b1;
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m_axis_tlast_int = 1'b1;
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s_axis_tready_next = 1'b1;
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state_next = STATE_IDLE;
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end
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end else if (count_reg == 8'd1) begin
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// next byte will be count value
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state_next = STATE_NEXT_SEGMENT;
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end else begin
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// next byte will be data
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state_next = STATE_SEGMENT;
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end
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end else begin
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state_next = STATE_SEGMENT;
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end
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end
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STATE_NEXT_SEGMENT: begin
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// next segment
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s_axis_tready_next = m_axis_tready_int_early;
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if (s_axis.tready && s_axis.tvalid) begin
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// valid input data
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// store zero in temp if not suppressed
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temp_tdata_next = 8'd0;
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temp_tvalid_next = !suppress_zero_reg;
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// move temp to output
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m_axis_tdata_int = temp_tdata_reg;
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m_axis_tvalid_int = temp_tvalid_reg;
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if (s_axis.tdata == 8'd0) begin
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// got a zero byte delineating the end of the frame, so mark as such and re-sync
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temp_tvalid_next = 1'b0;
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m_axis_tuser_int = s_axis.tuser;
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m_axis_tlast_int = 1'b1;
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s_axis_tready_next = 1'b1;
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state_next = STATE_IDLE;
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end else if (s_axis.LAST_EN && s_axis.tlast) begin
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if (s_axis.tdata == 8'd1 && (!s_axis.USER_EN || !s_axis.tuser)) begin
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// end of frame indication at correct time, go to idle to output final byte
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state_next = STATE_IDLE;
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end else begin
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// end of frame indication at invalid time or tuser assert, so mark as an error and re-sync
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temp_tvalid_next = 1'b0;
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m_axis_tvalid_int = 1'b1;
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m_axis_tuser_int = 1'b1;
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m_axis_tlast_int = 1'b1;
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s_axis_tready_next = 1'b1;
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state_next = STATE_IDLE;
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end
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end else begin
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// otherwise, store count value and zero suppress
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count_next = s_axis.tdata-1;
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suppress_zero_next = (s_axis.tdata == 8'd255);
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s_axis_tready_next = m_axis_tready_int_early;
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if (s_axis.tdata == 8'd1) begin
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// next byte will be count value
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state_next = STATE_NEXT_SEGMENT;
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end else begin
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// next byte will be data
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state_next = STATE_SEGMENT;
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end
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end
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end else begin
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state_next = STATE_NEXT_SEGMENT;
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end
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end
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default: begin
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// invalid state
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state_next = STATE_IDLE;
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end
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endcase
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end
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always_ff @(posedge clk) begin
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state_reg <= state_next;
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count_reg <= count_next;
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suppress_zero_reg <= suppress_zero_next;
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temp_tdata_reg <= temp_tdata_next;
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temp_tvalid_reg <= temp_tvalid_next;
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s_axis_tready_reg <= s_axis_tready_next;
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if (rst) begin
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state_reg <= STATE_IDLE;
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temp_tvalid_reg <= 1'b0;
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s_axis_tready_reg <= 1'b0;
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end
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end
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// output datapath logic
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logic [7:0] m_axis_tdata_reg = 8'd0;
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logic m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
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logic m_axis_tlast_reg = 1'b0;
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logic m_axis_tuser_reg = 1'b0;
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logic [7:0] temp_m_axis_tdata_reg = 8'd0;
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logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
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logic temp_m_axis_tlast_reg = 1'b0;
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logic temp_m_axis_tuser_reg = 1'b0;
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// datapath control
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logic store_axis_int_to_output;
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logic store_axis_int_to_temp;
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logic store_axis_temp_to_output;
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assign m_axis.tdata = m_axis_tdata_reg;
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assign m_axis.tkeep = 1'b1;
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assign m_axis.tstrb = m_axis.tkeep;
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assign m_axis.tvalid = m_axis_tvalid_reg;
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assign m_axis.tlast = m_axis_tlast_reg;
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assign m_axis.tid = '0;
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assign m_axis.tdest = '0;
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assign m_axis.tuser = m_axis_tuser_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign m_axis_tready_int_early = m_axis.tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
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always_comb begin
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// transfer sink ready state to source
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m_axis_tvalid_next = m_axis_tvalid_reg;
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temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
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store_axis_int_to_output = 1'b0;
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store_axis_int_to_temp = 1'b0;
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store_axis_temp_to_output = 1'b0;
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if (m_axis_tready_int_reg) begin
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// input is ready
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if (m_axis.tready || !m_axis_tvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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m_axis_tvalid_next = m_axis_tvalid_int;
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store_axis_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_m_axis_tvalid_next = m_axis_tvalid_int;
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store_axis_int_to_temp = 1'b1;
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end
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end else if (m_axis.tready) begin
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// input is not ready, but output is ready
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m_axis_tvalid_next = temp_m_axis_tvalid_reg;
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temp_m_axis_tvalid_next = 1'b0;
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store_axis_temp_to_output = 1'b1;
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end
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end
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always_ff @(posedge clk) begin
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m_axis_tvalid_reg <= m_axis_tvalid_next;
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m_axis_tready_int_reg <= m_axis_tready_int_early;
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temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
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// datapath
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if (store_axis_int_to_output) begin
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m_axis_tdata_reg <= m_axis_tdata_int;
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m_axis_tlast_reg <= m_axis_tlast_int;
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m_axis_tuser_reg <= m_axis_tuser_int;
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end else if (store_axis_temp_to_output) begin
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m_axis_tdata_reg <= temp_m_axis_tdata_reg;
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m_axis_tlast_reg <= temp_m_axis_tlast_reg;
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m_axis_tuser_reg <= temp_m_axis_tuser_reg;
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end
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if (store_axis_int_to_temp) begin
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temp_m_axis_tdata_reg <= m_axis_tdata_int;
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temp_m_axis_tlast_reg <= m_axis_tlast_int;
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temp_m_axis_tuser_reg <= m_axis_tuser_int;
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end
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if (rst) begin
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m_axis_tvalid_reg <= 1'b0;
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m_axis_tready_int_reg <= 1'b0;
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temp_m_axis_tvalid_reg <= 1'b0;
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end
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end
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endmodule
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`resetall
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