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75 lines
1.6 KiB
Systemverilog
75 lines
1.6 KiB
Systemverilog
// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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interface taxi_pcie_tlp_if #(
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parameter SEGS = 1,
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parameter SEG_DATA_W = 256,
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parameter SEG_EMPTY_W = $clog2(SEG_DATA_W/32),
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parameter HDR_W = 128,
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parameter FUNC_NUM_W = 8,
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parameter SEQ_NUM_W = 6
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)
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();
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logic [SEGS-1:0][SEG_DATA_W-1:0] data;
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logic [SEGS-1:0][SEG_EMPTY_W-1:0] empty;
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logic [SEGS-1:0][HDR_W-1:0] hdr;
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logic [SEGS-1:0][SEQ_NUM_W-1:0] seq;
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logic [SEGS-1:0][2:0] bar_id;
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logic [SEGS-1:0][FUNC_NUM_W-1:0] func_num;
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logic [SEGS-1:0][3:0] error;
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logic [SEGS-1:0] valid;
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logic [SEGS-1:0] sop;
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logic [SEGS-1:0] eop;
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logic ready;
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modport src (
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output data,
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output empty,
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output hdr,
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output seq,
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output bar_id,
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output func_num,
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output error,
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output valid,
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output sop,
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output eop,
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input ready
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);
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modport snk (
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input data,
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input empty,
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input hdr,
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input seq,
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input bar_id,
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input func_num,
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input error,
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input valid,
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input sop,
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input eop,
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output ready
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);
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modport mon (
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input data,
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input empty,
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input hdr,
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input seq,
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input bar_id,
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input func_num,
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input error,
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input valid,
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input sop,
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input eop,
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input ready
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);
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endinterface
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