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194 lines
4.9 KiB
Systemverilog
194 lines
4.9 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2016-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* LFSR PRBS checker
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*/
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module taxi_lfsr_prbs_check #
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(
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// width of LFSR
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parameter LFSR_W = 31,
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// LFSR polynomial
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parameter logic [LFSR_W-1:0] LFSR_POLY = 31'h10000001,
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// Initial state
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parameter logic [LFSR_W-1:0] LFSR_INIT = '1,
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// LFSR configuration: 0 for Fibonacci (PRBS), 1 for Galois (CRC)
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parameter logic LFSR_GALOIS = 1'b0,
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// bit-reverse input and output
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parameter logic REVERSE = 1'b0,
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// invert input
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parameter logic INVERT = 1'b1,
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// width of data input and output
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parameter DATA_W = 8
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)
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(
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input wire logic clk,
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input wire logic rst,
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input wire logic [DATA_W-1:0] data_in,
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input wire logic data_in_valid,
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output wire logic [DATA_W-1:0] data_out
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);
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/*
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Fully parametrizable combinatorial parallel LFSR PRBS checker. Implements an unrolled LFSR
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PRBS checker.
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Ports:
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clk
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Clock input
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rst
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Reset input, set state to LFSR_INIT
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data_in
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PRBS data input (DATA_W bits)
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data_in_valid
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Shift input data through LFSR when asserted
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data_out
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Error output (DATA_W bits)
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Parameters:
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LFSR_W
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Specify width of LFSR/CRC register
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LFSR_POLY
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Specify the LFSR/CRC polynomial in hex format. For example, the polynomial
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x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
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would be represented as
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32'h04c11db7
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Note that the largest term (x^32) is suppressed. This term is generated automatically based
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on LFSR_W.
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LFSR_INIT
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Initial state of LFSR. Defaults to all 1s.
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LFSR_GALOIS
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Specify the LFSR configuration, either Fibonacci (0) or Galois (1). Fibonacci is generally used
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for linear-feedback shift registers (LFSR) for pseudorandom binary sequence (PRBS) generators,
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scramblers, and descrambers, while Galois is generally used for cyclic redundancy check
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generators and checkers.
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Fibonacci style (example for 64b66b scrambler, 0x8000000001)
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DIN (LSB first)
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V
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(+)<---------------------------(+)<-----------------------------.
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| ^ |
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| .----. .----. .----. | .----. .----. .----. |
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+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--'
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| '----' '----' '----' '----' '----' '----'
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V
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DOUT
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Galois style (example for CRC16, 0x8005)
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,-------------------+-------------------------+----------(+)<-- DIN (MSB first)
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| | | ^
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| .----. .----. V .----. .----. V .----. |
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`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |--+---> DOUT
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'----' '----' '----' '----' '----'
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REVERSE
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Bit-reverse LFSR output. Shifts MSB first by default, set REVERSE for LSB first.
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INVERT
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Bitwise invert PRBS input.
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DATA_W
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Specify width of output data bus.
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Settings for common LFSR/CRC implementations:
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Name Configuration Length Polynomial Initial value Notes
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CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output
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PRBS6 Fibonacci 6 6'h21 any
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PRBS7 Fibonacci 7 7'h41 any
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PRBS9 Fibonacci 9 9'h021 any ITU V.52
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PRBS10 Fibonacci 10 10'h081 any ITU
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PRBS11 Fibonacci 11 11'h201 any ITU O.152
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PRBS15 Fibonacci, inverted 15 15'h4001 any ITU O.152
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PRBS17 Fibonacci 17 17'h04001 any
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PRBS20 Fibonacci 20 20'h00009 any ITU V.57
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PRBS23 Fibonacci, inverted 23 23'h040001 any ITU O.151
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PRBS29 Fibonacci, inverted 29 29'h08000001 any
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PRBS31 Fibonacci, inverted 31 31'h10000001 any
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64b66b Fibonacci, bit-reverse 58 58'h8000000001 any 10G Ethernet
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128b130b Galois, bit-reverse 23 23'h210125 any PCIe gen 3
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*/
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logic [LFSR_W-1:0] state_reg = LFSR_INIT;
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logic [DATA_W-1:0] output_reg = '0;
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wire [DATA_W-1:0] lfsr_data;
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wire [LFSR_W-1:0] lfsr_state;
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assign data_out = output_reg;
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taxi_lfsr #(
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.LFSR_W(LFSR_W),
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.LFSR_POLY(LFSR_POLY),
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.LFSR_GALOIS(LFSR_GALOIS),
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.LFSR_FEED_FORWARD('1),
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.REVERSE(REVERSE),
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.DATA_W(DATA_W),
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.DATA_IN_EN(1'b1),
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.DATA_OUT_EN(1'b1)
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)
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lfsr_inst (
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.data_in(INVERT ? ~data_in : data_in),
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.state_in(state_reg),
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.data_out(lfsr_data),
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.state_out(lfsr_state)
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);
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always_ff @(posedge clk) begin
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if (data_in_valid) begin
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state_reg <= lfsr_state;
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output_reg <= lfsr_data;
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end
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if (rst) begin
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state_reg <= LFSR_INIT;
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output_reg <= '0;
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end
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end
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endmodule
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`resetall
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