mirror of
https://github.com/fpganinja/taxi.git
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127 lines
2.6 KiB
Systemverilog
127 lines
2.6 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2019-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* MII PHY interface
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*/
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module taxi_mii_phy_if #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter VENDOR = "XILINX",
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// device family
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parameter FAMILY = "virtex7"
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)
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(
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input wire logic rst,
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/*
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* MII interface to MAC
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*/
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output wire logic mac_mii_rx_clk,
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output wire logic mac_mii_rx_rst,
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output wire logic [3:0] mac_mii_rxd,
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output wire logic mac_mii_rx_dv,
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output wire logic mac_mii_rx_er,
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output wire logic mac_mii_tx_clk,
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output wire logic mac_mii_tx_rst,
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input wire logic [3:0] mac_mii_txd,
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input wire logic mac_mii_tx_en,
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input wire logic mac_mii_tx_er,
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/*
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* MII interface to PHY
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*/
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input wire logic phy_mii_rx_clk,
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input wire logic [3:0] phy_mii_rxd,
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input wire logic phy_mii_rx_dv,
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input wire logic phy_mii_rx_er,
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input wire logic phy_mii_tx_clk,
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output wire logic [3:0] phy_mii_txd,
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output wire logic phy_mii_tx_en,
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output wire logic phy_mii_tx_er
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);
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taxi_ssio_sdr_in #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.WIDTH(6)
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)
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rx_ssio_sdr_inst (
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.input_clk(phy_mii_rx_clk),
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.input_d({phy_mii_rxd, phy_mii_rx_dv, phy_mii_rx_er}),
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.output_clk(mac_mii_rx_clk),
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.output_q({mac_mii_rxd, mac_mii_rx_dv, mac_mii_rx_er})
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);
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(* IOB = "TRUE" *)
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reg [3:0] phy_mii_txd_reg = 4'd0;
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(* IOB = "TRUE" *)
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reg phy_mii_tx_en_reg = 1'b0, phy_mii_tx_er_reg = 1'b0;
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assign phy_mii_txd = phy_mii_txd_reg;
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assign phy_mii_tx_en = phy_mii_tx_en_reg;
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assign phy_mii_tx_er = phy_mii_tx_er_reg;
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always_ff @(posedge mac_mii_tx_clk) begin
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phy_mii_txd_reg <= mac_mii_txd;
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phy_mii_tx_en_reg <= mac_mii_tx_en;
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phy_mii_tx_er_reg <= mac_mii_tx_er;
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end
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generate
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if (!SIM && VENDOR == "XILINX") begin
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// Xilinx/AMD device support
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BUFG
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mii_bufg_inst (
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.I(phy_mii_tx_clk),
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.O(mac_mii_tx_clk)
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);
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end else begin
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// generic/simulation implementation (no vendor primitives)
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assign mac_mii_tx_clk = phy_mii_tx_clk;
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end
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endgenerate
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// reset sync
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taxi_sync_reset #(
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.N(4)
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)
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tx_reset_sync_inst (
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.clk(mac_mii_tx_clk),
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.rst(rst),
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.out(mac_mii_tx_rst)
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);
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taxi_sync_reset #(
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.N(4)
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)
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rx_reset_sync_inst (
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.clk(mac_mii_rx_clk),
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.rst(rst),
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.out(mac_mii_rx_rst)
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);
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endmodule
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`resetall
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