mirror of
https://github.com/fpganinja/taxi.git
synced 2025-12-09 17:08:38 -08:00
243 lines
6.2 KiB
Python
243 lines
6.2 KiB
Python
#!/usr/bin/env python
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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"""
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import itertools
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import logging
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import os
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import struct
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import sys
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import cocotb_test.simulator
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import pytest
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotb.regression import TestFactory
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from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
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try:
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from xfcp import XfcpFrame
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except ImportError:
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# attempt import from current directory
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sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
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try:
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from xfcp import XfcpFrame
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finally:
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del sys.path[0]
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class TB(object):
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def __init__(self, dut, baud=3e6):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())
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self.usp_source = AxiStreamSource(AxiStreamBus.from_entity(dut.xfcp_usp_ds), dut.clk, dut.rst)
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self.usp_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.xfcp_usp_us), dut.clk, dut.rst)
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self.dsp_sources = [AxiStreamSource(AxiStreamBus.from_entity(bus), dut.clk, dut.rst) for bus in dut.xfcp_dsp_us]
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self.dsp_sinks = [AxiStreamSink(AxiStreamBus.from_entity(bus), dut.clk, dut.rst) for bus in dut.xfcp_dsp_ds]
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def set_idle_generator(self, generator=None):
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if generator:
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self.usp_source.set_pause_generator(generator())
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for src in self.dsp_sources:
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src.set_pause_generator(generator())
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def set_backpressure_generator(self, generator=None):
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if generator:
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self.usp_sink.set_pause_generator(generator())
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for snk in self.dsp_sinks:
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snk.set_pause_generator(generator())
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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async def run_test_downstream(dut, idle_inserter=None, backpressure_inserter=None, port=0):
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tb = TB(dut)
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await tb.reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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pkt = XfcpFrame()
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pkt.path = [port]
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pkt.ptype = 0x01
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pkt.payload = bytearray(range(8))
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tb.log.debug("TX packet: %s", pkt)
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await tb.usp_source.send(pkt.build())
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rx_frame = await tb.dsp_sinks[port].recv()
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rx_pkt = XfcpFrame.parse(rx_frame.tdata)
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tb.log.debug("RX packet: %s", rx_pkt)
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assert rx_pkt.path == []
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assert rx_pkt.ptype == 0x01
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assert rx_pkt.payload == bytearray(range(8))
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_test_upstream(dut, idle_inserter=None, backpressure_inserter=None, port=0):
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tb = TB(dut)
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await tb.reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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pkt = XfcpFrame()
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pkt.ptype = 0x01
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pkt.payload = bytearray(range(8))
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tb.log.debug("TX packet: %s", pkt)
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await tb.dsp_sources[port].send(pkt.build())
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rx_frame = await tb.usp_sink.recv()
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rx_pkt = XfcpFrame.parse(rx_frame.tdata)
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tb.log.debug("RX packet: %s", rx_pkt)
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assert rx_pkt.path == [port]
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assert rx_pkt.ptype == 0x01
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assert rx_pkt.payload == bytearray(range(8))
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_test_id(dut, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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await tb.reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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pkt = XfcpFrame()
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pkt.ptype = 0xFE
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pkt.payload = b''
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tb.log.debug("TX packet: %s", pkt)
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await tb.usp_source.send(pkt.build())
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rx_frame = await tb.usp_sink.recv()
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rx_pkt = XfcpFrame.parse(rx_frame.tdata)
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tb.log.debug("RX packet: %s", rx_pkt)
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assert len(rx_pkt.payload) == 32
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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def cycle_pause():
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return itertools.cycle([1, 1, 1, 0])
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if cocotb.SIM_NAME:
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ports = len(cocotb.top.xfcp_dsp_us)
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for test in [run_test_downstream, run_test_upstream]:
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factory = TestFactory(test)
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factory.add_option("idle_inserter", [None, cycle_pause])
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factory.add_option("backpressure_inserter", [None, cycle_pause])
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factory.add_option("port", list(range(ports)))
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factory.generate_tests()
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for test in [run_test_id]:
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factory = TestFactory(test)
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factory.add_option("idle_inserter", [None, cycle_pause])
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factory.add_option("backpressure_inserter", [None, cycle_pause])
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factory.generate_tests()
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# cocotb-test
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tests_dir = os.path.dirname(__file__)
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
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def process_f_files(files):
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lst = {}
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for f in files:
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if f[-2:].lower() == '.f':
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with open(f, 'r') as fp:
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l = fp.read().split()
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for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
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lst[os.path.basename(f)] = f
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else:
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lst[os.path.basename(f)] = f
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return list(lst.values())
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@pytest.mark.parametrize("ports", [1, 4])
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def test_taxi_xfcp_switch(request, ports):
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dut = "taxi_xfcp_switch"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = module
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verilog_sources = [
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os.path.join(tests_dir, f"{toplevel}.sv"),
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os.path.join(rtl_dir, "xfcp", f"{dut}.f"),
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]
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verilog_sources = process_f_files(verilog_sources)
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parameters = {}
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parameters['PORTS'] = ports
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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simulator="verilator",
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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