Alex Forencich 69e5ae8545 axis: Add AXI stream async FIFO module and testbench ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2025-02-06 00:46:39 -08:00

..

axis

axis: Add AXI stream async FIFO module and testbench

2025-02-06 00:46:39 -08:00

eth

eth: Add MAC pause control modules

2025-02-05 21:11:14 -08:00

io

io: Add switch debounce module

2025-02-04 00:16:34 -08:00

lfsr

lfsr: Add LFSR descrambler module and testbench

2025-02-05 15:29:12 -08:00

lss

lss: Add UART module and testbench

2025-02-03 15:02:48 -08:00

sync

sync: Add signal synchronizer module

2025-02-03 23:43:18 -08:00