Alex Forencich b434897069 eth: Update testbenches ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2026-08-04 14:10:05 -07:00

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apb

apb: Update APB interconnect to support arbitration between multiple upstream devices

2026-03-19 22:05:27 -07:00

axi

axi: Clean up user signal width handling in AXI RAM IF modules

2026-03-20 00:06:23 -07:00

axis

axis: Add AXI stream padding module and testbench

2026-05-11 15:22:56 -07:00

cndm

cndm: Update example designs

2026-07-13 19:31:54 -07:00

cndm_proto

cndm_proto: Update example designs

2026-07-13 17:50:14 -07:00

dma

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eth

eth: Update testbenches

2026-08-04 14:10:05 -07:00

hip/rtl/us

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io/rtl

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lfsr

lfsr: Update LFSR module to support shifting the state before/after shifting the data, including backwards shifts

2026-05-11 15:02:30 -07:00

lss

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math

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pcie

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prim

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ptp

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pyrite

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stats

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sync

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xfcp

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zircon

zircon: Reorganize metadata for better rules engine interface

2026-04-07 15:47:43 -07:00