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128 lines
2.3 KiB
Systemverilog
128 lines
2.3 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2018-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* 10G Ethernet PHY TX
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*/
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module taxi_eth_phy_10g_tx #
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(
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parameter DATA_W = 64,
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parameter CTRL_W = (DATA_W/8),
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parameter HDR_W = 2,
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parameter logic BIT_REVERSE = 1'b0,
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parameter logic SCRAMBLER_DISABLE = 1'b0,
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parameter logic PRBS31_EN = 1'b0,
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parameter SERDES_PIPELINE = 0
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* XGMII interface
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*/
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input wire logic [DATA_W-1:0] xgmii_txd,
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input wire logic [CTRL_W-1:0] xgmii_txc,
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/*
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* SERDES interface
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*/
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output wire logic [DATA_W-1:0] serdes_tx_data,
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output wire logic [HDR_W-1:0] serdes_tx_hdr,
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/*
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* Status
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*/
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output wire logic tx_bad_block,
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/*
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* Configuration
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*/
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input wire logic cfg_tx_prbs31_enable
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);
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// check configuration
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if (DATA_W != 64)
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$fatal(0, "Error: Interface width must be 64");
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if (CTRL_W * 8 != DATA_W)
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$fatal(0, "Error: Interface requires byte (8-bit) granularity");
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if (HDR_W != 2)
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$fatal(0, "Error: HDR_W must be 2");
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wire [DATA_W-1:0] encoded_tx_data;
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wire [HDR_W-1:0] encoded_tx_hdr;
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taxi_xgmii_baser_enc_64 #(
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.DATA_W(DATA_W),
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.CTRL_W(CTRL_W),
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.HDR_W(HDR_W)
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)
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xgmii_baser_enc_inst (
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.clk(clk),
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.rst(rst),
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/*
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* XGMII interface
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*/
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.xgmii_txd(xgmii_txd),
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.xgmii_txc(xgmii_txc),
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/*
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* 10GBASE-R encoded interface
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*/
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.encoded_tx_data(encoded_tx_data),
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.encoded_tx_hdr(encoded_tx_hdr),
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/*
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* Status
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*/
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.tx_bad_block(tx_bad_block)
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);
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taxi_eth_phy_10g_tx_if #(
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.DATA_W(DATA_W),
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.HDR_W(HDR_W),
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.BIT_REVERSE(BIT_REVERSE),
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.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
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.PRBS31_EN(PRBS31_EN),
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.SERDES_PIPELINE(SERDES_PIPELINE)
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)
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eth_phy_10g_tx_if_inst (
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.clk(clk),
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.rst(rst),
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/*
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* 10GBASE-R encoded interface
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*/
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.encoded_tx_data(encoded_tx_data),
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.encoded_tx_hdr(encoded_tx_hdr),
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/*
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* SERDES interface
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*/
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.serdes_tx_data(serdes_tx_data),
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.serdes_tx_hdr(serdes_tx_hdr),
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/*
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* Configuration
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*/
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.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable)
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);
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endmodule
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`resetall
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