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62 lines
780 B
Systemverilog
62 lines
780 B
Systemverilog
// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 tie
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*/
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module taxi_axi_tie
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(
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/*
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* AXI4 slave interface
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*/
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taxi_axi_if.wr_slv s_axi_wr,
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taxi_axi_if.rd_slv s_axi_rd,
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/*
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* AXI4 master interface
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*/
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taxi_axi_if.wr_mst m_axi_wr,
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taxi_axi_if.rd_mst m_axi_rd
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);
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taxi_axi_tie_wr
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wr_inst (
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/*
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* AXI4 slave interface
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*/
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.s_axi_wr(s_axi_wr),
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/*
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* AXI4 master interface
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*/
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.m_axi_wr(m_axi_wr)
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);
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taxi_axi_tie_rd
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rd_inst (
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/*
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* AXI4 slave interface
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*/
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.s_axi_rd(s_axi_rd),
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/*
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* AXI4 master interface
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*/
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.m_axi_rd(m_axi_rd)
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);
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endmodule
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`resetall
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