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24 lines
1.1 KiB
Tcl
24 lines
1.1 KiB
Tcl
# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2025-2026 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# XDC constraints for the Xilinx ZCU102 board
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# part: xczu9eg-ffvb1156-2-e
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# PMOD0
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set_property -dict {LOC A20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod0[0]}] ;# J55.1
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set_property -dict {LOC B20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod0[1]}] ;# J55.3
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set_property -dict {LOC A22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod0[2]}] ;# J55.5
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set_property -dict {LOC A21 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod0[3]}] ;# J55.7
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set_property -dict {LOC B21 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod0[4]}] ;# J55.2
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set_property -dict {LOC C21 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod0[5]}] ;# J55.4
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set_property -dict {LOC C22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod0[6]}] ;# J55.6
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set_property -dict {LOC D21 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {pmod0[7]}] ;# J55.8
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set_false_path -to [get_ports {pmod0[*]}]
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set_output_delay 0 [get_ports {pmod0[*]}]
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