mirror of
https://github.com/fpganinja/taxi.git
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259 lines
6.8 KiB
Python
259 lines
6.8 KiB
Python
#!/usr/bin/env python
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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"""
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Copyright (c) 2021-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import itertools
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import logging
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import os
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import random
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import cocotb_test.simulator
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import pytest
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotb.regression import TestFactory
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from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
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class TB(object):
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
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self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
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self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
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def set_idle_generator(self, generator=None):
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if generator:
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self.source.set_pause_generator(generator())
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def set_backpressure_generator(self, generator=None):
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if generator:
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self.sink.set_pause_generator(generator())
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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id_count = 2**len(tb.source.bus.tid)
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cur_id = 1
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await tb.reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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test_frames = []
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for test_data in [payload_data(x) for x in payload_lengths()]:
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test_frame = AxiStreamFrame(test_data)
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test_frame.tid = cur_id
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test_frame.tdest = cur_id
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test_frames.append(test_frame)
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await tb.source.send(test_frame)
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cur_id = (cur_id + 1) % id_count
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for test_frame in test_frames:
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rx_frame = await tb.sink.recv()
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assert rx_frame.tdata == test_frame.tdata
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assert rx_frame.tid == test_frame.tid
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assert rx_frame.tdest == test_frame.tdest
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assert not rx_frame.tuser
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assert tb.sink.empty()
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_test_tuser_assert(dut):
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tb = TB(dut)
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await tb.reset()
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test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
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test_frame = AxiStreamFrame(test_data, tuser=1)
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await tb.source.send(test_frame)
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rx_frame = await tb.sink.recv()
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assert rx_frame.tdata == test_data
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assert rx_frame.tuser
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assert tb.sink.empty()
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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byte_lanes = tb.source.byte_lanes
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id_count = 2**len(tb.source.bus.tid)
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cur_id = 1
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await tb.reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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test_frames = []
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for k in range(128):
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length = random.randint(1, byte_lanes*16)
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test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
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test_frame = AxiStreamFrame(test_data)
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test_frame.tid = cur_id
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test_frame.tdest = cur_id
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test_frames.append(test_frame)
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await tb.source.send(test_frame)
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cur_id = (cur_id + 1) % id_count
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for test_frame in test_frames:
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rx_frame = await tb.sink.recv()
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assert rx_frame.tdata == test_frame.tdata
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assert rx_frame.tid == test_frame.tid
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assert rx_frame.tdest == test_frame.tdest
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assert not rx_frame.tuser
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assert tb.sink.empty()
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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def cycle_pause():
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return itertools.cycle([1, 1, 1, 0])
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def size_list():
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data_width = len(cocotb.top.m_axis.tdata)
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byte_width = data_width // 8
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return list(range(1, byte_width*4+1))+[512]+[1]*64
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def incrementing_payload(length):
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return bytearray(itertools.islice(itertools.cycle(range(256)), length))
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if cocotb.SIM_NAME:
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factory = TestFactory(run_test)
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factory.add_option("payload_lengths", [size_list])
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factory.add_option("payload_data", [incrementing_payload])
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factory.add_option("idle_inserter", [None, cycle_pause])
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factory.add_option("backpressure_inserter", [None, cycle_pause])
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factory.generate_tests()
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for test in [run_test_tuser_assert]:
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factory = TestFactory(test)
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factory.generate_tests()
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factory = TestFactory(run_stress_test)
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factory.add_option("idle_inserter", [None, cycle_pause])
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factory.add_option("backpressure_inserter", [None, cycle_pause])
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factory.generate_tests()
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# cocotb-test
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tests_dir = os.path.dirname(__file__)
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
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def process_f_files(files):
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lst = {}
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for f in files:
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if f[-2:].lower() == '.f':
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with open(f, 'r') as fp:
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l = fp.read().split()
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for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
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lst[os.path.basename(f)] = f
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else:
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lst[os.path.basename(f)] = f
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return list(lst.values())
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@pytest.mark.parametrize("reg_type", [0, 1, 2])
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@pytest.mark.parametrize("data_w", [8, 16, 32])
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def test_taxi_axis_register(request, data_w, reg_type):
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dut = "taxi_axis_register"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = module
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verilog_sources = [
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os.path.join(tests_dir, f"{toplevel}.sv"),
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os.path.join(rtl_dir, "axis", f"{dut}.sv"),
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os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"),
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]
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verilog_sources = process_f_files(verilog_sources)
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parameters = {}
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parameters['DATA_W'] = data_w
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parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
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parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
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parameters['STRB_EN'] = 0
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parameters['LAST_EN'] = 1
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parameters['ID_EN'] = 1
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parameters['ID_W'] = 8
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parameters['DEST_EN'] = 1
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parameters['DEST_W'] = 8
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parameters['USER_EN'] = 1
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parameters['USER_W'] = 1
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parameters['REG_TYPE'] = reg_type
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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simulator="verilator",
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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