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70 lines
1.1 KiB
Systemverilog
70 lines
1.1 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Statistics counter testbench
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*/
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module test_taxi_stats_counter #
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(
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/* verilator lint_off WIDTHTRUNC */
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parameter STAT_COUNT_W = 32,
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parameter PIPELINE = 2,
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parameter STAT_INC_W = 16,
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parameter STAT_ID_W = 8,
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parameter AXIL_DATA_W = 32,
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parameter AXIL_ADDR_W = STAT_ID_W + $clog2((STAT_COUNT_W+7)/8)
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/* verilator lint_on WIDTHTRUNC */
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)
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();
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logic clk;
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logic rst;
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taxi_axis_if #(
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.DATA_W(STAT_INC_W),
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.KEEP_EN(0),
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.KEEP_W(1),
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.ID_EN(1),
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.ID_W(STAT_ID_W)
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) s_axis_stat();
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taxi_axil_if #(
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.DATA_W(AXIL_DATA_W),
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.ADDR_W(AXIL_ADDR_W)
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) s_axil();
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taxi_stats_counter #(
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.STAT_COUNT_W(STAT_COUNT_W),
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.PIPELINE(PIPELINE)
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)
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uut (
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.clk(clk),
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.rst(rst),
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/*
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* Statistics increment input
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*/
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.s_axis_stat(s_axis_stat),
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/*
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* AXI Lite register interface
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*/
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.s_axil_wr(s_axil),
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.s_axil_rd(s_axil)
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);
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endmodule
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`resetall
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