mirror of
https://github.com/fpganinja/taxi.git
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790 lines
19 KiB
Systemverilog
790 lines
19 KiB
Systemverilog
// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA core logic
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*/
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module fpga_core #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter string VENDOR = "XILINX",
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// device family
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parameter string FAMILY = "kintexu",
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// SFP rate selection (0 for 1G, 1 for 10G)
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parameter logic SFP_RATE = 1'b1
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)
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(
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/*
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* Clock: 125MHz
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* Synchronous reset
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*/
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input wire logic clk,
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input wire logic rst,
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/*
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* GPIO
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*/
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input wire logic btnu,
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input wire logic btnl,
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input wire logic btnd,
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input wire logic btnr,
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input wire logic btnc,
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input wire logic [7:0] sw,
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output wire logic [7:0] led,
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/*
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* UART: 115200 bps, 8N1
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*/
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input wire logic uart_rxd,
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output wire logic uart_txd,
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input wire logic uart_rts,
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output wire logic uart_cts,
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/*
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* Ethernet: 1000BASE-T
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*/
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input wire logic phy_gmii_clk,
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input wire logic phy_gmii_rst,
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input wire logic phy_gmii_clk_en,
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input wire logic [7:0] phy_gmii_rxd,
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input wire logic phy_gmii_rx_dv,
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input wire logic phy_gmii_rx_er,
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output wire logic [7:0] phy_gmii_txd,
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output wire logic phy_gmii_tx_en,
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output wire logic phy_gmii_tx_er,
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output wire logic phy_reset_n,
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input wire logic phy_int_n,
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/*
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* Ethernet: SFP+
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*/
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input wire logic [1:0] sfp_rx_p,
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input wire logic [1:0] sfp_rx_n,
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output wire logic [1:0] sfp_tx_p,
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output wire logic [1:0] sfp_tx_n,
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input wire logic sfp_mgt_refclk_0_p,
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input wire logic sfp_mgt_refclk_0_n,
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input wire logic sfp0_gmii_clk,
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input wire logic sfp0_gmii_rst,
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input wire logic sfp0_gmii_clk_en,
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input wire logic [7:0] sfp0_gmii_rxd,
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input wire logic sfp0_gmii_rx_dv,
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input wire logic sfp0_gmii_rx_er,
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output wire logic [7:0] sfp0_gmii_txd,
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output wire logic sfp0_gmii_tx_en,
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output wire logic sfp0_gmii_tx_er,
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input wire logic sfp1_gmii_clk,
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input wire logic sfp1_gmii_rst,
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input wire logic sfp1_gmii_clk_en,
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input wire logic [7:0] sfp1_gmii_rxd,
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input wire logic sfp1_gmii_rx_dv,
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input wire logic sfp1_gmii_rx_er,
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output wire logic [7:0] sfp1_gmii_txd,
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output wire logic sfp1_gmii_tx_en,
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output wire logic sfp1_gmii_tx_er,
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output wire logic [1:0] sfp_tx_disable_b
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);
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assign led = sw;
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// XFCP
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assign uart_cts = 1'b0;
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taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
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taxi_xfcp_if_uart #(
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.TX_FIFO_DEPTH(512),
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.RX_FIFO_DEPTH(512)
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)
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xfcp_if_uart_inst (
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.clk(clk),
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.rst(rst),
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/*
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* UART interface
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*/
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.uart_rxd(uart_rxd),
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.uart_txd(uart_txd),
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/*
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* XFCP downstream interface
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*/
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.xfcp_dsp_ds(xfcp_ds),
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.xfcp_dsp_us(xfcp_us),
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/*
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* Configuration
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*/
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.prescale(16'(125000000/921600))
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);
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taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[1](), xfcp_sw_us[1]();
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taxi_xfcp_switch #(
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.XFCP_ID_STR("KCU105"),
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.XFCP_EXT_ID(0),
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.XFCP_EXT_ID_STR("Taxi example"),
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.PORTS($size(xfcp_sw_us))
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)
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xfcp_sw_inst (
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.clk(clk),
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.rst(rst),
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/*
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* XFCP upstream port
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*/
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.xfcp_usp_ds(xfcp_ds),
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.xfcp_usp_us(xfcp_us),
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/*
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* XFCP downstream ports
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*/
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.xfcp_dsp_ds(xfcp_sw_ds),
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.xfcp_dsp_us(xfcp_sw_us)
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);
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taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_stat();
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taxi_xfcp_mod_stats #(
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.XFCP_ID_STR("Statistics"),
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.XFCP_EXT_ID(0),
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.XFCP_EXT_ID_STR(""),
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.STAT_COUNT_W(64),
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.STAT_PIPELINE(2)
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)
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xfcp_stats_inst (
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.clk(clk),
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.rst(rst),
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/*
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* XFCP upstream port
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*/
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.xfcp_usp_ds(xfcp_sw_ds[0]),
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.xfcp_usp_us(xfcp_sw_us[0]),
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/*
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* Statistics increment input
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*/
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.s_axis_stat(axis_stat)
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);
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taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[SFP_RATE ? 2 : 3]();
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taxi_axis_arb_mux #(
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.S_COUNT($size(axis_eth_stat)),
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.UPDATE_TID(1'b0),
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.ARB_ROUND_ROBIN(1'b1),
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.ARB_LSB_HIGH_PRIO(1'b0)
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)
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stat_mux_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4-Stream inputs (sink)
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*/
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.s_axis(axis_eth_stat),
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/*
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* AXI4-Stream output (source)
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*/
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.m_axis(axis_stat)
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);
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// BASE-T PHY
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assign phy_reset_n = !rst;
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taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth();
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taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
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taxi_eth_mac_1g_fifo #(
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.PADDING_EN(1),
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.MIN_FRAME_LEN(64),
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.STAT_EN(1),
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.STAT_TX_LEVEL(1),
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.STAT_RX_LEVEL(1),
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.STAT_ID_BASE(0),
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.STAT_UPDATE_PERIOD(1024),
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.TX_FIFO_DEPTH(16384),
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.TX_FRAME_FIFO(1),
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.RX_FIFO_DEPTH(16384),
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.RX_FRAME_FIFO(1)
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)
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eth_mac_inst (
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.rx_clk(phy_gmii_clk),
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.rx_rst(phy_gmii_rst),
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.tx_clk(phy_gmii_clk),
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.tx_rst(phy_gmii_rst),
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.logic_clk(clk),
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.logic_rst(rst),
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/*
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* Transmit interface (AXI stream)
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*/
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.s_axis_tx(axis_eth),
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.m_axis_tx_cpl(axis_tx_cpl),
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/*
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* Receive interface (AXI stream)
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*/
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.m_axis_rx(axis_eth),
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/*
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* GMII interface
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*/
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.gmii_rxd(phy_gmii_rxd),
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.gmii_rx_dv(phy_gmii_rx_dv),
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.gmii_rx_er(phy_gmii_rx_er),
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.gmii_txd(phy_gmii_txd),
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.gmii_tx_en(phy_gmii_tx_en),
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.gmii_tx_er(phy_gmii_tx_er),
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/*
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* Control
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*/
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.rx_clk_enable(phy_gmii_clk_en),
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.tx_clk_enable(phy_gmii_clk_en),
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.rx_mii_select(1'b0),
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.tx_mii_select(1'b0),
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/*
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* Statistics
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*/
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.stat_clk(clk),
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.stat_rst(rst),
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.m_axis_stat(axis_eth_stat[0]),
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/*
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* Status
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*/
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.tx_error_underflow(),
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.tx_fifo_overflow(),
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.tx_fifo_bad_frame(),
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.tx_fifo_good_frame(),
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.rx_error_bad_frame(),
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.rx_error_bad_fcs(),
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.rx_fifo_overflow(),
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.rx_fifo_bad_frame(),
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.rx_fifo_good_frame(),
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/*
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* Configuration
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*/
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.cfg_tx_max_pkt_len(16'd9218),
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.cfg_tx_ifg(8'd12),
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.cfg_tx_enable(1'b1),
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.cfg_rx_max_pkt_len(16'd9218),
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.cfg_rx_enable(1'b1)
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);
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// SFP+
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assign sfp_tx_disable_b = '1;
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if (SFP_RATE == 0) begin : sfp_mac
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taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_sfp0_eth();
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taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp0_tx_cpl();
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taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_sfp1_eth();
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taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp1_tx_cpl();
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taxi_eth_mac_1g_fifo #(
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.PADDING_EN(1),
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.MIN_FRAME_LEN(64),
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.STAT_EN(1),
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.STAT_TX_LEVEL(1),
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.STAT_RX_LEVEL(1),
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.STAT_ID_BASE((16+16)+(16+16)*0),
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.STAT_UPDATE_PERIOD(1024),
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.TX_FIFO_DEPTH(16384),
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.TX_FRAME_FIFO(1),
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.RX_FIFO_DEPTH(16384),
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.RX_FRAME_FIFO(1)
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)
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sfp0_eth_mac_inst (
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.rx_clk(sfp0_gmii_clk),
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.rx_rst(sfp0_gmii_rst),
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.tx_clk(sfp0_gmii_clk),
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.tx_rst(sfp0_gmii_rst),
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.logic_clk(clk),
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.logic_rst(rst),
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/*
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* Transmit interface (AXI stream)
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*/
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.s_axis_tx(axis_sfp0_eth),
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.m_axis_tx_cpl(axis_sfp0_tx_cpl),
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/*
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* Receive interface (AXI stream)
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*/
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.m_axis_rx(axis_sfp0_eth),
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/*
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* GMII interface
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*/
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.gmii_rxd(sfp0_gmii_rxd),
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.gmii_rx_dv(sfp0_gmii_rx_dv),
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.gmii_rx_er(sfp0_gmii_rx_er),
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.gmii_txd(sfp0_gmii_txd),
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.gmii_tx_en(sfp0_gmii_tx_en),
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.gmii_tx_er(sfp0_gmii_tx_er),
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/*
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* Control
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*/
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.rx_clk_enable(sfp0_gmii_clk_en),
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.tx_clk_enable(sfp0_gmii_clk_en),
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.rx_mii_select(1'b0),
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.tx_mii_select(1'b0),
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/*
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* Statistics
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*/
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.stat_clk(clk),
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.stat_rst(rst),
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.m_axis_stat(axis_eth_stat[1]),
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/*
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* Status
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*/
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.tx_error_underflow(),
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.tx_fifo_overflow(),
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.tx_fifo_bad_frame(),
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.tx_fifo_good_frame(),
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.rx_error_bad_frame(),
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.rx_error_bad_fcs(),
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.rx_fifo_overflow(),
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.rx_fifo_bad_frame(),
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.rx_fifo_good_frame(),
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/*
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* Configuration
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*/
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.cfg_tx_max_pkt_len(16'd9218),
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.cfg_tx_ifg(8'd12),
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.cfg_tx_enable(1'b1),
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.cfg_rx_max_pkt_len(16'd9218),
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.cfg_rx_enable(1'b1)
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);
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taxi_eth_mac_1g_fifo #(
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.PADDING_EN(1),
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.MIN_FRAME_LEN(64),
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.STAT_EN(1),
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.STAT_TX_LEVEL(1),
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.STAT_RX_LEVEL(1),
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.STAT_ID_BASE((16+16)+(16+16)*1),
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.STAT_UPDATE_PERIOD(1024),
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.TX_FIFO_DEPTH(16384),
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.TX_FRAME_FIFO(1),
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.RX_FIFO_DEPTH(16384),
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.RX_FRAME_FIFO(1)
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)
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sfp1_eth_mac_inst (
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.rx_clk(sfp1_gmii_clk),
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.rx_rst(sfp1_gmii_rst),
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.tx_clk(sfp1_gmii_clk),
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.tx_rst(sfp1_gmii_rst),
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.logic_clk(clk),
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.logic_rst(rst),
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/*
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* Transmit interface (AXI stream)
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*/
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.s_axis_tx(axis_sfp1_eth),
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.m_axis_tx_cpl(axis_sfp1_tx_cpl),
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/*
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* Receive interface (AXI stream)
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*/
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.m_axis_rx(axis_sfp1_eth),
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/*
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* GMII interface
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*/
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.gmii_rxd(sfp1_gmii_rxd),
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.gmii_rx_dv(sfp1_gmii_rx_dv),
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.gmii_rx_er(sfp1_gmii_rx_er),
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.gmii_txd(sfp1_gmii_txd),
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.gmii_tx_en(sfp1_gmii_tx_en),
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.gmii_tx_er(sfp1_gmii_tx_er),
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/*
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* Control
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*/
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.rx_clk_enable(sfp1_gmii_clk_en),
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.tx_clk_enable(sfp1_gmii_clk_en),
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.rx_mii_select(1'b0),
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.tx_mii_select(1'b0),
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/*
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* Statistics
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*/
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.stat_clk(clk),
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.stat_rst(rst),
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.m_axis_stat(axis_eth_stat[2]),
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/*
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* Status
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*/
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.tx_error_underflow(),
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.tx_fifo_overflow(),
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.tx_fifo_bad_frame(),
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.tx_fifo_good_frame(),
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.rx_error_bad_frame(),
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.rx_error_bad_fcs(),
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.rx_fifo_overflow(),
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.rx_fifo_bad_frame(),
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.rx_fifo_good_frame(),
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/*
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* Configuration
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*/
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.cfg_tx_max_pkt_len(16'd9218),
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.cfg_tx_ifg(8'd12),
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.cfg_tx_enable(1'b1),
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.cfg_rx_max_pkt_len(16'd9218),
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.cfg_rx_enable(1'b1)
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);
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end else begin : sfp_mac
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wire [1:0] sfp_tx_clk;
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wire [1:0] sfp_tx_rst;
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wire [1:0] sfp_rx_clk;
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wire [1:0] sfp_rx_rst;
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wire [1:0] sfp_rx_status;
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wire sfp_gtpowergood;
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wire sfp_mgt_refclk_0;
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wire sfp_mgt_refclk_0_int;
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wire sfp_mgt_refclk_0_bufg;
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wire sfp_rst;
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taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_tx[2]();
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taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[2]();
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taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_rx[2]();
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if (SIM) begin
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assign sfp_mgt_refclk_0 = sfp_mgt_refclk_0_p;
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assign sfp_mgt_refclk_0_int = sfp_mgt_refclk_0_p;
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assign sfp_mgt_refclk_0_bufg = sfp_mgt_refclk_0_int;
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end else begin
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IBUFDS_GTE3 ibufds_gte3_sfp_mgt_refclk_0_inst (
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.I (sfp_mgt_refclk_0_p),
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.IB (sfp_mgt_refclk_0_n),
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.CEB (1'b0),
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.O (sfp_mgt_refclk_0),
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.ODIV2 (sfp_mgt_refclk_0_int)
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);
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|
BUFG_GT bufg_gt_sfp_mgt_refclk_0_inst (
|
|
.CE (sfp_gtpowergood),
|
|
.CEMASK (1'b1),
|
|
.CLR (1'b0),
|
|
.CLRMASK (1'b1),
|
|
.DIV (3'd0),
|
|
.I (sfp_mgt_refclk_0_int),
|
|
.O (sfp_mgt_refclk_0_bufg)
|
|
);
|
|
|
|
end
|
|
|
|
taxi_sync_reset #(
|
|
.N(4)
|
|
)
|
|
sfp_sync_reset_inst (
|
|
.clk(sfp_mgt_refclk_0_bufg),
|
|
.rst(rst),
|
|
.out(sfp_rst)
|
|
);
|
|
|
|
taxi_eth_mac_25g_us #(
|
|
.SIM(SIM),
|
|
.VENDOR(VENDOR),
|
|
.FAMILY(FAMILY),
|
|
|
|
.CNT(2),
|
|
|
|
// GT type
|
|
.GT_TYPE("GTH"),
|
|
|
|
// PHY parameters
|
|
.PADDING_EN(1'b1),
|
|
.DIC_EN(1'b1),
|
|
.MIN_FRAME_LEN(64),
|
|
.PTP_TS_EN(1'b0),
|
|
.PTP_TS_FMT_TOD(1'b1),
|
|
.PTP_TS_W(96),
|
|
.PRBS31_EN(1'b0),
|
|
.TX_SERDES_PIPELINE(1),
|
|
.RX_SERDES_PIPELINE(1),
|
|
.COUNT_125US(125000/6.4),
|
|
.STAT_EN(1),
|
|
.STAT_TX_LEVEL(1),
|
|
.STAT_RX_LEVEL(1),
|
|
.STAT_ID_BASE(16+16),
|
|
.STAT_UPDATE_PERIOD(1024)
|
|
)
|
|
sfp_mac_inst (
|
|
.xcvr_ctrl_clk(clk),
|
|
.xcvr_ctrl_rst(sfp_rst),
|
|
|
|
/*
|
|
* Common
|
|
*/
|
|
.xcvr_gtpowergood_out(sfp_gtpowergood),
|
|
.xcvr_gtrefclk00_in(sfp_mgt_refclk_0),
|
|
.xcvr_qpll0lock_out(),
|
|
.xcvr_qpll0clk_out(),
|
|
.xcvr_qpll0refclk_out(),
|
|
|
|
/*
|
|
* Serial data
|
|
*/
|
|
.xcvr_txp(sfp_tx_p),
|
|
.xcvr_txn(sfp_tx_n),
|
|
.xcvr_rxp(sfp_rx_p),
|
|
.xcvr_rxn(sfp_rx_n),
|
|
|
|
/*
|
|
* MAC clocks
|
|
*/
|
|
.rx_clk(sfp_rx_clk),
|
|
.rx_rst_in('0),
|
|
.rx_rst_out(sfp_rx_rst),
|
|
.tx_clk(sfp_tx_clk),
|
|
.tx_rst_in('0),
|
|
.tx_rst_out(sfp_tx_rst),
|
|
.ptp_sample_clk('0),
|
|
|
|
/*
|
|
* Transmit interface (AXI stream)
|
|
*/
|
|
.s_axis_tx(axis_sfp_tx),
|
|
.m_axis_tx_cpl(axis_sfp_tx_cpl),
|
|
|
|
/*
|
|
* Receive interface (AXI stream)
|
|
*/
|
|
.m_axis_rx(axis_sfp_rx),
|
|
|
|
/*
|
|
* PTP clock
|
|
*/
|
|
.tx_ptp_ts('{2{'0}}),
|
|
.tx_ptp_ts_step('0),
|
|
.rx_ptp_ts('{2{'0}}),
|
|
.rx_ptp_ts_step('0),
|
|
|
|
/*
|
|
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
|
*/
|
|
.tx_lfc_req('0),
|
|
.tx_lfc_resend('0),
|
|
.rx_lfc_en('0),
|
|
.rx_lfc_req(),
|
|
.rx_lfc_ack('0),
|
|
|
|
/*
|
|
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
|
*/
|
|
.tx_pfc_req('{2{'0}}),
|
|
.tx_pfc_resend('0),
|
|
.rx_pfc_en('{2{'0}}),
|
|
.rx_pfc_req(),
|
|
.rx_pfc_ack('{2{'0}}),
|
|
|
|
/*
|
|
* Pause interface
|
|
*/
|
|
.tx_lfc_pause_en('0),
|
|
.tx_pause_req('0),
|
|
.tx_pause_ack(),
|
|
|
|
/*
|
|
* Statistics
|
|
*/
|
|
.stat_clk(clk),
|
|
.stat_rst(rst),
|
|
.m_axis_stat(axis_eth_stat[1]),
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
.tx_start_packet(),
|
|
.stat_tx_byte(),
|
|
.stat_tx_pkt_len(),
|
|
.stat_tx_pkt_ucast(),
|
|
.stat_tx_pkt_mcast(),
|
|
.stat_tx_pkt_bcast(),
|
|
.stat_tx_pkt_vlan(),
|
|
.stat_tx_pkt_good(),
|
|
.stat_tx_pkt_bad(),
|
|
.stat_tx_err_oversize(),
|
|
.stat_tx_err_user(),
|
|
.stat_tx_err_underflow(),
|
|
.rx_start_packet(),
|
|
.rx_error_count(),
|
|
.rx_block_lock(),
|
|
.rx_high_ber(),
|
|
.rx_status(sfp_rx_status),
|
|
.stat_rx_byte(),
|
|
.stat_rx_pkt_len(),
|
|
.stat_rx_pkt_fragment(),
|
|
.stat_rx_pkt_jabber(),
|
|
.stat_rx_pkt_ucast(),
|
|
.stat_rx_pkt_mcast(),
|
|
.stat_rx_pkt_bcast(),
|
|
.stat_rx_pkt_vlan(),
|
|
.stat_rx_pkt_good(),
|
|
.stat_rx_pkt_bad(),
|
|
.stat_rx_err_oversize(),
|
|
.stat_rx_err_bad_fcs(),
|
|
.stat_rx_err_bad_block(),
|
|
.stat_rx_err_framing(),
|
|
.stat_rx_err_preamble(),
|
|
.stat_rx_fifo_drop('0),
|
|
.stat_tx_mcf(),
|
|
.stat_rx_mcf(),
|
|
.stat_tx_lfc_pkt(),
|
|
.stat_tx_lfc_xon(),
|
|
.stat_tx_lfc_xoff(),
|
|
.stat_tx_lfc_paused(),
|
|
.stat_tx_pfc_pkt(),
|
|
.stat_tx_pfc_xon(),
|
|
.stat_tx_pfc_xoff(),
|
|
.stat_tx_pfc_paused(),
|
|
.stat_rx_lfc_pkt(),
|
|
.stat_rx_lfc_xon(),
|
|
.stat_rx_lfc_xoff(),
|
|
.stat_rx_lfc_paused(),
|
|
.stat_rx_pfc_pkt(),
|
|
.stat_rx_pfc_xon(),
|
|
.stat_rx_pfc_xoff(),
|
|
.stat_rx_pfc_paused(),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.cfg_tx_max_pkt_len('{2{16'd9218}}),
|
|
.cfg_tx_ifg('{2{8'd12}}),
|
|
.cfg_tx_enable('1),
|
|
.cfg_rx_max_pkt_len('{2{16'd9218}}),
|
|
.cfg_rx_enable('1),
|
|
.cfg_tx_prbs31_enable('0),
|
|
.cfg_rx_prbs31_enable('0),
|
|
.cfg_mcf_rx_eth_dst_mcast('{2{48'h01_80_C2_00_00_01}}),
|
|
.cfg_mcf_rx_check_eth_dst_mcast('1),
|
|
.cfg_mcf_rx_eth_dst_ucast('{2{48'd0}}),
|
|
.cfg_mcf_rx_check_eth_dst_ucast('0),
|
|
.cfg_mcf_rx_eth_src('{2{48'd0}}),
|
|
.cfg_mcf_rx_check_eth_src('0),
|
|
.cfg_mcf_rx_eth_type('{2{16'h8808}}),
|
|
.cfg_mcf_rx_opcode_lfc('{2{16'h0001}}),
|
|
.cfg_mcf_rx_check_opcode_lfc('1),
|
|
.cfg_mcf_rx_opcode_pfc('{2{16'h0101}}),
|
|
.cfg_mcf_rx_check_opcode_pfc('1),
|
|
.cfg_mcf_rx_forward('0),
|
|
.cfg_mcf_rx_enable('0),
|
|
.cfg_tx_lfc_eth_dst('{2{48'h01_80_C2_00_00_01}}),
|
|
.cfg_tx_lfc_eth_src('{2{48'h80_23_31_43_54_4C}}),
|
|
.cfg_tx_lfc_eth_type('{2{16'h8808}}),
|
|
.cfg_tx_lfc_opcode('{2{16'h0001}}),
|
|
.cfg_tx_lfc_en('0),
|
|
.cfg_tx_lfc_quanta('{2{16'hffff}}),
|
|
.cfg_tx_lfc_refresh('{2{16'h7fff}}),
|
|
.cfg_tx_pfc_eth_dst('{2{48'h01_80_C2_00_00_01}}),
|
|
.cfg_tx_pfc_eth_src('{2{48'h80_23_31_43_54_4C}}),
|
|
.cfg_tx_pfc_eth_type('{2{16'h8808}}),
|
|
.cfg_tx_pfc_opcode('{2{16'h0101}}),
|
|
.cfg_tx_pfc_en('0),
|
|
.cfg_tx_pfc_quanta('{2{'{8{16'hffff}}}}),
|
|
.cfg_tx_pfc_refresh('{2{'{8{16'h7fff}}}}),
|
|
.cfg_rx_lfc_opcode('{2{16'h0001}}),
|
|
.cfg_rx_lfc_en('0),
|
|
.cfg_rx_pfc_opcode('{2{16'h0101}}),
|
|
.cfg_rx_pfc_en('0)
|
|
);
|
|
|
|
for (genvar n = 0; n < 2; n = n + 1) begin : sfp_ch
|
|
|
|
taxi_axis_async_fifo #(
|
|
.DEPTH(16384),
|
|
.RAM_PIPELINE(2),
|
|
.FRAME_FIFO(1),
|
|
.USER_BAD_FRAME_VALUE(1'b1),
|
|
.USER_BAD_FRAME_MASK(1'b1),
|
|
.DROP_OVERSIZE_FRAME(1),
|
|
.DROP_BAD_FRAME(1),
|
|
.DROP_WHEN_FULL(1)
|
|
)
|
|
ch_fifo (
|
|
/*
|
|
* AXI4-Stream input (sink)
|
|
*/
|
|
.s_clk(sfp_rx_clk[n]),
|
|
.s_rst(sfp_rx_rst[n]),
|
|
.s_axis(axis_sfp_rx[n]),
|
|
|
|
/*
|
|
* AXI4-Stream output (source)
|
|
*/
|
|
.m_clk(sfp_tx_clk[n]),
|
|
.m_rst(sfp_tx_rst[n]),
|
|
.m_axis(axis_sfp_tx[n]),
|
|
|
|
/*
|
|
* Pause
|
|
*/
|
|
.s_pause_req(1'b0),
|
|
.s_pause_ack(),
|
|
.m_pause_req(1'b0),
|
|
.m_pause_ack(),
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
.s_status_depth(),
|
|
.s_status_depth_commit(),
|
|
.s_status_overflow(),
|
|
.s_status_bad_frame(),
|
|
.s_status_good_frame(),
|
|
.m_status_depth(),
|
|
.m_status_depth_commit(),
|
|
.m_status_overflow(),
|
|
.m_status_bad_frame(),
|
|
.m_status_good_frame()
|
|
);
|
|
|
|
end
|
|
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|