Files
taxi/example/HTG940/fpga/eth_rgmii.xdc
Alex Forencich 650da9c972 example/HTG940: Add example design for HTG940
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-02-20 10:20:15 -08:00

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Tcl

# SPDX-License-Identifier: MIT
#
# Copyright (c) 2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# Ethernet constraints
# IDELAY from PHY chip (RGMII)
set_property DELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_bit[*].idelay_inst}]
# MMCM phase (RGMII)
set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]