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123 lines
6.5 KiB
Tcl
123 lines
6.5 KiB
Tcl
# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# XDC constraints for the HiTech Global HTG-9200 board
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# part: xcvu9p-flgb2104-2-e
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# part: xcvu13p-fhgb2104-2-e
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# General configuration
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
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set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
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set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
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set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
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# System clocks
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# DDR4 clocks from U37 (200 MHz)
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#set_property -dict {LOC BA34 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_a_p]
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#set_property -dict {LOC BB34 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_a_n]
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#create_clock -period 5.000 -name sys_clk_ddr4_a [get_ports sys_clk_ddr4_a_p]
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# refclk from U39 (156.25 MHz)
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set_property -dict {LOC AW28 IOSTANDARD LVDS} [get_ports ref_clk_p]
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set_property -dict {LOC AY28 IOSTANDARD LVDS} [get_ports ref_clk_n]
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create_clock -period 6.400 -name ref_clk [get_ports ref_clk_p]
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# LEDs
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set_property -dict {LOC AP28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
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set_property -dict {LOC AN28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}]
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set_property -dict {LOC AP26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[2]}]
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set_property -dict {LOC AP25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[3]}]
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set_property -dict {LOC AR28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[4]}]
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set_property -dict {LOC AR27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[5]}]
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set_property -dict {LOC AT28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[6]}]
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set_property -dict {LOC AR25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[7]}]
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set_false_path -to [get_ports {led[*]}]
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set_output_delay 0 [get_ports {led[*]}]
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# Push buttons
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set_property -dict {LOC AJ34 IOSTANDARD LVCMOS12} [get_ports {btn[0]}]
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set_property -dict {LOC AK32 IOSTANDARD LVCMOS12} [get_ports {btn[1]}]
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set_false_path -from [get_ports {btn[*]}]
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set_input_delay 0 [get_ports {btn[*]}]
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# DIP switches
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set_property -dict {LOC BF33 IOSTANDARD LVCMOS12} [get_ports {sw[0]}]
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set_property -dict {LOC AK27 IOSTANDARD LVCMOS12} [get_ports {sw[1]}]
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set_property -dict {LOC AR32 IOSTANDARD LVCMOS12} [get_ports {sw[2]}]
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set_property -dict {LOC AR31 IOSTANDARD LVCMOS12} [get_ports {sw[3]}]
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set_property -dict {LOC AT32 IOSTANDARD LVCMOS12} [get_ports {sw[4]}]
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set_property -dict {LOC AW30 IOSTANDARD LVCMOS12} [get_ports {sw[5]}]
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set_property -dict {LOC BC32 IOSTANDARD LVCMOS12} [get_ports {sw[6]}]
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set_property -dict {LOC BC33 IOSTANDARD LVCMOS12} [get_ports {sw[7]}]
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set_false_path -from [get_ports {sw[*]}]
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set_input_delay 0 [get_ports {sw[*]}]
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# UART (U53 CP2103)
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set_property -dict {LOC R15 IOSTANDARD LVCMOS18} [get_ports {uart_txd}] ;# U53.25 TXD_O
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set_property -dict {LOC P15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_rxd}] ;# U53.24 RXD_I
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set_property -dict {LOC L15 IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U53.23 RTS_O_B
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set_property -dict {LOC D14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U53.22 CTS_I_B
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set_property -dict {LOC P16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_rst_n}] ;# U53.9 RST_B
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set_false_path -to [get_ports {uart_rxd uart_cts uart_rst_n}]
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set_output_delay 0 [get_ports {uart_rxd uart_cts uart_rst_n}]
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set_false_path -from [get_ports {uart_txd uart_rts}]
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set_input_delay 0 [get_ports {uart_txd uart_rts}]
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# I2C
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set_property -dict {LOC AV28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_scl]
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set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_sda]
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set_property -dict {LOC AV27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_rst_n]
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set_false_path -to [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}]
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set_output_delay 0 [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}]
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set_false_path -from [get_ports {i2c_main_sda i2c_main_scl}]
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set_input_delay 0 [get_ports {i2c_main_sda i2c_main_scl}]
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# Gigabit Ethernet RGMII PHY
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set_property -dict {LOC G20 IOSTANDARD LVCMOS18} [get_ports {phy_rx_clk}] ;# from U2.43 // MAYBE
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set_property -dict {LOC A20 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[0]}] ;# from U2.44
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set_property -dict {LOC D21 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[1]}] ;# from U2.45
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set_property -dict {LOC E21 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[2]}] ;# from U2.46
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set_property -dict {LOC C21 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[3]}] ;# from U2.47
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set_property -dict {LOC B21 IOSTANDARD LVCMOS18} [get_ports {phy_rx_ctl}] ;# from U2.53
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set_property -dict {LOC B20 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_tx_clk}] ;# from U2.40
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set_property -dict {LOC D20 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] ;# from U2.38
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set_property -dict {LOC A19 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] ;# from U2.37
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set_property -dict {LOC B19 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] ;# from U2.36
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set_property -dict {LOC E20 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] ;# from U2.35
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set_property -dict {LOC G21 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_tx_ctl}] ;# from U2.52
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#set_property -dict {LOC G19 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy_mdio}] ;# from U2.21
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#set_property -dict {LOC A18 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy_mdc}] ;# from U2.20
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create_clock -period 8.000 -name {phy_rx_clk} [get_ports {phy_rx_clk}]
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#set_false_path -to [get_ports {phy_mdio phy_mdc}]
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#set_output_delay 0 [get_ports {phy_mdio phy_mdc}]
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#set_false_path -from [get_ports {phy_mdio}]
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#set_input_delay 0 [get_ports {phy_mdio}]
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# QSPI flash
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#set_property -dict {LOC AM26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[0]}]
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#set_property -dict {LOC AN26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[1]}]
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#set_property -dict {LOC AL25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[2]}]
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#set_property -dict {LOC AM25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[3]}]
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#set_property -dict {LOC BF27 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_cs_n}]
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#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}]
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#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}]
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#set_false_path -from [get_ports {qspi_1_dq}]
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#set_input_delay 0 [get_ports {qspi_1_dq}]
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