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25 lines
996 B
Tcl
25 lines
996 B
Tcl
# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2019-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# RGMII PHY IF timing constraints
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foreach inst [get_cells -hier -regexp -filter {(ORIG_REF_NAME =~ "taxi_rgmii_phy_if(__\w+__\d+)?" ||
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REF_NAME =~ "taxi_rgmii_phy_if(__\w+__\d+)?")}] {
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puts "Inserting timing constraints for taxi_rgmii_phy_if instance $inst"
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# clock output
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set_property ASYNC_REG TRUE [get_cells $inst/clk_oddr_inst/oddr[0].oddr_inst]
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set src_clk [get_clocks -of_objects [get_pins $inst/rgmii_tx_clk_1_reg_reg/C]]
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set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}]
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set_max_delay -from [get_cells $inst/rgmii_tx_clk_1_reg_reg] -to [get_cells $inst/clk_oddr_inst/oddr[0].oddr_inst] -datapath_only [expr $src_clk_period/4]
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set_max_delay -from [get_cells $inst/rgmii_tx_clk_2_reg_reg] -to [get_cells $inst/clk_oddr_inst/oddr[0].oddr_inst] -datapath_only [expr $src_clk_period/4]
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}
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