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https://github.com/fpganinja/taxi.git
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136 lines
3.0 KiB
Systemverilog
136 lines
3.0 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream UART (RX)
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*/
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module taxi_uart_rx #
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(
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parameter DATA_W = 8
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4-Stream output (source)
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*/
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taxi_axis_if.src m_axis_rx,
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/*
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* UART interface
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*/
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input wire logic rxd,
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/*
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* Status
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*/
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output wire logic busy,
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output wire logic overrun_error,
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output wire logic frame_error,
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/*
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* Configuration
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*/
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input wire logic [15:0] prescale
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);
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// check configuration
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if (m_axis_rx.DATA_W != DATA_W)
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$fatal(0, "Error: Interface parameter DATA_W mismatch (instance %m)");
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logic [DATA_W-1:0] m_axis_tdata_reg = 0;
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logic m_axis_tvalid_reg = 0;
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logic rxd_reg = 1;
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logic busy_reg = 0;
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logic overrun_error_reg = 0;
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logic frame_error_reg = 0;
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logic [DATA_W-1:0] data_reg = 0;
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logic [18:0] prescale_reg = 0;
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logic [3:0] bit_cnt_reg = 0;
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assign m_axis_rx.tdata = m_axis_tdata_reg;
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assign m_axis_rx.tkeep = 1'b1;
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assign m_axis_rx.tstrb = m_axis_rx.tkeep;
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assign m_axis_rx.tvalid = m_axis_tvalid_reg;
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assign m_axis_rx.tlast = 1'b1;
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assign busy = busy_reg;
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assign overrun_error = overrun_error_reg;
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assign frame_error = frame_error_reg;
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always_ff @(posedge clk) begin
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rxd_reg <= rxd;
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overrun_error_reg <= 0;
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frame_error_reg <= 0;
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if (m_axis_rx.tvalid && m_axis_rx.tready) begin
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m_axis_tvalid_reg <= 0;
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end
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if (prescale_reg > 0) begin
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prescale_reg <= prescale_reg - 1;
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end else if (bit_cnt_reg > 0) begin
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if (bit_cnt_reg > DATA_W+1) begin
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if (!rxd_reg) begin
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bit_cnt_reg <= bit_cnt_reg - 1;
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prescale_reg <= {prescale, 3'd0}-1;
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end else begin
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bit_cnt_reg <= 0;
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prescale_reg <= 0;
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end
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end else if (bit_cnt_reg > 1) begin
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bit_cnt_reg <= bit_cnt_reg - 1;
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prescale_reg <= {prescale, 3'd0}-1;
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data_reg <= {rxd_reg, data_reg[DATA_W-1:1]};
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end else if (bit_cnt_reg == 1) begin
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bit_cnt_reg <= bit_cnt_reg - 1;
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if (rxd_reg) begin
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m_axis_tdata_reg <= data_reg;
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m_axis_tvalid_reg <= 1;
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overrun_error_reg <= m_axis_tvalid_reg;
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end else begin
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frame_error_reg <= 1;
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end
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end
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end else begin
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busy_reg <= 0;
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if (!rxd_reg) begin
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prescale_reg <= {prescale, 2'd0}-2;
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bit_cnt_reg <= DATA_W+2;
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data_reg <= 0;
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busy_reg <= 1;
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end
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end
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if (rst) begin
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m_axis_tdata_reg <= 0;
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m_axis_tvalid_reg <= 0;
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rxd_reg <= 1;
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prescale_reg <= 0;
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bit_cnt_reg <= 0;
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busy_reg <= 0;
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overrun_error_reg <= 0;
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frame_error_reg <= 0;
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end
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end
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endmodule
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`resetall
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